From 5fcdc65807517d6caa88e21651f793c765ae4a32 Mon Sep 17 00:00:00 2001 From: jquevremont Date: Sun, 28 Jan 2024 10:51:03 +0100 Subject: [PATCH] Fixed 'Title underline too short' warnings Signed-off-by: jquevremont --- docs/01_cva6_user/Programmer_View.rst | 6 +++--- docs/01_cva6_user/RISCV_Instructions_RVZbs.rst | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/01_cva6_user/Programmer_View.rst b/docs/01_cva6_user/Programmer_View.rst index b601ade72b..461e5b0c12 100644 --- a/docs/01_cva6_user/Programmer_View.rst +++ b/docs/01_cva6_user/Programmer_View.rst @@ -60,7 +60,7 @@ Notes: *The following tables detail the availability of extensions for the various CVA6 configurations:* CV32A60AX extensions -~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~ These extensions are available in CV32A60AX: @@ -128,7 +128,7 @@ Note: The addition of the H Extension is in the process. After that, HS, VS, and *The following tables detail the availability of privileges modes for the various CVA6 configurations:* CV32A60AX privilege modes -~~~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~~~~ These privilege modes are available in CV32A60AX: @@ -181,7 +181,7 @@ Notes for the integrator: *These are the addressing modes supported by the various CVA6 configurations:* CV32A60AX virtual memory -~~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~~~ CV32A60AX integrates an MMU and supports both the **Bare** and **Sv32** addressing modes. diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst index 06cf980356..85341b2a19 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst @@ -29,9 +29,9 @@ "CV32A60X", "Implemented extension" -============================ +============================== RVZbs: Single-bit instructions -============================ +============================== The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index. The following instructions (and pseudoinstructions) comprise the Zbs extension: