From 53d388071d51f4cca018e5f4ddf08ccacb45ecff Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Tue, 24 Oct 2023 17:29:47 +0200 Subject: [PATCH] Condition dcache_ctrl by MMU_PRESENT (#1568) When MMU is not present ldst does not request address translation, that's why related dcache_ctrl is not useful. Condition it to MMU_PRESENT to increase code coverage and decrease the gate count. --- core/cache_subsystem/wt_dcache.sv | 99 ++++++++++++++++++------------- 1 file changed, 59 insertions(+), 40 deletions(-) diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index f6dc3d0db7..e3a7c321b5 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -168,49 +168,68 @@ module wt_dcache // read controllers (LD unit and PTW/MMU) /////////////////////////////////////////////////////// - // note: last read port is used by the write buffer + // 0 is used by MMU, 1 by READ and 2 by WRITE access requests for (genvar k = 0; k < NumPorts - 1; k++) begin : gen_rd_ports // set these to high prio ports - assign rd_prio[k] = 1'b1; - - wt_dcache_ctrl #( - .CVA6Cfg(CVA6Cfg), - .RdTxId (RdAmoTxId) - ) i_wt_dcache_ctrl ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .cache_en_i (cache_en), - // reqs from core - .req_port_i (req_ports_i[k]), - .req_port_o (req_ports_o[k]), - // miss interface - .miss_req_o (miss_req[k]), - .miss_ack_i (miss_ack[k]), - .miss_we_o (miss_we[k]), - .miss_wdata_o (miss_wdata[k]), - .miss_wuser_o (miss_wuser[k]), - .miss_vld_bits_o(miss_vld_bits_o[k]), - .miss_paddr_o (miss_paddr[k]), - .miss_nc_o (miss_nc[k]), - .miss_size_o (miss_size[k]), - .miss_id_o (miss_id[k]), - .miss_replay_i (miss_replay[k]), - .miss_rtrn_vld_i(miss_rtrn_vld[k]), - // used to detect readout mux collisions - .wr_cl_vld_i (wr_cl_vld), - // cache mem interface - .rd_tag_o (rd_tag[k]), - .rd_idx_o (rd_idx[k]), - .rd_off_o (rd_off[k]), - .rd_req_o (rd_req[k]), - .rd_tag_only_o (rd_tag_only[k]), - .rd_ack_i (rd_ack[k]), - .rd_data_i (rd_data), - .rd_user_i (rd_user), - .rd_vld_bits_i (rd_vld_bits), - .rd_hit_oh_i (rd_hit_oh) - ); + if (k != 0 || MMU_PRESENT) begin + assign rd_prio[k] = 1'b1; + wt_dcache_ctrl #( + .CVA6Cfg(CVA6Cfg), + .RdTxId (RdAmoTxId) + ) i_wt_dcache_ctrl ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .cache_en_i (cache_en), + // reqs from core + .req_port_i (req_ports_i[k]), + .req_port_o (req_ports_o[k]), + // miss interface + .miss_req_o (miss_req[k]), + .miss_ack_i (miss_ack[k]), + .miss_we_o (miss_we[k]), + .miss_wdata_o (miss_wdata[k]), + .miss_wuser_o (miss_wuser[k]), + .miss_vld_bits_o(miss_vld_bits_o[k]), + .miss_paddr_o (miss_paddr[k]), + .miss_nc_o (miss_nc[k]), + .miss_size_o (miss_size[k]), + .miss_id_o (miss_id[k]), + .miss_replay_i (miss_replay[k]), + .miss_rtrn_vld_i(miss_rtrn_vld[k]), + // used to detect readout mux collisions + .wr_cl_vld_i (wr_cl_vld), + // cache mem interface + .rd_tag_o (rd_tag[k]), + .rd_idx_o (rd_idx[k]), + .rd_off_o (rd_off[k]), + .rd_req_o (rd_req[k]), + .rd_tag_only_o (rd_tag_only[k]), + .rd_ack_i (rd_ack[k]), + .rd_data_i (rd_data), + .rd_user_i (rd_user), + .rd_vld_bits_i (rd_vld_bits), + .rd_hit_oh_i (rd_hit_oh) + ); + end else begin + assign rd_prio[0] = 1'b0; + assign req_ports_o[0] = '0; + assign miss_req[0] = 1'b0; + assign miss_we[0] = 1'b0; + assign miss_wdata[0] = {{riscv::XLEN}{1'b0}}; + assign miss_wuser[0] = {{DCACHE_USER_WIDTH}{1'b0}}; + assign miss_vld_bits_o[0] = {{DCACHE_SET_ASSOC}{1'b0}}; + assign miss_paddr[0] = {{riscv::PLEN}{1'b0}}; + assign miss_nc[0] = 1'b0; + assign miss_size[0] = 3'b0; + assign miss_id[0] = {{CACHE_ID_WIDTH}{1'b0}}; + assign rd_tag[0] = {{DCACHE_TAG_WIDTH}{1'b0}}; + assign rd_idx[0] = {{DCACHE_CL_IDX_WIDTH}{1'b0}}; + assign rd_off[0] = {{DCACHE_OFFSET_WIDTH}{1'b0}}; + assign rd_req[0] = 1'b0; + assign rd_tag_only[0] = 1'b0; + end end + /////////////////////////////////////////////////////// // store unit controller ///////////////////////////////////////////////////////