From 51543db607a8cdf006e686e0af013ad8b132fe56 Mon Sep 17 00:00:00 2001 From: Valentin Thomazic Date: Mon, 4 Nov 2024 17:33:19 +0100 Subject: [PATCH] fix readme links (#2575) Fix dashboard and label links in README (see #2554 ) --- README.md | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/README.md b/README.md index 63c6ae6205..758a93fe14 100644 --- a/README.md +++ b/README.md @@ -1,9 +1,4 @@ -![Build Status](https://riscv-ci.pages.thales-invia.fr/dashboard/) - - -[CVA6 dashboard](util/toolchain-builder/README.md#Prerequisites) - -# CVA6 RISC-V CPU +# CVA6 RISC-V CPU [![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml) [![CVA6 dashboard](https://riscv-ci.pages.thales-invia.fr/dashboard/badge.svg)](https://riscv-ci.pages.thales-invia.fr/dashboard/) [![GitHub release](https://img.shields.io/github/release/openhwgroup/cva6?include_prereleases=&sort=semver&color=blue)](https://github.com/openhwgroup/cva6/releases/) CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13.