From 472308e50512323c97554f9a9c369ece871429d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Fri, 8 Mar 2024 14:58:48 +0100 Subject: [PATCH] format: apply Verible --- .../cva6_hpdcache_if_adapter.sv | 16 +++++----- .../cva6_hpdcache_subsystem.sv | 26 ++++++++-------- .../cva6_hpdcache_subsystem_axi_arbiter.sv | 12 ++++---- core/cache_subsystem/miss_handler.sv | 12 ++++---- core/cache_subsystem/std_cache_subsystem.sv | 6 ++-- core/cache_subsystem/std_nbdcache.sv | 6 ++-- core/cache_subsystem/wt_cache_subsystem.sv | 20 ++++++------- core/cache_subsystem/wt_dcache.sv | 10 +++---- core/cache_subsystem/wt_dcache_ctrl.sv | 2 +- core/cache_subsystem/wt_dcache_mem.sv | 6 ++-- core/cva6.sv | 30 +++++++++---------- core/ex_stage.sv | 4 +-- core/frontend/frontend.sv | 8 ++--- core/include/ariane_pkg.sv | 2 +- core/mmu_sv39/mmu.sv | 18 +++++------ 15 files changed, 89 insertions(+), 89 deletions(-) diff --git a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv index fc8d1ce93d..7f27d61b1d 100644 --- a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv +++ b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv @@ -15,10 +15,10 @@ module cva6_hpdcache_if_adapter // Parameters // {{{ #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type dcache_req_i_t = logic, - parameter type dcache_req_o_t = logic, - parameter bit is_load_port = 1'b1 + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter bit is_load_port = 1'b1 ) // }}} @@ -33,10 +33,10 @@ module cva6_hpdcache_if_adapter input hpdcache_pkg::hpdcache_req_sid_t hpdcache_req_sid_i, // Request/response ports from/to the CVA6 core - input dcache_req_i_t cva6_req_i, - output dcache_req_o_t cva6_req_o, - input ariane_pkg::amo_req_t cva6_amo_req_i, - output ariane_pkg::amo_resp_t cva6_amo_resp_o, + input dcache_req_i_t cva6_req_i, + output dcache_req_o_t cva6_req_o, + input ariane_pkg::amo_req_t cva6_amo_req_i, + output ariane_pkg::amo_resp_t cva6_amo_resp_o, // Request port to the L1 Dcache output logic hpdcache_req_valid_o, diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index 0802ba88ca..83a4be5da2 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -68,17 +68,17 @@ module cva6_hpdcache_subsystem output logic dcache_miss_o, // we missed on a ld/st // AMO interface - input ariane_pkg::amo_req_t dcache_amo_req_i, // from LSU - output ariane_pkg::amo_resp_t dcache_amo_resp_o, // to LSU + input ariane_pkg::amo_req_t dcache_amo_req_i, // from LSU + output ariane_pkg::amo_resp_t dcache_amo_resp_o, // to LSU // CMO interface - input cmo_req_t dcache_cmo_req_i, // from CMO FU - output cmo_rsp_t dcache_cmo_resp_o, // to CMO FU + input cmo_req_t dcache_cmo_req_i, // from CMO FU + output cmo_rsp_t dcache_cmo_resp_o, // to CMO FU // Request ports - input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // from LSU - output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to LSU + input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // from LSU + output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to LSU // Write Buffer status - output logic wbuffer_empty_o, - output logic wbuffer_not_ni_o, + output logic wbuffer_empty_o, + output logic wbuffer_not_ni_o, // Hardware memory prefetcher configuration input logic [NrHwPrefetchers-1:0] hwpf_base_set_i, @@ -119,7 +119,7 @@ module cva6_hpdcache_subsystem .icache_drsp_t(icache_drsp_t), .icache_req_t(icache_req_t), .icache_rtrn_t(icache_rtrn_t), - .RdTxId (ICACHE_RDTXID) + .RdTxId(ICACHE_RDTXID) ) i_cva6_icache ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -232,10 +232,10 @@ module cva6_hpdcache_subsystem assign dcache_req_ports[r] = dcache_req_ports_i[r]; cva6_hpdcache_if_adapter #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), - .is_load_port(1'b1) + .is_load_port (1'b1) ) i_cva6_hpdcache_load_if_adapter ( .clk_i, .rst_ni, @@ -260,10 +260,10 @@ module cva6_hpdcache_subsystem end cva6_hpdcache_if_adapter #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), - .is_load_port(1'b0) + .is_load_port (1'b0) ) i_cva6_hpdcache_store_if_adapter ( .clk_i, .rst_ni, diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv index 88728a0e0d..5af3ae6f66 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv @@ -49,13 +49,13 @@ module cva6_hpdcache_subsystem_axi_arbiter // Interfaces from/to I$ // {{{ - input logic icache_miss_valid_i, - output logic icache_miss_ready_o, - input icache_req_t icache_miss_i, - input hpdcache_mem_id_t icache_miss_id_i, + input logic icache_miss_valid_i, + output logic icache_miss_ready_o, + input icache_req_t icache_miss_i, + input hpdcache_mem_id_t icache_miss_id_i, - output logic icache_miss_resp_valid_o, - output icache_rtrn_t icache_miss_resp_o, + output logic icache_miss_resp_valid_o, + output icache_rtrn_t icache_miss_resp_o, // }}} // Interfaces from/to D$ diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv index ff977b8e15..223fc46bae 100644 --- a/core/cache_subsystem/miss_handler.sv +++ b/core/cache_subsystem/miss_handler.sv @@ -20,12 +20,12 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter int unsigned NR_PORTS = 4, - parameter type axi_req_t = logic, - parameter type axi_rsp_t = logic, - parameter type cache_line_t = logic, - parameter type cl_be_t = logic + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter int unsigned NR_PORTS = 4, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic, + parameter type cache_line_t = logic, + parameter type cl_be_t = logic ) ( input logic clk_i, input logic rst_ni, diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index 3dbcf43075..e5d077c7cc 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -76,7 +76,7 @@ module std_cache_subsystem axi_rsp_t axi_resp_data; cva6_icache_axi_wrapper #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), @@ -106,10 +106,10 @@ module std_cache_subsystem // Port 2: Accelerator // Port 3: Store Unit std_nbdcache #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), - .NumPorts (NumPorts), + .NumPorts(NumPorts), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t) ) i_nbdcache ( diff --git a/core/cache_subsystem/std_nbdcache.sv b/core/cache_subsystem/std_nbdcache.sv index f2e71fdaf8..466feaf205 100644 --- a/core/cache_subsystem/std_nbdcache.sv +++ b/core/cache_subsystem/std_nbdcache.sv @@ -53,7 +53,7 @@ module std_nbdcache logic dirty; // state array }; localparam type cl_be_t = struct packed { - logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array + logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] vldrty; // bit enable into state array (valid for a pair of dirty/valid bits) }; @@ -152,8 +152,8 @@ module std_nbdcache // Miss Handling Unit // ------------------ miss_handler #( - .CVA6Cfg (CVA6Cfg), - .NR_PORTS (NumPorts), + .CVA6Cfg(CVA6Cfg), + .NR_PORTS(NumPorts), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t), .cache_line_t(cache_line_t), diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index a8c336efa2..a79670cb7a 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -23,18 +23,18 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type icache_areq_t = logic, - parameter type icache_arsp_t = logic, - parameter type icache_dreq_t = logic, - parameter type icache_drsp_t = logic, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, + parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, parameter type icache_req_t = logic, parameter type icache_rtrn_t = logic, - parameter int unsigned NumPorts = 4, - parameter type noc_req_t = logic, - parameter type noc_resp_t = logic + parameter int unsigned NumPorts = 4, + parameter type noc_req_t = logic, + parameter type noc_resp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -145,7 +145,7 @@ module wt_cache_subsystem // they have equal prio and are RR arbited // Port 2 is write only and goes into the merging write buffer wt_dcache #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), .dcache_req_t(dcache_req_t), @@ -205,7 +205,7 @@ module wt_cache_subsystem ); `else wt_axi_adapter #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .axi_req_t(noc_req_t), .axi_rsp_t(noc_resp_t), .dcache_req_t(dcache_req_t), diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index d616f3c992..a1467ffbf0 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -128,10 +128,10 @@ module wt_dcache /////////////////////////////////////////////////////// wt_dcache_missunit #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .dcache_req_t(dcache_req_t), .dcache_rtrn_t(dcache_rtrn_t), - .AmoTxId (RdAmoTxId), + .AmoTxId(RdAmoTxId), .NumPorts(NumPorts) ) i_wt_dcache_missunit ( .clk_i (clk_i), @@ -194,7 +194,7 @@ module wt_dcache .CVA6Cfg(CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), - .RdTxId (RdAmoTxId) + .RdTxId(RdAmoTxId) ) i_wt_dcache_ctrl ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -317,9 +317,9 @@ module wt_dcache /////////////////////////////////////////////////////// wt_dcache_mem #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .wbuffer_t(wbuffer_t), - .NumPorts(NumPorts) + .NumPorts (NumPorts) ) i_wt_dcache_mem ( .clk_i (clk_i), .rst_ni (rst_ni), diff --git a/core/cache_subsystem/wt_dcache_ctrl.sv b/core/cache_subsystem/wt_dcache_ctrl.sv index ad76083d67..237cac8ad8 100644 --- a/core/cache_subsystem/wt_dcache_ctrl.sv +++ b/core/cache_subsystem/wt_dcache_ctrl.sv @@ -20,7 +20,7 @@ module wt_dcache_ctrl parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, - parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1 + parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1 ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/core/cache_subsystem/wt_dcache_mem.sv b/core/cache_subsystem/wt_dcache_mem.sv index c8b55463fa..90bf80a2d6 100644 --- a/core/cache_subsystem/wt_dcache_mem.sv +++ b/core/cache_subsystem/wt_dcache_mem.sv @@ -30,9 +30,9 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type wbuffer_t = logic, - parameter int unsigned NumPorts = 3 + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type wbuffer_t = logic, + parameter int unsigned NumPorts = 3 ) ( input logic clk_i, input logic rst_ni, diff --git a/core/cva6.sv b/core/cva6.sv index 3ca2a0a18c..cb3b065362 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -1205,21 +1205,21 @@ module cva6 // note: this only works with one cacheable region // not as important since this cache subsystem is about to be // deprecated - .CVA6Cfg (CVA6Cfg), - .icache_areq_t(icache_areq_t), - .icache_arsp_t(icache_arsp_t), - .icache_dreq_t(icache_dreq_t), - .icache_drsp_t(icache_drsp_t), + .CVA6Cfg (CVA6Cfg), + .icache_areq_t (icache_areq_t), + .icache_arsp_t (icache_arsp_t), + .icache_dreq_t (icache_dreq_t), + .icache_drsp_t (icache_drsp_t), .icache_req_t (icache_req_t), .icache_rtrn_t (icache_rtrn_t), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), - .NumPorts (NumPorts), - .axi_ar_chan_t(axi_ar_chan_t), - .axi_aw_chan_t(axi_aw_chan_t), - .axi_w_chan_t (axi_w_chan_t), - .axi_req_t (noc_req_t), - .axi_rsp_t (noc_resp_t) + .NumPorts (NumPorts), + .axi_ar_chan_t (axi_ar_chan_t), + .axi_aw_chan_t (axi_aw_chan_t), + .axi_w_chan_t (axi_w_chan_t), + .axi_req_t (noc_req_t), + .axi_rsp_t (noc_resp_t) ) i_cache_subsystem ( // to D$ .clk_i (clk_i), @@ -1510,11 +1510,11 @@ module cva6 //RVFI INSTR cva6_rvfi_probes #( - .CVA6Cfg (CVA6Cfg), - .exception_t (exception_t), + .CVA6Cfg (CVA6Cfg), + .exception_t (exception_t), .scoreboard_entry_t(scoreboard_entry_t), - .lsu_ctrl_t (lsu_ctrl_t), - .rvfi_probes_t(rvfi_probes_t) + .lsu_ctrl_t (lsu_ctrl_t), + .rvfi_probes_t (rvfi_probes_t) ) i_cva6_rvfi_probes ( .flush_i (flush_ctrl_if), diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 6340f2b186..d168ad630a 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -240,7 +240,7 @@ module ex_stage assign alu_data = (alu_valid_i | branch_valid_i) ? fu_data_i : '0; alu #( - .CVA6Cfg(CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .fu_data_t(fu_data_t) ) alu_i ( .clk_i, @@ -346,7 +346,7 @@ module ex_stage assign fpu_data = fpu_valid_i ? fu_data_i : '0; fpu_wrap #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .exception_t(exception_t), .fu_data_t(fu_data_t) ) fpu_i ( diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 8e0f822792..587887c051 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -455,10 +455,10 @@ module frontend .clk_i, .rst_ni, .flush_bp_i(flush_bp_i), - .push_i (ras_push), - .pop_i (ras_pop), - .data_i (ras_update), - .data_o (ras_predict) + .push_i(ras_push), + .pop_i(ras_pop), + .data_i(ras_update), + .data_o(ras_predict) ); end diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 4b3a0a3553..7240f3f1bf 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -723,7 +723,7 @@ package ariane_pkg; riscv::xlen_t acc_cons_q; riscv::pmpcfg_t [15:0] pmpcfg_q; logic [15:0][riscv::PLEN-3:0] pmpaddr_q; - } rvfi_probes_csr_t; + } rvfi_probes_csr_t; // RVFI CSR structure typedef struct packed { diff --git a/core/mmu_sv39/mmu.sv b/core/mmu_sv39/mmu.sv index 1fdb3f528e..6aecb2b39f 100644 --- a/core/mmu_sv39/mmu.sv +++ b/core/mmu_sv39/mmu.sv @@ -23,9 +23,9 @@ module mmu parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, - parameter type dcache_req_i_t = logic, - parameter type dcache_req_o_t = logic, - parameter type exception_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, parameter int unsigned INSTR_TLB_ENTRIES = 4, parameter int unsigned DATA_TLB_ENTRIES = 4, parameter int unsigned ASID_WIDTH = 1 @@ -114,10 +114,10 @@ module mmu tlb #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .tlb_update_t(tlb_update_t), - .TLB_ENTRIES(INSTR_TLB_ENTRIES), - .ASID_WIDTH (ASID_WIDTH) + .TLB_ENTRIES (INSTR_TLB_ENTRIES), + .ASID_WIDTH (ASID_WIDTH) ) i_itlb ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -138,10 +138,10 @@ module mmu ); tlb #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .tlb_update_t(tlb_update_t), - .TLB_ENTRIES(DATA_TLB_ENTRIES), - .ASID_WIDTH (ASID_WIDTH) + .TLB_ENTRIES (DATA_TLB_ENTRIES), + .ASID_WIDTH (ASID_WIDTH) ) i_dtlb ( .clk_i (clk_i), .rst_ni (rst_ni),