From 46e9d5a7fcf2777d7e34fb941e6e027fea9752b6 Mon Sep 17 00:00:00 2001 From: Cyprien Heusse <46382251+cyprienh@users.noreply.github.com> Date: Thu, 30 May 2024 18:47:39 +0200 Subject: [PATCH] 32 bits WB cache (#2170) --- core/cache_subsystem/cache_ctrl.sv | 37 ++++++++++++------- .../tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv | 9 ++--- 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/core/cache_subsystem/cache_ctrl.sv b/core/cache_subsystem/cache_ctrl.sv index 02899e029a..f787937257 100644 --- a/core/cache_subsystem/cache_ctrl.sv +++ b/core/cache_subsystem/cache_ctrl.sv @@ -82,10 +82,10 @@ module cache_ctrl logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] index; logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag; logic [CVA6Cfg.DcacheIdWidth-1:0] id; - logic [7:0] be; + logic [(CVA6Cfg.XLEN/8)-1:0] be; logic [1:0] size; logic we; - logic [63:0] wdata; + logic [CVA6Cfg.XLEN-1:0] wdata; logic bypass; logic killed; } mem_req_t; @@ -112,9 +112,12 @@ module cache_ctrl // -------------- always_comb begin : cache_ctrl_fsm automatic logic [$clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset; + automatic logic [$clog2(CVA6Cfg.AxiDataWidth)-1:0] axi_offset; // incoming cache-line -> this is needed as synthesis is not supporting +: indexing in a multi-dimensional array - // cache-line offset -> multiple of 64 - cl_offset = mem_req_q.index[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:3] << 6; // shift by 6 to the left + // cache-line offset -> multiple of XLEN + cl_offset = mem_req_q.index[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:$clog2(CVA6Cfg.XLEN/8)] << + $clog2(CVA6Cfg.XLEN); // shift by log2(XLEN) to the left + axi_offset = '0; // default assignments state_d = state_q; mem_req_d = mem_req_q; @@ -135,6 +138,11 @@ module cache_ctrl mem_req_d.killed |= req_port_i.kill_req; + if (CVA6Cfg.XLEN == 32) begin + axi_offset = mem_req_q.index[$clog2(CVA6Cfg.AxiDataWidth/8)-1:$clog2(CVA6Cfg.XLEN/8)] << + $clog2(CVA6Cfg.XLEN); + end + case (state_q) IDLE: begin @@ -211,7 +219,7 @@ module cache_ctrl end // this is timing critical - req_port_o.data_rdata = cl_i[cl_offset+:64]; + req_port_o.data_rdata = cl_i[cl_offset+:CVA6Cfg.XLEN]; // report data for a read if (!mem_req_q.we) begin @@ -307,14 +315,15 @@ module cache_ctrl addr_o = mem_req_q.index; we_o = 1'b1; - be_o.vldrty = hit_way_q; + be_o.vldrty = hit_way_q; // set the correct byte enable - be_o.data[cl_offset>>3+:8] = mem_req_q.be; - data_o.data[cl_offset+:64] = mem_req_q.wdata; + be_o.data[cl_offset>>3+:CVA6Cfg.XLEN/8] = mem_req_q.be; + data_o.data[cl_offset+:CVA6Cfg.XLEN] = mem_req_q.wdata; + data_o.tag = mem_req_d.tag; // ~> change the state - data_o.dirty = 1'b1; - data_o.valid = 1'b1; + data_o.dirty = 1'b1; + data_o.valid = 1'b1; // got a grant ~> this is finished now if (gnt_i) begin @@ -357,10 +366,10 @@ module cache_ctrl miss_req_o.valid = 1'b1; miss_req_o.bypass = mem_req_q.bypass; miss_req_o.addr = {mem_req_q.tag, mem_req_q.index}; - miss_req_o.be = mem_req_q.be; + miss_req_o.be[axi_offset>>3+:CVA6Cfg.XLEN/8] = mem_req_q.be; miss_req_o.size = mem_req_q.size; miss_req_o.we = mem_req_q.we; - miss_req_o.wdata = mem_req_q.wdata; + miss_req_o.wdata[axi_offset+:CVA6Cfg.XLEN] = mem_req_q.wdata; // got a grant so go to valid if (bypass_gnt_i) begin @@ -399,7 +408,7 @@ module cache_ctrl if (critical_word_valid_i) begin req_port_o.data_rvalid = ~mem_req_q.killed; - req_port_o.data_rdata = critical_word_i; + req_port_o.data_rdata = critical_word_i[axi_offset+:CVA6Cfg.XLEN]; // we can make another request if (req_port_i.data_req && !flush_i) begin // save index, be and we @@ -428,7 +437,7 @@ module cache_ctrl WAIT_REFILL_VALID: begin // got a valid answer if (bypass_valid_i) begin - req_port_o.data_rdata = bypass_data_i; + req_port_o.data_rdata = bypass_data_i[axi_offset+:CVA6Cfg.XLEN]; req_port_o.data_rvalid = ~mem_req_q.killed; state_d = IDLE; end diff --git a/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv b/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv index d26138aeb8..a06a6e418c 100644 --- a/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv +++ b/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv @@ -58,9 +58,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; - localparam CVA6ConfigInstrTlbEntries = 2; - localparam CVA6ConfigDataTlbEntries = 2; - localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; @@ -149,8 +146,10 @@ package cva6_config_pkg; WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), FetchUserEn: unsigned'(CVA6ConfigFetchUserEn), - InstrTlbEntries: int'(CVA6ConfigInstrTlbEntries), - DataTlbEntries: int'(CVA6ConfigDataTlbEntries), + InstrTlbEntries: int'(2), + DataTlbEntries: int'(2), + UseSharedTlb: bit'(1), + SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)