From 4619a67fc65d8bc31f1f9630f73bfe545b731322 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me?= <124148386+cathales@users.noreply.github.com> Date: Thu, 7 Nov 2024 16:51:46 +0100 Subject: [PATCH] expand glob port maps (#2585) Expands all glob port maps in the core/ directory of this repository except the core/cache_subsystem/ directory, despite the glob port maps in core/cache_subsystem/miss_handler.sv and core/cache_subsystem/std_nbdcache.sv. Also reorders port maps to keep the same order as port declarations. --- core/acc_dispatcher.sv | 12 +- core/cache_subsystem/std_cache_subsystem.sv | 10 +- core/cache_subsystem/tag_cmp.sv | 14 +-- core/commit_stage.sv | 6 +- core/controller.sv | 4 + core/csr_regfile.sv | 2 - core/cva6.sv | 119 ++++++++++---------- core/cva6_mmu/cva6_mmu.sv | 43 +++++-- core/cva6_mmu/cva6_ptw.sv | 2 - core/issue_read_operands.sv | 21 ++-- core/issue_stage.sv | 80 +++++++++---- core/load_store_unit.sv | 40 +++++-- core/scoreboard.sv | 3 + 13 files changed, 220 insertions(+), 136 deletions(-) diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 5091159862..d00e7eb5f0 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -302,18 +302,18 @@ module acc_dispatcher assign acc_valid_o = acc_resp_i.resp_valid; assign acc_exception_o = acc_resp_i.exception; // Unpack the accelerator response - assign acc_fflags_valid_o = acc_resp_i.fflags_valid; - assign acc_fflags_o = acc_resp_i.fflags; + assign acc_fflags_valid_o = acc_resp_i.fflags_valid; + assign acc_fflags_o = acc_resp_i.fflags; // Always ready to receive responses assign acc_req_o.resp_ready = 1'b1; // Signal dispatched load/store to issue stage - assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD); - assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE); + assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD); + assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE); // Cache invalidation - assign inval_valid_o = acc_resp_i.inval_valid; - assign inval_addr_o = acc_resp_i.inval_addr; + assign inval_valid_o = acc_resp_i.inval_valid; + assign inval_addr_o = acc_resp_i.inval_addr; /************************** * Accelerator commit * diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index ed0bd65834..7adb935c27 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -193,7 +193,7 @@ module std_cache_subsystem .flush_i (1'b0), .testmode_i(1'b0), .full_o (w_fifo_full), - .empty_o (), // leave open + .empty_o (), // leave open .usage_o (w_fifo_usage), .data_i (w_select), // a new transaction was requested and granted @@ -204,14 +204,14 @@ module std_cache_subsystem .pop_i (w_fifo_pop) ); - always_ff @( posedge clk_i or negedge rst_ni ) begin : aw_lock_reg + always_ff @(posedge clk_i or negedge rst_ni) begin : aw_lock_reg if (~rst_ni) aw_lock_q <= 1'b0; - else aw_lock_q <= aw_lock_d; + else aw_lock_q <= aw_lock_d; end assign w_fifo_push = ~aw_lock_q & axi_req_o.aw_valid; - assign w_fifo_pop = axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last; - assign aw_lock_d = ~axi_resp_i.aw_ready & (axi_req_o.aw_valid | aw_lock_q); + assign w_fifo_pop = axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last; + assign aw_lock_d = ~axi_resp_i.aw_ready & (axi_req_o.aw_valid | aw_lock_q); // In fall-through mode, the empty_o will be low when push_i is high (on zero usage). // We do not want this here. Also, usage_o is missing the MSB, so on full fifo, usage_o is zero. diff --git a/core/cache_subsystem/tag_cmp.sv b/core/cache_subsystem/tag_cmp.sv index b1293884a9..38d1ce1145 100644 --- a/core/cache_subsystem/tag_cmp.sv +++ b/core/cache_subsystem/tag_cmp.sv @@ -85,13 +85,13 @@ module tag_cmp #( `ifndef SYNTHESIS `ifndef VERILATOR - // assert that cache only hits on one way - // this only needs to be checked one cycle after all ways have been requested - onehot : - assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o)) - else begin - $fatal(1, "Hit should be one-hot encoded"); - end + // assert that cache only hits on one way + // this only needs to be checked one cycle after all ways have been requested + onehot : + assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o)) + else begin + $fatal(1, "Hit should be one-hot encoded"); + end `endif `endif diff --git a/core/commit_stage.sv b/core/commit_stage.sv index c193c9154e..8984b7d626 100644 --- a/core/commit_stage.sv +++ b/core/commit_stage.sv @@ -60,10 +60,10 @@ module commit_stage output logic [CVA6Cfg.XLEN-1:0] csr_wdata_o, // Data to read from CSR - CSR_REGFILE input logic [CVA6Cfg.XLEN-1:0] csr_rdata_i, - // Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE - input exception_t csr_exception_i, // Write the fflags CSR - CSR_REGFILE output logic csr_write_fflags_o, + // Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE + input exception_t csr_exception_i, // Commit the pending store - EX_STAGE output logic commit_lsu_o, // Commit buffer of LSU is ready - EX_STAGE @@ -84,7 +84,9 @@ module commit_stage output logic flush_commit_o, // Flush TLBs and pipeline - CONTROLLER output logic sfence_vma_o, + // TO_BE_COMPLETED - CONTROLLER output logic hfence_vvma_o, + // TO_BE_COMPLETED - CONTROLLER output logic hfence_gvma_o ); diff --git a/core/controller.sv b/core/controller.sv index a5edcf131a..ebd0e0c75d 100644 --- a/core/controller.sv +++ b/core/controller.sv @@ -45,7 +45,9 @@ module controller input logic flush_dcache_ack_i, // Flush TLBs - EX_STAGE output logic flush_tlb_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic flush_tlb_vvma_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic flush_tlb_gvma_o, // Halt request from CSR (WFI instruction) - CSR_REGFILE input logic halt_csr_i, @@ -69,7 +71,9 @@ module controller input logic fence_i, // We got an instruction to flush the TLBs and pipeline - COMMIT_STAGE input logic sfence_vma_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic hfence_vvma_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic hfence_gvma_i, // Flush request from commit stage - COMMIT_STAGE input logic flush_commit_i, diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 0c996e2da3..63046531d3 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -42,7 +42,6 @@ module csr_regfile input logic [CVA6Cfg.VLEN-1:0] boot_addr_i, // Hart id in a multicore environment (reflected in a CSR) - SUBSYSTEM input logic [CVA6Cfg.XLEN-1:0] hart_id_i, - // we are taking an exception // We've got an exception from the commit stage, take it - COMMIT_STAGE input exception_t ex_i, // Operation to perform on the CSR file - COMMIT_STAGE @@ -153,7 +152,6 @@ module csr_regfile output logic dcache_en_o, // Accelerator memory consistent mode - ACC_DISPATCHER output logic acc_cons_en_o, - // Performance Counter // read/write address to performance counter module - PERF_COUNTERS output logic [11:0] perf_addr_o, // write data to performance counter module - PERF_COUNTERS diff --git a/core/cva6.sv b/core/cva6.sv index c845a644d0..4c6b3bf7d6 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -643,25 +643,26 @@ module cva6 .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t) ) i_frontend ( - .flush_i (flush_ctrl_if), // not entirely correct + .clk_i, + .rst_ni, + .boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]), .flush_bp_i (1'b0), + .flush_i (flush_ctrl_if), // not entirely correct .halt_i (halt_ctrl), - .debug_mode_i (debug_mode), - .boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]), - .icache_dreq_i (icache_dreq_cache_if), - .icache_dreq_o (icache_dreq_if_cache), - .resolved_branch_i (resolved_branch), - .pc_commit_i (pc_commit), .set_pc_commit_i (set_pc_ctrl_pcgen), - .set_debug_pc_i (set_debug_pc), - .epc_i (epc_commit_pcgen), + .pc_commit_i (pc_commit), + .ex_valid_i (ex_commit.valid), + .resolved_branch_i (resolved_branch), .eret_i (eret), + .epc_i (epc_commit_pcgen), .trap_vector_base_i (trap_vector_base_commit_pcgen), - .ex_valid_i (ex_commit.valid), + .set_debug_pc_i (set_debug_pc), + .debug_mode_i (debug_mode), + .icache_dreq_o (icache_dreq_if_cache), + .icache_dreq_i (icache_dreq_cache_if), .fetch_entry_o (fetch_entry_if_id), .fetch_entry_valid_o(fetch_valid_if_id), - .fetch_entry_ready_i(fetch_ready_id_if), - .* + .fetch_entry_ready_i(fetch_ready_id_if) ); // --------- @@ -857,8 +858,8 @@ module cva6 .issue_instr_o (issue_instr_id_acc), .issue_instr_hs_o (issue_instr_hs_id_acc), // Commit - .resolved_branch_i (resolved_branch), .trans_id_i (trans_id_ex_id), + .resolved_branch_i (resolved_branch), .wbdata_i (wbdata_ex_id), .ex_ex_i (ex_ex_ex_id), .wt_valid_i (wt_valid_ex_id), @@ -876,8 +877,7 @@ module cva6 .stall_issue_o (stall_issue), //RVFI .rvfi_issue_pointer_o (rvfi_issue_pointer), - .rvfi_commit_pointer_o(rvfi_commit_pointer), - .* + .rvfi_commit_pointer_o(rvfi_commit_pointer) ); // --------- @@ -1043,30 +1043,29 @@ module cva6 .commit_drop_i (commit_drop_id_commit), .commit_ack_o (commit_ack_commit_id), .commit_macro_ack_o(commit_macro_ack), - .no_st_pending_i (no_st_pending_commit), .waddr_o (waddr_commit_id), .wdata_o (wdata_commit_id), .we_gpr_o (we_gpr_commit_id), .we_fpr_o (we_fpr_commit_id), - .commit_lsu_o (lsu_commit_commit_ex), - .commit_lsu_ready_i(lsu_commit_ready_ex_commit), - .commit_tran_id_o (lsu_commit_trans_id), - .amo_valid_commit_o(amo_valid_commit), .amo_resp_i (amo_resp), - .commit_csr_o (csr_commit_commit_ex), .pc_o (pc_commit), .csr_op_o (csr_op_commit_csr), .csr_wdata_o (csr_wdata_commit_csr), .csr_rdata_i (csr_rdata_csr_commit), .csr_write_fflags_o(csr_write_fflags_commit_cs), .csr_exception_i (csr_exception_csr_commit), + .commit_lsu_o (lsu_commit_commit_ex), + .commit_lsu_ready_i(lsu_commit_ready_ex_commit), + .commit_tran_id_o (lsu_commit_trans_id), + .amo_valid_commit_o(amo_valid_commit), + .no_st_pending_i (no_st_pending_commit), + .commit_csr_o (csr_commit_commit_ex), .fence_i_o (fence_i_commit_controller), .fence_o (fence_commit_controller), + .flush_commit_o (flush_commit), .sfence_vma_o (sfence_vma_commit_controller), .hfence_vvma_o (hfence_vvma_commit_controller), - .hfence_gvma_o (hfence_gvma_commit_controller), - .flush_commit_o (flush_commit), - .* + .hfence_gvma_o (hfence_gvma_commit_controller) ); assign commit_ack = commit_macro_ack & ~commit_drop_id_commit; @@ -1082,6 +1081,9 @@ module cva6 .rvfi_probes_csr_t (rvfi_probes_csr_t), .MHPMCounterNum (MHPMCounterNum) ) csr_regfile_i ( + .clk_i, + .rst_ni, + .time_irq_i, .flush_o (flush_csr_ctrl), .halt_csr_o (halt_csr_ctrl), .commit_instr_i (commit_instr_id_commit), @@ -1090,17 +1092,16 @@ module cva6 .hart_id_i (hart_id_i[CVA6Cfg.XLEN-1:0]), .ex_i (ex_commit), .csr_op_i (csr_op_commit_csr), - .csr_write_fflags_i (csr_write_fflags_commit_cs), - .dirty_fp_state_i (dirty_fp_state), - .dirty_v_state_i (dirty_v_state), .csr_addr_i (csr_addr_ex_csr), .csr_wdata_i (csr_wdata_commit_csr), .csr_rdata_o (csr_rdata_csr_commit), + .dirty_fp_state_i (dirty_fp_state), + .csr_write_fflags_i (csr_write_fflags_commit_cs), + .dirty_v_state_i (dirty_v_state), .pc_i (pc_commit), .csr_exception_o (csr_exception_csr_commit), .epc_o (epc_commit_pcgen), .eret_o (eret), - .set_debug_pc_o (set_debug_pc), .trap_vector_base_o (trap_vector_base_commit_pcgen), .priv_lvl_o (priv_lvl), .v_o (v), @@ -1113,13 +1114,13 @@ module cva6 .fprec_o (fprec_csr_ex), .vs_o (vs), .irq_ctrl_o (irq_ctrl_csr_id), - .ld_st_priv_lvl_o (ld_st_priv_lvl_csr_ex), - .ld_st_v_o (ld_st_v_csr_ex), - .csr_hs_ld_st_inst_i (csr_hs_ld_st_inst_ex), .en_translation_o (enable_translation_csr_ex), .en_g_translation_o (enable_g_translation_csr_ex), .en_ld_st_translation_o (en_ld_st_translation_csr_ex), .en_ld_st_g_translation_o(en_ld_st_g_translation_csr_ex), + .ld_st_priv_lvl_o (ld_st_priv_lvl_csr_ex), + .ld_st_v_o (ld_st_v_csr_ex), + .csr_hs_ld_st_inst_i (csr_hs_ld_st_inst_ex), .sum_o (sum_csr_ex), .vs_sum_o (vs_sum_csr_ex), .mxr_o (mxr_csr_ex), @@ -1130,6 +1131,10 @@ module cva6 .vs_asid_o (vs_asid_csr_ex), .hgatp_ppn_o (hgatp_ppn_csr_ex), .vmid_o (vmid_csr_ex), + .irq_i, + .ipi_i, + .debug_req_i, + .set_debug_pc_o (set_debug_pc), .tvm_o (tvm_csr_id), .tw_o (tw_csr_id), .vtw_o (vtw_csr_id), @@ -1137,8 +1142,8 @@ module cva6 .hu_o (hu), .debug_mode_o (debug_mode), .single_step_o (single_step_csr_commit), - .dcache_en_o (dcache_en_csr_nbdcache), .icache_en_o (icache_en_csr), + .dcache_en_o (dcache_en_csr_nbdcache), .acc_cons_en_o (acc_cons_en_csr), .perf_addr_o (addr_csr_perf), .perf_data_o (data_csr_perf), @@ -1148,12 +1153,7 @@ module cva6 .pmpaddr_o (pmpaddr), .mcountinhibit_o (mcountinhibit_csr_perf), //RVFI - .rvfi_csr_o (rvfi_csr), - .debug_req_i, - .ipi_i, - .irq_i, - .time_irq_i, - .* + .rvfi_csr_o (rvfi_csr) ); // ------------------------ @@ -1211,40 +1211,39 @@ module cva6 .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t) ) controller_i ( + .clk_i, + .rst_ni, // virtualization mode .v_i (v), // flush ports .set_pc_commit_o (set_pc_ctrl_pcgen), - .flush_unissued_instr_o(flush_unissued_instr_ctrl_id), .flush_if_o (flush_ctrl_if), + .flush_unissued_instr_o(flush_unissued_instr_ctrl_id), .flush_id_o (flush_ctrl_id), .flush_ex_o (flush_ctrl_ex), .flush_bp_o (flush_ctrl_bp), + .flush_icache_o (icache_flush_ctrl_cache), + .flush_dcache_o (dcache_flush_ctrl_cache), + .flush_dcache_ack_i (dcache_flush_ack_cache_ctrl), .flush_tlb_o (flush_tlb_ctrl_ex), .flush_tlb_vvma_o (flush_tlb_vvma_ctrl_ex), .flush_tlb_gvma_o (flush_tlb_gvma_ctrl_ex), - .flush_dcache_o (dcache_flush_ctrl_cache), - .flush_dcache_ack_i (dcache_flush_ack_cache_ctrl), - - .halt_csr_i (halt_csr_ctrl), - .halt_acc_i (halt_acc_ctrl), - .halt_o (halt_ctrl), + .halt_csr_i (halt_csr_ctrl), + .halt_acc_i (halt_acc_ctrl), + .halt_o (halt_ctrl), // control ports - .eret_i (eret), - .ex_valid_i (ex_commit.valid), - .set_debug_pc_i (set_debug_pc), - .flush_csr_i (flush_csr_ctrl), - .resolved_branch_i(resolved_branch), - .fence_i_i (fence_i_commit_controller), - .fence_i (fence_commit_controller), - .sfence_vma_i (sfence_vma_commit_controller), - .hfence_vvma_i (hfence_vvma_commit_controller), - .hfence_gvma_i (hfence_gvma_commit_controller), - .flush_commit_i (flush_commit), - .flush_acc_i (flush_acc), - - .flush_icache_o(icache_flush_ctrl_cache), - .* + .eret_i (eret), + .ex_valid_i (ex_commit.valid), + .set_debug_pc_i (set_debug_pc), + .resolved_branch_i (resolved_branch), + .flush_csr_i (flush_csr_ctrl), + .fence_i_i (fence_i_commit_controller), + .fence_i (fence_commit_controller), + .sfence_vma_i (sfence_vma_commit_controller), + .hfence_vvma_i (hfence_vvma_commit_controller), + .hfence_gvma_i (hfence_gvma_commit_controller), + .flush_commit_i (flush_commit), + .flush_acc_i (flush_acc) ); // ------------------- diff --git a/core/cva6_mmu/cva6_mmu.sv b/core/cva6_mmu/cva6_mmu.sv index 364c2ef269..9afe90c17e 100644 --- a/core/cva6_mmu/cva6_mmu.sv +++ b/core/cva6_mmu/cva6_mmu.sv @@ -193,12 +193,15 @@ module cva6_mmu .lu_asid_i (itlb_lu_asid), .lu_vmid_i (vmid_i), .lu_vaddr_i (icache_areq_i.fetch_vaddr), + .lu_gpaddr_o (itlb_gpaddr), .lu_content_o (itlb_content), .lu_g_content_o(itlb_g_content), - .lu_gpaddr_o (itlb_gpaddr), + .asid_to_be_flushed_i, + .vmid_to_be_flushed_i, + .vaddr_to_be_flushed_i, + .gpaddr_to_be_flushed_i, .lu_is_page_o (itlb_is_page), - .lu_hit_o (itlb_lu_hit), - .* + .lu_hit_o (itlb_lu_hit) ); cva6_tlb #( @@ -221,12 +224,15 @@ module cva6_mmu .lu_asid_i (itlb_lu_asid), .lu_vmid_i (vmid_i), .lu_vaddr_i (lsu_vaddr_i), + .lu_gpaddr_o (dtlb_gpaddr), .lu_content_o (dtlb_content), .lu_g_content_o(dtlb_g_content), - .lu_gpaddr_o (dtlb_gpaddr), + .asid_to_be_flushed_i, + .vmid_to_be_flushed_i, + .vaddr_to_be_flushed_i, + .gpaddr_to_be_flushed_i, .lu_is_page_o (dtlb_is_page), - .lu_hit_o (dtlb_lu_hit), - .* + .lu_hit_o (dtlb_lu_hit) ); @@ -290,6 +296,7 @@ module cva6_mmu ) i_ptw ( .clk_i (clk_i), .rst_ni(rst_ni), + .flush_i, .ptw_active_o (ptw_active), .walking_instr_o (walking_instr), @@ -297,17 +304,27 @@ module cva6_mmu .ptw_error_at_g_st_o (ptw_error_at_g_st), .ptw_err_at_g_int_st_o (ptw_err_at_g_int_st), .ptw_access_exception_o(ptw_access_exception), + .enable_translation_i, + .enable_g_translation_i, + .en_ld_st_translation_i, + .en_ld_st_g_translation_i, + .v_i, + .ld_st_v_i, + .hlvx_inst_i (hlvx_inst_i), .lsu_is_store_i(lsu_is_store_i), // PTW memory interface .req_port_i (req_port_i), .req_port_o (req_port_o), - .update_vaddr_o(update_vaddr), - // to Shared TLB, update logic .shared_tlb_update_o(update_shared_tlb), + .update_vaddr_o(update_vaddr), + + .asid_i, + .vs_asid_i, + .vmid_i, // from shared TLB // did we miss? @@ -317,7 +334,11 @@ module cva6_mmu .itlb_req_i(itlb_req), - .hlvx_inst_i(hlvx_inst_i), + .satp_ppn_i, + .vsatp_ppn_i, + .hgatp_ppn_i, + .mxr_i, + .vmxr_i, // Performance counters .shared_tlb_miss_o(shared_tlb_miss), //open for now @@ -326,9 +347,7 @@ module cva6_mmu .pmpcfg_i (pmpcfg_i), .pmpaddr_i (pmpaddr_i), .bad_paddr_o(ptw_bad_paddr), - .bad_gpaddr_o(ptw_bad_gpaddr), - .* - + .bad_gpaddr_o(ptw_bad_gpaddr) ); //----------------------- diff --git a/core/cva6_mmu/cva6_ptw.sv b/core/cva6_mmu/cva6_ptw.sv index f7117d62ee..c4713701dd 100644 --- a/core/cva6_mmu/cva6_ptw.sv +++ b/core/cva6_mmu/cva6_ptw.sv @@ -83,12 +83,10 @@ module cva6_ptw output logic shared_tlb_miss_o, // PMP - input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, output logic [CVA6Cfg.PLEN-1:0] bad_paddr_o, output logic [CVA6Cfg.GPLEN-1:0] bad_gpaddr_o - ); // input registers diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index f80bc3bf14..032774b427 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -28,7 +28,6 @@ module issue_read_operands parameter type x_issue_resp_t = logic, parameter type x_register_t = logic, parameter type x_commit_t = logic - ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -984,13 +983,14 @@ module issue_read_operands .NR_READ_PORTS(CVA6Cfg.NrRgprPorts), .ZERO_REG_ZERO(1) ) i_ariane_regfile_fpga ( + .clk_i, + .rst_ni, .test_en_i(1'b0), .raddr_i (raddr_pack), .rdata_o (rdata), .waddr_i (waddr_pack), .wdata_i (wdata_pack), - .we_i (we_pack), - .* + .we_i (we_pack) ); end else begin : gen_asic_regfile ariane_regfile #( @@ -999,13 +999,14 @@ module issue_read_operands .NR_READ_PORTS(CVA6Cfg.NrRgprPorts), .ZERO_REG_ZERO(1) ) i_ariane_regfile ( + .clk_i, + .rst_ni, .test_en_i(1'b0), .raddr_i (raddr_pack), .rdata_o (rdata), .waddr_i (waddr_pack), .wdata_i (wdata_pack), - .we_i (we_pack), - .* + .we_i (we_pack) ); end @@ -1044,13 +1045,14 @@ module issue_read_operands .NR_READ_PORTS(3), .ZERO_REG_ZERO(0) ) i_ariane_fp_regfile_fpga ( + .clk_i, + .rst_ni, .test_en_i(1'b0), .raddr_i (fp_raddr_pack), .rdata_o (fprdata), .waddr_i (waddr_pack), .wdata_i (fp_wdata_pack), - .we_i (we_fpr_i), - .* + .we_i (we_fpr_i) ); end else begin : gen_asic_fp_regfile ariane_regfile #( @@ -1059,13 +1061,14 @@ module issue_read_operands .NR_READ_PORTS(3), .ZERO_REG_ZERO(0) ) i_ariane_fp_regfile ( + .clk_i, + .rst_ni, .test_en_i(1'b0), .raddr_i (fp_raddr_pack), .rdata_o (fprdata), .waddr_i (waddr_pack), .wdata_i (fp_wdata_pack), - .we_i (we_fpr_i), - .* + .we_i (we_fpr_i) ); end end else begin : no_fpr_gen diff --git a/core/issue_stage.sv b/core/issue_stage.sv index 094c34365c..d22ddec0c1 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -67,16 +67,16 @@ module issue_stage input logic flu_ready_i, // ALU FU is valid - EX_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_o, + // Branch unit is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_o, + // Information of branch prediction - EX_STAGE + output branchpredict_sbe_t branch_predict_o, // Signaling that we resolved the branch - EX_STAGE input logic resolve_branch_i, // Load store unit FU is ready - EX_STAGE input logic lsu_ready_i, // Load store unit FU is valid - EX_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_o, - // Branch unit is valid - EX_STAGE - output logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_o, - // Information of branch prediction - EX_STAGE - output branchpredict_sbe_t branch_predict_o, // Mult FU is valid - EX_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_o, // FPU FU is ready - EX_STAGE @@ -99,17 +99,23 @@ module issue_stage output logic [31:0] x_off_instr_o, // CVA6 Hart ID - SUBSYSTEM input logic [CVA6Cfg.XLEN-1:0] hart_id_i, - // CVXIF Issue interface + // CVXIF Issue interface - EX_STAGE input logic x_issue_ready_i, + // TO_BE_COMPLETED - EX_STAGE input x_issue_resp_t x_issue_resp_i, + // TO_BE_COMPLETED - EX_STAGE output logic x_issue_valid_o, + // TO_BE_COMPLETED - EX_STAGE output x_issue_req_t x_issue_req_o, - // CVXIF Register interface + // CVXIF Register interface - EX_STAGE input logic x_register_ready_i, + // TO_BE_COMPLETED - EX_STAGE output logic x_register_valid_o, + // TO_BE_COMPLETED - EX_STAGE output x_register_t x_register_o, - // CVXIF Commit interface + // CVXIF Commit interface - EX_STAGE output logic x_commit_valid_o, + // TO_BE_COMPLETED - EX_STAGE output x_commit_t x_commit_o, // CVXIF Transaction rejected -> instruction is illegal - EX_STAGE output logic x_transaction_rejected_o, @@ -195,24 +201,35 @@ module issue_stage .exception_t(exception_t), .scoreboard_entry_t(scoreboard_entry_t) ) i_scoreboard ( + .clk_i, + .rst_ni, .sb_full_o (sb_full_o), + .flush_unissued_instr_i, + .flush_i, .x_transaction_accepted_i(x_transaction_accepted_iro_sb), .x_issue_writeback_i (x_issue_writeback_iro_sb), .x_id_i (x_id_iro_sb), - .fwd_o (fwd), + .commit_instr_o, + .commit_drop_o, + .commit_ack_i, .decoded_instr_i (decoded_instr_i), + .orig_instr_i, .decoded_instr_valid_i (decoded_instr_valid_i), .decoded_instr_ack_o (decoded_instr_ack_o), .issue_instr_o (issue_instr_sb_iro), .orig_instr_o (orig_instr_sb_iro), .issue_instr_valid_o (issue_instr_valid_sb_iro), .issue_ack_i (issue_ack_iro_sb), - - .resolved_branch_i(resolved_branch_i), - .trans_id_i (trans_id_i), - .wbdata_i (wbdata_i), - .ex_i (ex_ex_i), - .* + .fwd_o (fwd), + .resolved_branch_i (resolved_branch_i), + .trans_id_i (trans_id_i), + .wbdata_i (wbdata_i), + .ex_i (ex_ex_i), + .wt_valid_i, + .x_we_i, + .x_rd_i, + .rvfi_issue_pointer_o, + .rvfi_commit_pointer_o ); // --------------------------------------------------------- @@ -231,20 +248,37 @@ module issue_stage .x_register_t(x_register_t), .x_commit_t(x_commit_t) ) i_issue_read_operands ( + .clk_i, + .rst_ni, .flush_i (flush_unissued_instr_i), + .stall_i, .issue_instr_i (issue_instr_sb_iro), .orig_instr_i (orig_instr_sb_iro), .issue_instr_valid_i (issue_instr_valid_sb_iro), .issue_ack_o (issue_ack_iro_sb), + .fwd_i (fwd), .fu_data_o (fu_data_o), + .rs1_forwarding_o (rs1_forwarding_xlen), + .rs2_forwarding_o (rs2_forwarding_xlen), + .pc_o, + .is_compressed_instr_o, .flu_ready_i (flu_ready_i), - .fwd_i (fwd), .alu_valid_o (alu_valid_o), - .alu2_valid_o (alu2_valid_o), .branch_valid_o (branch_valid_o), - .csr_valid_o (csr_valid_o), + .tinst_o (tinst_o), + .branch_predict_o, + .lsu_ready_i, + .lsu_valid_o, + .mult_valid_o, + .fpu_ready_i, + .fpu_valid_o, + .fpu_fmt_o, + .fpu_rm_o, + .alu2_valid_o, + .csr_valid_o, .cvxif_valid_o (xfu_valid_o), .cvxif_ready_i (xfu_ready_i), + .cvxif_off_instr_o (x_off_instr_o), .hart_id_i (hart_id_i), .x_issue_ready_i (x_issue_ready_i), .x_issue_resp_i (x_issue_resp_i), @@ -259,13 +293,11 @@ module issue_stage .x_transaction_rejected_o(x_transaction_rejected_o), .x_issue_writeback_o (x_issue_writeback_iro_sb), .x_id_o (x_id_iro_sb), - .cvxif_off_instr_o (x_off_instr_o), - .mult_valid_o (mult_valid_o), - .rs1_forwarding_o (rs1_forwarding_xlen), - .rs2_forwarding_o (rs2_forwarding_xlen), - .stall_issue_o (stall_issue_o), - .tinst_o (tinst_o), - .* + .waddr_i, + .wdata_i, + .we_gpr_i, + .we_fpr_i, + .stall_issue_o ); endmodule diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index c1db6e1d9a..04c4e00e07 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -256,6 +256,10 @@ module load_store_unit .clk_i(clk_i), .rst_ni(rst_ni), .flush_i(flush_i), + .enable_translation_i, + .enable_g_translation_i, + .en_ld_st_translation_i, + .en_ld_st_g_translation_i, .icache_areq_i(icache_areq_i), .icache_areq_o(icache_areq_o), // misaligned bypass @@ -273,10 +277,29 @@ module load_store_unit .lsu_exception_o(mmu_exception), .priv_lvl_i (priv_lvl_i), + .v_i, .ld_st_priv_lvl_i(ld_st_priv_lvl_i), + .ld_st_v_i, + .sum_i, + .vs_sum_i, + .mxr_i, + .vmxr_i, .hlvx_inst_i (mmu_hlvx_inst), .hs_ld_st_inst_i(mmu_hs_ld_st_inst), + .satp_ppn_i, + .vsatp_ppn_i, + .hgatp_ppn_i, + .asid_i, + .vs_asid_i, + .asid_to_be_flushed_i, + .vmid_i, + .vmid_to_be_flushed_i, + .vaddr_to_be_flushed_i, + .gpaddr_to_be_flushed_i, + .flush_tlb_i, + .flush_tlb_vvma_i, + .flush_tlb_gvma_i, .itlb_miss_o(itlb_miss_o), .dtlb_miss_o(dtlb_miss_o), @@ -284,8 +307,7 @@ module load_store_unit .req_port_i(dcache_req_ports_i[0]), .req_port_o(dcache_req_ports_o[0]), .pmpcfg_i, - .pmpaddr_i, - .* + .pmpaddr_i ); end else begin : gen_no_mmu @@ -391,6 +413,9 @@ module load_store_unit .exception_t(exception_t), .lsu_ctrl_t(lsu_ctrl_t) ) i_load_unit ( + .clk_i, + .rst_ni, + .flush_i, .valid_i (ld_valid_i), .lsu_ctrl_i(lsu_ctrl), .pop_ld_o (pop_ld), @@ -413,12 +438,11 @@ module load_store_unit .page_offset_o (page_offset), .page_offset_matches_i(page_offset_matches), .store_buffer_empty_i (store_buffer_empty), + .commit_tran_id_i, // to memory arbiter .req_port_i (dcache_req_ports_i[1]), .req_port_o (dcache_req_ports_o[1]), - .dcache_wbuffer_not_ni_i, - .commit_tran_id_i, - .* + .dcache_wbuffer_not_ni_i ); // ---------------------------- @@ -692,14 +716,16 @@ module load_store_unit .CVA6Cfg(CVA6Cfg), .lsu_ctrl_t(lsu_ctrl_t) ) lsu_bypass_i ( + .clk_i, + .rst_ni, + .flush_i, .lsu_req_i (lsu_req_i), .lsu_req_valid_i(lsu_valid_i), .pop_ld_i (pop_ld), .pop_st_i (pop_st), .lsu_ctrl_o(lsu_ctrl), - .ready_o (lsu_ready_o), - .* + .ready_o (lsu_ready_o) ); assign rvfi_lsu_ctrl_o = lsu_ctrl; diff --git a/core/scoreboard.sv b/core/scoreboard.sv index 61984f4b07..fbf6a6faff 100644 --- a/core/scoreboard.sv +++ b/core/scoreboard.sv @@ -32,8 +32,11 @@ module scoreboard #( // Flush whole scoreboard - TO_BE_COMPLETED input logic flush_i, // Writeback Handling of CVXIF + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic x_transaction_accepted_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic x_issue_writeback_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_id_i, // advertise instruction to commit stage, if commit_ack_i is asserted advance the commit pointer // TO_BE_COMPLETED - TO_BE_COMPLETED