diff --git a/core/frontend/bht.sv b/core/frontend/bht.sv
index baff335c73..e95c536770 100644
--- a/core/frontend/bht.sv
+++ b/core/frontend/bht.sv
@@ -1,5 +1,6 @@
 // Copyright 2018 - 2019 ETH Zurich and University of Bologna.
-// Copyright 2023 - Thales for additionnal conribution.
+// Copyright 2023 - Thales for additionnal contribution.
+// Copyright 2024 - PlanV Technologies for additionnal contribution.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 2.0 (the "License"); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at
@@ -15,6 +16,8 @@
 // Date: 09.06.2018
 // FPGA optimization: Sebastien Jacq, Thales
 // Date: 2023-01-30
+// FPGA optimization for Altera: Angela Gonzalez, PlanV Technolgies
+// Date: 2024-10-16
 
 // branch history table - 2 bit saturation counter
 
@@ -47,8 +50,6 @@ module bht #(
   localparam ROW_INDEX_BITS = CVA6Cfg.RVC == 1'b1 ? $clog2(CVA6Cfg.INSTR_PER_FETCH) : 1;
   // number of bits we should use for prediction
   localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS;
-  // we are not interested in all bits of the address
-  unread i_unread (.d_i(|vpc_i));
 
   struct packed {
     logic       valid;
@@ -58,7 +59,7 @@ module bht #(
       bht_q[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0];
 
   logic [$clog2(NR_ROWS)-1:0] index, update_pc;
-  logic [ROW_INDEX_BITS-1:0] update_row_index;
+  logic [ROW_INDEX_BITS-1:0] update_row_index, update_row_index_q, check_update_row_index;
 
   assign index     = vpc_i[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET];
   assign update_pc = bht_update_i.pc[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET];
@@ -127,17 +128,23 @@ module bht #(
 
     // number of bits par word in the bram
     localparam BRAM_WORD_BITS = $bits(ariane_pkg::bht_t);
-    logic             [                         ROW_INDEX_BITS-1:0] row_index;
-    logic             [                CVA6Cfg.INSTR_PER_FETCH-1:0] bht_ram_we;
-    logic             [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0] bht_ram_read_address_0;
-    logic             [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0] bht_ram_read_address_1;
-    logic             [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0] bht_ram_write_address;
-    logic             [ CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] bht_ram_wdata;
-    logic             [ CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] bht_ram_rdata_0;
-    logic             [ CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] bht_ram_rdata_1;
-
-    ariane_pkg::bht_t [                CVA6Cfg.INSTR_PER_FETCH-1:0] bht;
-    ariane_pkg::bht_t [                CVA6Cfg.INSTR_PER_FETCH-1:0] bht_updated;
+    logic [ROW_INDEX_BITS-1:0] row_index, row_index_q, check_row_index;
+    logic [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_ram_we, bht_ram_we_q;
+    logic [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0] bht_ram_read_address_0;
+    logic [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0] bht_ram_read_address_1;
+    logic [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0]
+        bht_ram_write_address, bht_ram_write_address_q;
+    logic [CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] bht_ram_wdata, bht_ram_wdata_q;
+    logic [CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] bht_ram_rdata_0;
+    logic [CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] bht_ram_rdata_1;
+
+    ariane_pkg::bht_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht;
+    ariane_pkg::bht_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_updated;
+
+    logic [CVA6Cfg.INSTR_PER_FETCH-1:0][1:0] bht_updated_valid;
+    logic [CVA6Cfg.INSTR_PER_FETCH-1:0][1:0][CVA6Cfg.VLEN-1:0] bht_updated_pc;
+    logic bht_update_taken, check_bht_update_taken;
+    logic [CVA6Cfg.VLEN-1:0] vpc_q;
 
     if (CVA6Cfg.RVC) begin : gen_row_index
       assign row_index = vpc_i[ROW_ADDR_BITS+OFFSET-1:OFFSET];
@@ -157,64 +164,150 @@ module bht #(
       bht_updated = '0;
       bht = '0;
 
-      for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin
-        bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = index;
-        bht_prediction_o[i].valid = bht_ram_rdata_0[i*BRAM_WORD_BITS+2];
-        bht_prediction_o[i].taken = bht_ram_rdata_0[i*BRAM_WORD_BITS+1];
-      end
-
+      //Write to RAM
       if (bht_update_i.valid && !debug_mode_i) begin
         for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin
           if (update_row_index == i) begin
-            bht_ram_read_address_1[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = update_pc;
-            bht[i].saturation_counter = bht_ram_rdata_1[i*BRAM_WORD_BITS+:2];
-
-            if (bht[i].saturation_counter == 2'b11) begin
-              // we can safely decrease it
-              if (!bht_update_i.taken)
-                bht_updated[i].saturation_counter = bht[i].saturation_counter - 1;
-              else bht_updated[i].saturation_counter = 2'b11;
-              // then check if it saturated in the negative regime e.g.: branch not taken
-            end else if (bht[i].saturation_counter == 2'b00) begin
-              // we can safely increase it
-              if (bht_update_i.taken)
-                bht_updated[i].saturation_counter = bht[i].saturation_counter + 1;
-              else bht_updated[i].saturation_counter = 2'b00;
-            end else begin // otherwise we are not in any boundaries and can decrease or increase it
-              if (bht_update_i.taken)
-                bht_updated[i].saturation_counter = bht[i].saturation_counter + 1;
-              else bht_updated[i].saturation_counter = bht[i].saturation_counter - 1;
-            end
-
             bht_updated[i].valid = 1'b1;
             bht_ram_we[i] = 1'b1;
             bht_ram_write_address[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = update_pc;
-            //bht_ram_wdata[(i+1)*BRAM_WORD_BITS-1] =  1'b1; //valid
-            bht_ram_wdata[i*BRAM_WORD_BITS+:BRAM_WORD_BITS] = {
-              bht_updated[i].valid, bht_updated[i].saturation_counter
-            };
+          end
+        end
+      end
+
+      for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin
+
+        //When synchronous RAM is used, addresses are needed as soon as available
+        if (CVA6Cfg.FpgaAlteraEn)
+          bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = index;
+        if (CVA6Cfg.FpgaAlteraEn)
+          bht_ram_read_address_1[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = update_pc;
+
+        if (check_update_row_index == i) begin
+          //When asynchronous RAM is used, the address can be updated on the cycle when data is read
+          if (!CVA6Cfg.FpgaAlteraEn)
+            bht_ram_read_address_1[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = update_pc;
+          bht[i].saturation_counter = bht_ram_rdata_1[i*BRAM_WORD_BITS+:2];
+
+          if (bht[i].saturation_counter == 2'b11) begin
+            // we can safely decrease it
+            if (!check_bht_update_taken)
+              bht_updated[i].saturation_counter = bht[i].saturation_counter - 1;
+            else bht_updated[i].saturation_counter = 2'b11;
+            // then check if it saturated in the negative regime e.g.: branch not taken
+          end else if (bht[i].saturation_counter == 2'b00) begin
+            // we can safely increase it
+            if (check_bht_update_taken)
+              bht_updated[i].saturation_counter = bht[i].saturation_counter + 1;
+            else bht_updated[i].saturation_counter = 2'b00;
+          end else begin  // otherwise we are not in any boundaries and can decrease or increase it
+            if (check_bht_update_taken)
+              bht_updated[i].saturation_counter = bht[i].saturation_counter + 1;
+            else bht_updated[i].saturation_counter = bht[i].saturation_counter - 1;
+          end
 
+          //The data written in the RAM will have the valid bit from current input (async RAM) or the one from one clock cycle before (sync RAM)
+          bht_ram_wdata[i*BRAM_WORD_BITS+:BRAM_WORD_BITS] = CVA6Cfg.FpgaAlteraEn ? {bht_updated_valid[i][0], bht_updated[i].saturation_counter} :
+                                                                           {bht_updated[i].valid, bht_updated[i].saturation_counter};
+        end
+
+
+        if (!rst_ni) begin
+          //initialize output
+          bht_prediction_o[i] = '0;
+        end else begin
+          //When asynchronous RAM is used, addresses can be calculated on the same cycle as data is read
+          if (!CVA6Cfg.FpgaAlteraEn)
+            bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = index;
+          //When synchronous RAM is used and data is read right after writing, we need some buffering
+          // This is one cycle of buffering
+          if (CVA6Cfg.FpgaAlteraEn && bht_updated_valid[i][0] && vpc_q == bht_updated_pc[i][0]) begin
+            bht_prediction_o[i].valid = bht_ram_wdata[i*BRAM_WORD_BITS+2];
+            bht_prediction_o[i].taken = bht_ram_wdata[i*BRAM_WORD_BITS+1];
+            //This is two cycles of buffering
+          end else if (CVA6Cfg.FpgaAlteraEn && bht_updated_valid[i][1] && vpc_q == bht_updated_pc[i][1]) begin
+            bht_prediction_o[i].valid = bht_ram_wdata_q[i*BRAM_WORD_BITS+2];
+            bht_prediction_o[i].taken = bht_ram_wdata_q[i*BRAM_WORD_BITS+1];
+            //In any other case we can safely read from the RAM as data is available
+          end else begin
+            bht_prediction_o[i].valid = bht_ram_rdata_0[i*BRAM_WORD_BITS+2];
+            bht_prediction_o[i].taken = bht_ram_rdata_0[i*BRAM_WORD_BITS+1];
           end
         end
       end
     end
 
     for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_bht_ram
-      AsyncThreePortRam #(
-          .ADDR_WIDTH($clog2(NR_ROWS)),
-          .DATA_DEPTH(NR_ROWS),
-          .DATA_WIDTH(BRAM_WORD_BITS)
-      ) i_bht_ram (
-          .Clk_CI     (clk_i),
-          .WrEn_SI    (bht_ram_we[i]),
-          .WrAddr_DI  (bht_ram_write_address[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]),
-          .WrData_DI  (bht_ram_wdata[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]),
-          .RdAddr_DI_0(bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]),
-          .RdAddr_DI_1(bht_ram_read_address_1[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]),
-          .RdData_DO_0(bht_ram_rdata_0[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]),
-          .RdData_DO_1(bht_ram_rdata_1[i*BRAM_WORD_BITS+:BRAM_WORD_BITS])
-      );
+      if (CVA6Cfg.FpgaAlteraEn) begin
+        SyncThreePortRam #(
+            .ADDR_WIDTH($clog2(NR_ROWS)),
+            .DATA_DEPTH(NR_ROWS),
+            .DATA_WIDTH(BRAM_WORD_BITS)
+        ) i_bht_ram (
+            .Clk_CI     (clk_i),
+            .WrEn_SI    (bht_ram_we_q[i]),
+            .WrAddr_DI  (bht_ram_write_address_q[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]),
+            .WrData_DI  (bht_ram_wdata[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]),
+            .RdAddr_DI_0(bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]),
+            .RdAddr_DI_1(bht_ram_read_address_1[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]),
+            .RdData_DO_0(bht_ram_rdata_0[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]),
+            .RdData_DO_1(bht_ram_rdata_1[i*BRAM_WORD_BITS+:BRAM_WORD_BITS])
+        );
+
+      end else begin
+        AsyncThreePortRam #(
+            .ADDR_WIDTH($clog2(NR_ROWS)),
+            .DATA_DEPTH(NR_ROWS),
+            .DATA_WIDTH(BRAM_WORD_BITS)
+        ) i_bht_ram (
+            .Clk_CI     (clk_i),
+            .WrEn_SI    (bht_ram_we[i]),
+            .WrAddr_DI  (bht_ram_write_address[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]),
+            .WrData_DI  (bht_ram_wdata[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]),
+            .RdAddr_DI_0(bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]),
+            .RdAddr_DI_1(bht_ram_read_address_1[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]),
+            .RdData_DO_0(bht_ram_rdata_0[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]),
+            .RdData_DO_1(bht_ram_rdata_1[i*BRAM_WORD_BITS+:BRAM_WORD_BITS])
+        );
+      end
+    end
+
+    // Extra buffering signals needed when synchronous RAM is used
+
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (CVA6Cfg.FpgaAlteraEn) begin
+        if (!rst_ni) begin
+          bht_updated_valid <= '0;
+          bht_update_taken <= '0;
+          bht_ram_wdata_q <= '0;
+          row_index_q <= '0;
+          bht_ram_we_q <= '0;
+          bht_ram_write_address_q <= '0;
+          update_row_index_q <= '0;
+        end else begin
+          for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin
+            bht_updated_valid[i][1] <= bht_updated_valid[i][0];
+            bht_updated_valid[i][0] <= bht_updated[i].valid;
+            bht_updated_pc[i][1] <= bht_updated_pc[i][0];
+            bht_updated_pc[i][0] <= bht_update_i.pc;
+
+          end
+          vpc_q <= vpc_i;
+          bht_update_taken <= bht_update_i.taken;
+          bht_ram_wdata_q <= bht_ram_wdata;
+          bht_ram_we_q <= bht_ram_we;
+          bht_ram_write_address_q <= bht_ram_write_address;
+          update_row_index_q <= update_row_index;
+
+          row_index_q <= row_index;
+        end
+      end
     end
 
+    // Assignment of indexes checked to generate data written in the RAM. When synchronous RAM is used these signals need to be delayed
+    assign check_update_row_index = CVA6Cfg.FpgaAlteraEn ? update_row_index_q : update_row_index;
+    assign check_bht_update_taken = CVA6Cfg.FpgaAlteraEn ? bht_update_taken : bht_update_i.taken;
+    assign check_row_index        = CVA6Cfg.FpgaAlteraEn ? row_index_q : row_index;
+
   end
 endmodule
diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv
index e59da0ee36..3117e27654 100644
--- a/core/frontend/frontend.sv
+++ b/core/frontend/frontend.sv
@@ -140,6 +140,7 @@ module frontend
   btb_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0]                   btb_prediction_shifted;
   ras_t                                                            ras_predict;
   logic            [           CVA6Cfg.VLEN-1:0]                   vpc_btb;
+  logic            [           CVA6Cfg.VLEN-1:0]                   vpc_bht;
 
   // branch-predict update
   logic                                                            is_mispredict;
@@ -484,7 +485,9 @@ module frontend
   //For FPGA, BTB is implemented in read synchronous BRAM
   //while for ASIC, BTB is implemented in D flip-flop
   //and can be read at the same cycle.
+  //Same for BHT
   assign vpc_btb = (CVA6Cfg.FpgaEn) ? icache_dreq_i.vaddr : icache_vaddr_q;
+  assign vpc_bht = (CVA6Cfg.FpgaEn && CVA6Cfg.FpgaAlteraEn && icache_dreq_i.valid) ? icache_dreq_i.vaddr : icache_vaddr_q;
 
   if (CVA6Cfg.BTBEntries == 0) begin
     assign btb_prediction = '0;
@@ -517,7 +520,7 @@ module frontend
         .rst_ni,
         .flush_bp_i      (flush_bp_i),
         .debug_mode_i,
-        .vpc_i           (icache_vaddr_q),
+        .vpc_i           (vpc_bht),
         .bht_update_i    (bht_update),
         .bht_prediction_o(bht_prediction)
     );
diff --git a/docs/04_cv32a65x/tristan/verif-spec/media/interrupt_uvm_agent.png b/docs/04_cv32a65x/tristan/verif-spec/media/interrupt_uvm_agent.png
new file mode 100644
index 0000000000..03cb21e2ec
Binary files /dev/null and b/docs/04_cv32a65x/tristan/verif-spec/media/interrupt_uvm_agent.png differ
diff --git a/docs/04_cv32a65x/tristan/verif-spec/verification_specifications.adoc b/docs/04_cv32a65x/tristan/verif-spec/verification_specifications.adoc
index 23efda5cd3..b7b59b27e1 100644
--- a/docs/04_cv32a65x/tristan/verif-spec/verification_specifications.adoc
+++ b/docs/04_cv32a65x/tristan/verif-spec/verification_specifications.adoc
@@ -492,6 +492,75 @@ image:./media/axiagentmerge.png[./media/axiagentmerge,width=602,height=285]
 At the time of writing this document, the merge of the two agents is not yet completed.
 It remains to publish on GitHub the agent and to integrate it with CVA6.
 
+*_[.underline]#Interrupt Agent#_*
+
+This document describes the interrupt agent that plays as a interrupt controler for the CV32A65X, the agent is based on the following protocol:
+https://github.com/openhwgroup/cva6/blob/master/verif/docs/Protocols/interrupt-verification.adoc
+
+[.underline]#Agent Architecture:#
+
+image:./media/interrupt_uvm_agent.png[./media/image5,width=618,height=366]
+
+[.underline]#Agent components:#
+
+The Interrupt agent provides following components:
+
+* uvma_interrupt_agent_c: UVM Agent.
+
+* uvma_interrupt_mon_c: Agent monitor, collects and broadcast transactions to the coverage model each time the interrupt interface changes.
+
+* uvma_interrupt_base_seq_c: Base sequence, instantiate agent configuration & context, and connect it with the sequencer configuration & context.
+
+* uvma_interrupt_seq_c: Generates interrupt requests & clear them based on the clear protocol decribe in link above.
+
+* uvma_interrupt_seq_item_c: Have main items of an interrupt transaction, `+interrupt_vector,+`interrupt_channel_mask and interrupt delays.
+
+* uvma_interrupt_sqr_c: Sequencer, receives requests from the sequence and send it to the driver.
+
+* uvma_interrupt_drv_c: drive the vif with the requests received from sequencer.
+
+* uvma_interrupt_cntxt_c: Agent context, instantiate VIF uma_interrupt_intf and memory uvml_mem. VIF and Memory are accessible in all components through context.
+
+* uvma_interrupt_cfg_c: Agent configuration, all available configuration fields are described in Configuration Fields.
+
+[.underline]#Supported features:#
+
+features are:
+
+* Asynchronous request: the agent support Asynchronously interrupts requests.
+
+* No channel Dependency: there’s no dependency between the interrupt channels, every one is managed independently.
+
+* Channel delay: provide delay after setting the interrupt request, also after clear it.
+
+* Randomize channel: full randomization of setting interrupt request.
+
+* Timeout: the agent is triggering a `+UVM_FATAL+` after a number of clock cycle if it failed to clear the interrupt request.
+
+[.underline]#Agent configuration Fields:#
+
+* is_active: Switch the agent mode to active. The agent support only UVM_ACTIVE mode (can’t be in passive mode).
+
+* trn_log_enabled: Enabling interrupt transaction logger when 1.
+
+* enable_interrupt: Enabling sending interrupt request when 1.
+
+* interrupt_plusarg_valid: Enabling interrupts from commande line request when 1.
+
+* num_irq_supported: Represent the number of interrupt channels supported.
+
+* irq_addr: Represent the memory address used by the interrupt clear mechanism.
+
+* enable_clear_irq: Enabling the interrupt clear mechanism when 1.
+
+* irq_timeout: Represent the number of clock cyle before the agent trigger a `+UVM_FATAL+` timeout.
+
+[.underline]#Sequences:#
+
+This agent provides only one sequence:
+
+* Set/Clear sequence: this sequence set interrupt request also clear it based on a protocol.
+
 ==== UVCs
 
 No UVC used in this project
diff --git a/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv b/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv
new file mode 100644
index 0000000000..2b65c9ec80
--- /dev/null
+++ b/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv
@@ -0,0 +1,65 @@
+// Copyright 2024 PlanV Technologies
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// You may obtain a copy of the License at https://solderpad.org/licenses
+//
+// Inferable, Asynchronous Three-Ports RAM, there are a write port and two read ports
+//
+//
+// This module is designed to work with both Xilinx, Microchip and Altera FPGA tools by following the respective
+// guidelines:
+// - Xilinx UG901 Vivado Design Suite User Guide: Synthesis
+// - Inferring Microchip PolarFire RAM Blocks
+// - Altera Quartus II Handbook Volume 1: Design and Synthesis (p. 768)
+//
+// Current Maintainers:: Angela Gonzalez - PlanV Technologies
+
+ 
+module SyncThreePortRam
+#(
+  parameter ADDR_WIDTH = 10,
+  parameter DATA_DEPTH = 1024, // usually 2**ADDR_WIDTH, but can be lower
+  parameter DATA_WIDTH = 32
+)(
+  input  logic                    Clk_CI,
+
+  // Write port
+  input  logic                    WrEn_SI,
+  input  logic [ADDR_WIDTH-1:0]   WrAddr_DI,
+  input  logic [DATA_WIDTH-1:0]   WrData_DI,
+  
+  // Read ports
+  input  logic [ADDR_WIDTH-1:0]   RdAddr_DI_0,
+  input  logic [ADDR_WIDTH-1:0]   RdAddr_DI_1,
+  
+  output logic [DATA_WIDTH-1:0]   RdData_DO_0,
+  output logic [DATA_WIDTH-1:0]   RdData_DO_1
+);
+
+logic [DATA_WIDTH-1:0] mem [DATA_DEPTH-1:0]= '{default:0};
+
+  // WRITE
+  always_ff @(posedge Clk_CI)
+  begin
+    if (WrEn_SI) begin
+      mem[WrAddr_DI] <= WrData_DI;
+    end
+    
+    RdData_DO_0 = mem[RdAddr_DI_0];
+    RdData_DO_1 = mem[RdAddr_DI_1];
+  
+  end
+  
+  ////////////////////////////
+  // assertions
+  ////////////////////////////
+
+  // pragma translate_off
+  assert property
+    (@(posedge Clk_CI) (longint'(2)**longint'(ADDR_WIDTH) >= longint'(DATA_DEPTH)))
+    else $error("depth out of bounds");
+  // pragma translate_on
+
+endmodule 
diff --git a/verif/docs/VerifPlans/csr_access/VP_IP000.yml b/verif/docs/VerifPlans/csr_access/VP_IP000.yml
index 664f24fee5..a62965d9d2 100644
--- a/verif/docs/VerifPlans/csr_access/VP_IP000.yml
+++ b/verif/docs/VerifPlans/csr_access/VP_IP000.yml
@@ -17,7 +17,7 @@ subfeatures: !!omap
         description: Upon reset, RISC-V CVA6 Machine mode RW CSRs must initialize
           to their respective POR value.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -68,7 +68,7 @@ subfeatures: !!omap
           random values like 0xa5a5a5a5, 0x5a5a5a5a, 0xffa1ae40.. and read using the
           CSR instructions defined in the instruction set architecture (ISA).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -94,7 +94,7 @@ subfeatures: !!omap
         description: Accessing RISC-V CVA6 Machine Mode CSRs in different privilege
           modes (User, Supervisor and Machine modes).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
diff --git a/verif/docs/VerifPlans/csr_access/VP_IP001.yml b/verif/docs/VerifPlans/csr_access/VP_IP001.yml
index 4e72a8156c..8b16419697 100644
--- a/verif/docs/VerifPlans/csr_access/VP_IP001.yml
+++ b/verif/docs/VerifPlans/csr_access/VP_IP001.yml
@@ -16,7 +16,7 @@ subfeatures: !!omap
         description: Upon reset,RISC-V CVA6 Machine RO(read only) CSR must initialize
           to their respective POR value.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -42,7 +42,7 @@ subfeatures: !!omap
           random values like 0xa5a5a5a5, 0x5a5a5a5a, 0xffa1ae40.. and confirm whether
           write into RO CSRs is possible or not.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -68,7 +68,7 @@ subfeatures: !!omap
         description: Accessing RISC-V Machine read only CSRs in different privilege
           modes (User, Supervisor and Machine modes).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
diff --git a/verif/docs/VerifPlans/csr_access/VP_IP002.yml b/verif/docs/VerifPlans/csr_access/VP_IP002.yml
index c615ae16e4..51ed9fa8d0 100644
--- a/verif/docs/VerifPlans/csr_access/VP_IP002.yml
+++ b/verif/docs/VerifPlans/csr_access/VP_IP002.yml
@@ -17,7 +17,7 @@ subfeatures: !!omap
         description: Upon reset, RISC-V CVA6 Supervisor mode RW CSRs must initialize
           to their respective POR value.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -67,7 +67,7 @@ subfeatures: !!omap
           writing random values like 0xa5a5a5a5, 0x5a5a5a5a, 0xffa1ae40.. and read
           using the CSR instructions defined in the instruction set architecture (ISA).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -93,7 +93,7 @@ subfeatures: !!omap
         description: Accessing RISC-V CVA6 Supervisor Mode CSRs in different privilege
           modes (User,Supervisor and Machine modes).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
diff --git a/verif/docs/VerifPlans/csr_access/VP_IP003.yml b/verif/docs/VerifPlans/csr_access/VP_IP003.yml
index 3267c6030f..3099b330be 100644
--- a/verif/docs/VerifPlans/csr_access/VP_IP003.yml
+++ b/verif/docs/VerifPlans/csr_access/VP_IP003.yml
@@ -16,7 +16,7 @@ subfeatures: !!omap
         description: Upon reset, RISC-V CVA6 User mode counter CSRs must initialize
           to their respective POR value.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -51,7 +51,7 @@ subfeatures: !!omap
           two continuous reads and checking whether the value in the second read is
           greater than the value in the first read."
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -80,7 +80,7 @@ subfeatures: !!omap
         description: Accessing RISC-V CVA6 user Mode counter CSR in different privilege
           modes (User, Supervisor and Machine modes).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
diff --git a/verif/docs/VerifPlans/csr_access/VP_IP004.yml b/verif/docs/VerifPlans/csr_access/VP_IP004.yml
index 8c7d5b8871..2250afd03e 100644
--- a/verif/docs/VerifPlans/csr_access/VP_IP004.yml
+++ b/verif/docs/VerifPlans/csr_access/VP_IP004.yml
@@ -16,7 +16,7 @@ subfeatures: !!omap
         description: Upon reset, RISC-V CVA6 Machine mode counter CSRs must initialize
           to their respective POR value.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -52,7 +52,7 @@ subfeatures: !!omap
           tested by performing two continuous reads and checking whether the value
           in the second read is greater than the value in the first read."
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -81,7 +81,7 @@ subfeatures: !!omap
         description: Accessing RISC-V CVA6 user Machine mode counter CSRs in different
           privilege modes (User, Supervisor and Machine modes).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
diff --git a/verif/docs/VerifPlans/csr_access/dvplan_csr-access.md b/verif/docs/VerifPlans/csr_access/dvplan_csr-access.md
index 60e8d9e63c..861c79e614 100644
--- a/verif/docs/VerifPlans/csr_access/dvplan_csr-access.md
+++ b/verif/docs/VerifPlans/csr_access/dvplan_csr-access.md
@@ -89,7 +89,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#item-000 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -153,7 +153,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id2 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -188,7 +188,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id3 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -223,7 +223,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id5 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -254,7 +254,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id6 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -287,7 +287,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id7 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -322,7 +322,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id9 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -384,7 +384,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id13 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -417,7 +417,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id15 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -451,7 +451,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id17 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -483,7 +483,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id18 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -524,7 +524,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id20 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -588,7 +588,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id23 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -620,7 +620,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id25 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -662,7 +662,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id27 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
diff --git a/verif/env/uvme/uvma_interrupt/README.md b/verif/env/uvme/uvma_interrupt/README.md
index 2994761f7d..37edcd36ab 100644
--- a/verif/env/uvme/uvma_interrupt/README.md
+++ b/verif/env/uvme/uvma_interrupt/README.md
@@ -1,16 +1,3 @@
-Description of the interrupt agent.  
+*Interrupt Agent documentation:*
 
-- The interrupt agent supports mainly 3 modes:  
-  1 - The agent sends one interrupt request, then we deassert it.   
-  2 - The agent sends several interrupt requests at the same time, with the same size, then we deassert the interrupt requests.   
-  3 - The agent sends randomized interrupt requests.   
-
-- The interrupt agent has 2 type of delays in `uvma_interrupt_seq_item.sv`:  
-  1 - `irq_delay` is related to the delay between two interrupt request.  
-  2 - `irq_time` is related to the time the interrupt request could take.  
-
-- The interrupt agent sends requests asynchronously.
-
-- To enable interrupt requests you should add the option `"+enable_interrupt"`.
-
-- There is no mechanism to clear the interrupt requests (on going).
+You can see the UVM interrupt agent documentation in : https://gitlab-tss.gemalto.com/riscv/ohg-pr/cva6/-/blob/master/docs/04_cv32a65x/tristan/verif-spec/verification_specifications.adoc
diff --git a/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv b/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv
index dbe12ed238..0a08d68af4 100644
--- a/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv
+++ b/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv
@@ -29,8 +29,6 @@ package uvma_interrupt_pkg;
    import uvml_hrtbt_pkg::*;
    import uvml_trn_pkg  ::*;
    import uvml_logs_pkg ::*;
-   import uvma_isacov_pkg ::*;
-   import uvma_rvfi_pkg ::*;
 
    parameter XLEN = 32;
    parameter int MAX_ADDR_WIDTH    = `UVMA_AXI_ADDR_MAX_WIDTH    ; // subjective maximum