From 4279cc0f6e514ba1cd8916a0a039c64979d2618a Mon Sep 17 00:00:00 2001 From: Jalali <110232072+AyoubJalali@users.noreply.github.com> Date: Tue, 9 Jan 2024 10:55:09 +0000 Subject: [PATCH] Fix CSR coverage model & HVP (#1751) --- verif/env/uvme/cov/uvme_cva6_config_covg.sv | 4 ++-- verif/env/uvme/reg/cva6_csr_reg_file.sv | 19 ++++++++-------- verif/sim/Makefile | 2 +- verif/sim/cva6.hvp | 25 +++++++++++++++++++++ 4 files changed, 38 insertions(+), 12 deletions(-) diff --git a/verif/env/uvme/cov/uvme_cva6_config_covg.sv b/verif/env/uvme/cov/uvme_cva6_config_covg.sv index 4692b9c375..c3fde94db0 100644 --- a/verif/env/uvme/cov/uvme_cva6_config_covg.sv +++ b/verif/env/uvme/cov/uvme_cva6_config_covg.sv @@ -121,7 +121,7 @@ covergroup cg_cva6_config(string name) with function sample(); bins NrStorePipeRegs ={0}; } cp_NrLoadBufEntries : coverpoint cva6_config_pkg::CVA6ConfigNrLoadBufEntries { - bins NrLoadBufEntries ={2}; + bins NrLoadBufEntries ={1}; } cp_InstrTlbEntries : coverpoint cva6_config_pkg::CVA6ConfigInstrTlbEntries { bins InstrTlbEntries ={2}; @@ -130,7 +130,7 @@ covergroup cg_cva6_config(string name) with function sample(); bins DataTlbEntries ={2}; } cp_RASDepth : coverpoint cva6_config_pkg::CVA6ConfigRASDepth { - bins RASDepth ={0}; + bins RASDepth ={2}; } cp_BTBEntries : coverpoint cva6_config_pkg::CVA6ConfigBTBEntries { bins BTBEntries ={0}; diff --git a/verif/env/uvme/reg/cva6_csr_reg_file.sv b/verif/env/uvme/reg/cva6_csr_reg_file.sv index c513cbacf9..185b2f9d5f 100644 --- a/verif/env/uvme/reg/cva6_csr_reg_file.sv +++ b/verif/env/uvme/reg/cva6_csr_reg_file.sv @@ -96,22 +96,22 @@ class reg_mstatus extends csr_reg; MPRV: coverpoint data[17:17]; XS: coverpoint data[16:15] { bins legal_values[] = {0}; - //GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); } FS: coverpoint data[14:13] { bins legal_values[] = {0}; - //GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); } MPP: coverpoint data[12:11]; VS: coverpoint data[10:9] { bins legal_values[] = {0}; - //GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); } SPP: coverpoint data[8:8]; MPIE: coverpoint data[7:7]; UBE: coverpoint data[6:6] { bins legal_values[] = {0}; - //GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); } SPIE: coverpoint data[5:5]; MIE: coverpoint data[3:3]; @@ -256,8 +256,9 @@ class reg_misa extends csr_reg; illegal_bins illegal_values = {[0:$]} with (!(item inside {1})); } Extensions: coverpoint data[25:0] { - bins legal_values[] = {26'h0001104}; - illegal_bins illegal_values = {[0:$]} with (!(item inside {26'h0001104})); + bins legal_values[] = {26'h0001106}; + //TODO : Fix issue#1734 + //illegal_bins illegal_values = {[0:$]} with (!(item inside {26'h0001106})); } endgroup @@ -269,8 +270,8 @@ class reg_misa extends csr_reg; bins illegal_values[] = {[0:$]} with (!(item inside {1})); } Extensions: coverpoint data[25:0] { - bins legal_values[] = {26'h0001104}; - bins illegal_values[3] = {[0:$]} with (!(item inside {26'h0001104})); + bins legal_values[] = {26'h0001106}; + bins illegal_values[3] = {[0:$]} with (!(item inside {26'h0001106})); } endgroup @@ -297,7 +298,7 @@ class reg_misa extends csr_reg; MXL.configure(.parent(this), .size(2), .lsb_pos(30), .access("RW"), .volatile(0), .reset(0), .has_reset(1), .is_rand(1), .individually_accessible(0)); Extensions = uvm_reg_field::type_id::create("Extensions"); - Extensions.configure(.parent(this), .size(26), .lsb_pos(0), .access("RW"), .volatile(0), .reset(37782532), .has_reset(1), .is_rand(1), .individually_accessible(0)); + Extensions.configure(.parent(this), .size(26), .lsb_pos(0), .access("RW"), .volatile(0), .reset(26'h0001106), .has_reset(1), .is_rand(1), .individually_accessible(0)); endfunction virtual function void sample(uvm_reg_data_t data, uvm_reg_data_t byte_en,bit is_read, uvm_reg_map map); diff --git a/verif/sim/Makefile b/verif/sim/Makefile index 3607185461..d75105fd75 100644 --- a/verif/sim/Makefile +++ b/verif/sim/Makefile @@ -253,7 +253,7 @@ vcs-uvm: $(tool_path)/spike-dasm --isa=$(variant) < ./vcs_results/default/vcs.d/trace_rvfi_hart_00.dasm > $(log) generate_cov_dash: - urg -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes description -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp -tgl portsonly + urg -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes weight+description+Comment -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -tgl portsonly vcs_clean_all: @echo "[VCS] Cleanup (entire vcs_work dir)" diff --git a/verif/sim/cva6.hvp b/verif/sim/cva6.hvp index 99e2cfd070..985741fc75 100644 --- a/verif/sim/cva6.hvp +++ b/verif/sim/cva6.hvp @@ -1,6 +1,7 @@ plan "CVA6 Verification Master Plan"; + attribute string Comment = ""; description = "CVA6 Verification Master Plan"; feature "Programmer view level"; @@ -9,7 +10,10 @@ plan "CVA6 Verification Master Plan"; description = "Instruction Set Architecture\nSpecification: Done, Dvplan: Done, Verification execution: Done"; feature RV32I; description = "I extension"; + Comment = ""; feature ADD; + Comment = "Issue in Spike-dasm decoder +Waiting for ISA_DECODER to be merge on master"; measure Group ADD; source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_add_cg"; endmeasure @@ -65,16 +69,19 @@ plan "CVA6 Verification Master Plan"; endmeasure endfeature feature DRET; + Comment = "RVFI limitation issue(#1338)"; measure Group DRET; source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_dret_cg"; endmeasure endfeature feature EBREAK; + Comment = "RVFI limitation issue(#1338)"; measure Group EBREAK; source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_ebreak_cg"; endmeasure endfeature feature ECALL; + Comment = "RVFI limitation issue(#1338)"; measure Group ECALL; source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_ecall_cg"; endmeasure @@ -331,6 +338,7 @@ plan "CVA6 Verification Master Plan"; endmeasure endfeature feature EBREAK; + Comment = "RVFI limitation issue(#1338)"; measure Group EBREAK; source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32c_ebreak_cg"; endmeasure @@ -461,6 +469,7 @@ plan "CVA6 Verification Master Plan"; endfeature feature RV32ZIFENCEI; description = "ZIFENCE.I extension"; + Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master"; measure Group FEINCE_I; source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32zifencei_fence_i_cg"; endmeasure @@ -478,6 +487,7 @@ plan "CVA6 Verification Master Plan"; feature RV32ZCB; weight = 0; description = "ZCB extension"; + Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master"; measure Group C_MUL; endmeasure measure Group C_ZEXT_B; @@ -495,6 +505,7 @@ plan "CVA6 Verification Master Plan"; endfeature feature RV32ZB; description = "Bitmanip extension"; + Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master"; feature RV32ZBA; measure Group SH1ADD; source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32zba_sh1add_cg"; @@ -608,12 +619,14 @@ plan "CVA6 Verification Master Plan"; endfeature feature "Illegal instructions"; weight = 0; + Comment = "RVFI limitation issue(#1338)"; measure Group illegal_instructions; endmeasure endfeature endfeature feature "CSR access"; description = "CSR registers access.\nSpecification: Done, Dvplan: Done, Verification execution: Done"; + Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master"; feature "CSR CODE COVERAGE"; measure Line, Cond, Toggle CSR_code_cov; source = "tree: uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.csr_regfile_i"; @@ -1272,6 +1285,7 @@ plan "CVA6 Verification Master Plan"; endfeature feature TRAPs; description = "Interrupts and Exceptions.\nSpecification: Done, Dvplan: Done, Verification execution: No."; + Comment = "RVFI limitation issue(#1338)"; feature Interrupts; measure Group Interrupts; endmeasure @@ -1288,6 +1302,7 @@ plan "CVA6 Verification Master Plan"; endfeature feature PMP; description = "Physical Memory Protection suppor.t\nSpecification: No, Dvplan: No, Verification execution: No."; + Comment = "Need to separate PMP from MMU"; measure Group PMP; endmeasure endfeature @@ -1343,6 +1358,11 @@ plan "CVA6 Verification Master Plan"; measure Group Features; endmeasure endfeature + feature "Code Coverage"; + measure Line, Cond, Toggle, Assert, SnpsAvg AXI; + source = "tree: uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.gen_cache_wt.i_cache_subsystem.i_adapter.i_axi_shim"; + endmeasure + endfeature feature Assertions; measure Assert axi_protocol_assertion; source = "property: **.axi_ar_assert.*", "property: **.axi_aw_assert.*", "property: **.axi_b_assert.*", "property: **.axi_r_assert.*", "property: **.axi_w_assert.*"; @@ -1363,6 +1383,11 @@ plan "CVA6 Verification Master Plan"; source = "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_after_n_cycle", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_kill", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_same_cycle", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_valid_pulse", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_issue_multic", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_issue_resp_null_when_n_accept", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_res_multic", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_res_multic_we", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_result_dualwrite", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_sync_exc"; endmeasure endfeature + feature "Code Coverage"; + measure Line, Cond, Toggle, Assert, SnpsAvg CVXIF; + source = "tree: uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.ex_stage_i.gen_cvxif.cvxif_fu_i"; + endmeasure + endfeature feature "Extended instructions"; description = "XIF extended instructions"; feature Instructions;