diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv
index 998993fbe8..8b5998ae17 100644
--- a/core/acc_dispatcher.sv
+++ b/core/acc_dispatcher.sv
@@ -30,6 +30,10 @@ module acc_dispatcher
     output logic acc_fflags_valid_o,
     output logic [4:0] acc_fflags_o,
     // Interface with the CSRs
+    input priv_lvl_t ld_st_priv_lvl_i,
+    input logic sum_i,
+    input pmpcfg_t [15:0] pmpcfg_i,
+    input logic [15:0][PLEN-3:0] pmpaddr_i,
     input logic [2:0] fcsr_frm_i,
     output logic dirty_v_state_o,
     // Interface with the issue stage
diff --git a/core/cva6.sv b/core/cva6.sv
index cf5fd45f15..777ea3865f 100644
--- a/core/cva6.sv
+++ b/core/cva6.sv
@@ -1138,6 +1138,10 @@ module cva6
         .acc_cons_en_i         (acc_cons_en_csr),
         .acc_fflags_valid_o    (acc_resp_fflags_valid),
         .acc_fflags_o          (acc_resp_fflags),
+        .ld_st_priv_lvl_i      (ld_st_priv_lvl_csr_ex),
+        .sum_i                 (sum_csr_ex),
+        .pmpcfg_i              (pmpcfg),
+        .pmpaddr_i             (pmpaddr),
         .fcsr_frm_i            (frm_csr_id_issue_ex),
         .dirty_v_state_o       (dirty_v_state),
         .issue_instr_i         (issue_instr_id_acc),