diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 8ddf8fd478c..f31e0e41d2b 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -17,6 +17,7 @@ module csr_regfile import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace), parameter int AsidWidth = 1, parameter int unsigned MHPMCounterNum = 6 ) ( @@ -135,8 +136,11 @@ module csr_regfile // PMP addresses - ACC_DISPATCHER output logic [ 15:0][riscv::PLEN-3:0] pmpaddr_o, // TO_BE_COMPLETED - PERF_COUNTERS - output logic [ 31:0] mcountinhibit_o + output logic [ 31:0] mcountinhibit_o, + // RVFI + rvfi_csr_t rvfi_csr_o ); + // internal signal to keep track of access exceptions logic read_access_exception, update_access_exception, privilege_violation; logic csr_we, csr_read; @@ -191,8 +195,8 @@ module csr_regfile logic [63:0] cycle_q, cycle_d; logic [63:0] instret_q, instret_d; - riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d; - logic [15:0][riscv::PLEN-3:0] pmpaddr_q, pmpaddr_d; + riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d, pmpcfg_next; + logic [15:0][riscv::PLEN-3:0] pmpaddr_q, pmpaddr_d, pmpaddr_next; logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q; logic [3:0] index; @@ -1663,23 +1667,29 @@ module csr_regfile // wait for interrupt wfi_q <= wfi_d; // pmp - for (int i = 0; i < 16; i++) begin - if (i < CVA6Cfg.NrPMPEntries) begin - // We only support >=8-byte granularity, NA4 is disabled - if(!CVA6Cfg.PMPEntryReadOnly[i] && pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin - pmpcfg_q[i] <= pmpcfg_d[i]; - end else begin - pmpcfg_q[i] <= pmpcfg_q[i]; - end - if (!CVA6Cfg.PMPEntryReadOnly[i]) begin - pmpaddr_q[i] <= pmpaddr_d[i]; - end else begin - pmpaddr_q[i] <= pmpaddr_q[i]; - end + pmpcfg_q <= pmpcfg_next; + pmpaddr_q <= pmpaddr_next; + end + end + + // write logic pmp + always_comb begin : write + for (int i = 0; i < 16; i++) begin + if (i < CVA6Cfg.NrPMPEntries) begin + // We only support >=8-byte granularity, NA4 is disabled + if(!CVA6Cfg.PMPEntryReadOnly[i] && pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin + pmpcfg_next[i] <= pmpcfg_d[i]; end else begin - pmpcfg_q[i] <= '0; - pmpaddr_q[i] <= '0; + pmpcfg_next[i] <= pmpcfg_q[i]; + end + if (!CVA6Cfg.PMPEntryReadOnly[i]) begin + pmpaddr_next[i] <= pmpaddr_d[i]; + end else begin + pmpaddr_next[i] <= pmpaddr_q[i]; end + end else begin + pmpcfg_next[i] <= '0; + pmpaddr_next[i] <= '0; end end end @@ -1695,4 +1705,293 @@ module csr_regfile $stop(); end //pragma translate_on + + //pragma translate_off + + if (IsRVFI) begin + + //------------- + // RVFI + //------------- + assign rvfi_csr_o.fflags = CVA6Cfg.FpPresent ? + '{rdata: {'0, fcsr_q.fflags}, wdata: {'0, fcsr_d.fflags}, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.frm = CVA6Cfg.FpPresent ? + '{rdata: {'0, fcsr_q.frm}, wdata: {'0, fcsr_d.frm}, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.fcsr = CVA6Cfg.FpPresent ? + '{ + rdata: {'0, fcsr_q.frm, fcsr_q.fflags}, + wdata: {'0, fcsr_d.frm, fcsr_d.fflags}, + rmask: '1, + wmask: '1 + } + : '0; + assign rvfi_csr_o.ftran = CVA6Cfg.FpPresent ? + '{rdata: {'0, fcsr_q.fprec}, wdata: {'0, fcsr_d.fprec}, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.dcsr = CVA6Cfg.DebugEn ? + '{rdata: {'0, dcsr_q}, wdata: {'0, dcsr_d}, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.dpc = CVA6Cfg.DebugEn ? + '{rdata: {dpc_q}, wdata: dpc_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.dscratch0 = CVA6Cfg.DebugEn ? + '{rdata: dscratch0_q, wdata: dscratch0_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.dscratch1 = CVA6Cfg.DebugEn ? + '{rdata: dscratch1_q, wdata: dscratch1_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.sstatus = CVA6Cfg.RVS ? + '{ + rdata: mstatus_extended & ariane_pkg::SMODE_STATUS_READ_MASK[riscv::XLEN-1:0], + wdata: mstatus_extended & ariane_pkg::SMODE_STATUS_READ_MASK[riscv::XLEN-1:0], + rmask: '1, + wmask: '1 + } + : '0; + assign rvfi_csr_o.sie = CVA6Cfg.RVS ? + '{rdata: mie_q & mideleg_q, wdata: mie_d & mideleg_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.sip = CVA6Cfg.RVS ? + '{rdata: mip_q & mideleg_q, wdata: mip_d & mideleg_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.stvec = CVA6Cfg.RVS ? + '{rdata: stvec_q, wdata: stvec_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.scounteren = CVA6Cfg.RVS ? + '{rdata: scounteren_q, wdata: scounteren_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.sscratch = CVA6Cfg.RVS ? + '{rdata: sscratch_q, wdata: sscratch_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.sepc = CVA6Cfg.RVS ? + '{rdata: sepc_q, wdata: sepc_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.scause = CVA6Cfg.RVS ? + '{rdata: scause_q, wdata: scause_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.stval = CVA6Cfg.RVS ? + '{rdata: stval_q, wdata: stval_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.satp = CVA6Cfg.RVS ? + '{rdata: satp_q, wdata: satp_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.mstatus = '{ + rdata: mstatus_extended, + wdata: mstatus_extended, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.mstatush = riscv::XLEN == 32 ? + '{rdata: '0, wdata: '0, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.misa = '{rdata: IsaCode, wdata: IsaCode, rmask: '1, wmask: '1}; + assign rvfi_csr_o.medeleg = CVA6Cfg.RVS ? + '{rdata: medeleg_q, wdata: medeleg_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.mideleg = CVA6Cfg.RVS ? + '{rdata: mideleg_q, wdata: mideleg_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.mie = '{rdata: mie_q, wdata: mie_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mtvec = '{rdata: mtvec_q, wdata: mtvec_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mcounteren = '{ + rdata: mcounteren_q, + wdata: mcounteren_d, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.mscratch = '{rdata: mscratch_q, wdata: mscratch_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mepc = '{rdata: mepc_q, wdata: mepc_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mcause = '{rdata: mcause_q, wdata: mcause_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mtval = '{rdata: mtval_q, wdata: mtval_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mip = '{rdata: mip_q, wdata: mip_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.menvcfg = '{ + rdata: {'0, fiom_q}, + wdata: {'0, fiom_d}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.menvcfgh = riscv::XLEN == 32 ? + '{rdata: '0, wdata: '0, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.mvendorid = '{ + rdata: OPENHWGROUP_MVENDORID, + wdata: OPENHWGROUP_MVENDORID, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.marchid = '{ + rdata: ARIANE_MARCHID, + wdata: ARIANE_MARCHID, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.mhartid = '{rdata: hart_id_i, wdata: hart_id_i, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mcountinhibit = '{ + rdata: {'0, mcountinhibit_q}, + wdata: {'0, mcountinhibit_d}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.mcycle = '{ + rdata: cycle_q[riscv::XLEN-1:0], + wdata: cycle_d[riscv::XLEN-1:0], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.mcycleh = riscv::XLEN == 32 ? + '{rdata: cycle_q[63:32], wdata: cycle_d[63:32], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.minstret = '{ + rdata: instret_q[riscv::XLEN-1:0], + wdata: instret_d[riscv::XLEN-1:0], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.minstreth = riscv::XLEN == 32 ? + '{rdata: instret_q[63:32], wdata: instret_d[63:32], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.cycle = '{ + rdata: cycle_q[riscv::XLEN-1:0], + wdata: cycle_d[riscv::XLEN-1:0], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.cycleh = riscv::XLEN == 32 ? + '{rdata: cycle_q[63:32], wdata: cycle_d[63:32], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.instret = '{ + rdata: instret_q[riscv::XLEN-1:0], + wdata: instret_d[riscv::XLEN-1:0], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.instreth = riscv::XLEN == 32 ? + '{rdata: instret_q[63:32], wdata: instret_d[63:32], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.dcache = '{rdata: dcache_q, wdata: dcache_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.icache = '{rdata: icache_q, wdata: icache_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.acc_cons = CVA6Cfg.EnableAccelerator ? + '{rdata: acc_cons_q, wdata: acc_cons_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.pmpcfg0 = '{ + rdata: pmpcfg_q[riscv::XLEN/8-1:0], + wdata: pmpcfg_d[riscv::XLEN/8-1:0], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpcfg1 = riscv::XLEN == 32 ? + '{rdata: pmpcfg_q[7:4], wdata: pmpcfg_d[7:4], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.pmpcfg2 = '{ + rdata: pmpcfg_q[8+:riscv::XLEN/8], + wdata: pmpcfg_d[8+:riscv::XLEN/8], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpcfg3 = riscv::XLEN == 32 ? + '{rdata: pmpcfg_q[15:12], wdata: pmpcfg_d[15:12], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.pmpaddr0 = '{ + rdata: {'0, pmpaddr_q[0][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[0][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr1 = '{ + rdata: {'0, pmpaddr_q[1][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[1][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr2 = '{ + rdata: {'0, pmpaddr_q[2][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[2][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr3 = '{ + rdata: {'0, pmpaddr_q[3][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[3][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr4 = '{ + rdata: {'0, pmpaddr_q[4][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[4][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr5 = '{ + rdata: {'0, pmpaddr_q[5][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[5][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr6 = '{ + rdata: {'0, pmpaddr_q[6][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[6][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr7 = '{ + rdata: {'0, pmpaddr_q[7][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[7][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr8 = '{ + rdata: {'0, pmpaddr_q[8][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[8][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr9 = '{ + rdata: {'0, pmpaddr_q[9][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[9][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr10 = '{ + rdata: {'0, pmpaddr_q[10][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[10][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr11 = '{ + rdata: {'0, pmpaddr_q[11][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[11][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr12 = '{ + rdata: {'0, pmpaddr_q[12][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[12][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr13 = '{ + rdata: {'0, pmpaddr_q[13][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[13][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr14 = '{ + rdata: {'0, pmpaddr_q[14][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[14][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr15 = '{ + rdata: {'0, pmpaddr_q[15][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[15][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + + end //is RVFI + + //pragma translate_on + endmodule diff --git a/core/cva6.sv b/core/cva6.sv index 385a487908c..2a8323d38ef 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -19,7 +19,7 @@ module cva6 // CVA6 config parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg, parameter bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace), - // RVFI + parameter type rvfi_probes_t = struct packed { logic [TRANS_ID_BITS-1:0] issue_pointer; logic [CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] commit_pointer; @@ -42,6 +42,7 @@ module cva6 logic [riscv::PLEN-1:0] mem_paddr; logic debug_mode; logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata; + rvfi_csr_t csr; }, // AXI types @@ -463,7 +464,7 @@ module cva6 logic [riscv::PLEN-1:0] rvfi_mem_paddr; logic rvfi_is_compressed; rvfi_probes_t rvfi_probes; - + rvfi_csr_t rvfi_csr; // Accelerator port logic [ 63:0] inval_addr; @@ -881,6 +882,8 @@ module cva6 .pmpcfg_o (pmpcfg), .pmpaddr_o (pmpaddr), .mcountinhibit_o (mcountinhibit_csr_perf), + //RVFI + .rvfi_csr_o (rvfi_csr), .debug_req_i, .ipi_i, .irq_i, @@ -1377,9 +1380,10 @@ module cva6 if (IsRVFI) begin cva6_rvfi_probes #( - .CVA6Cfg (CVA6ExtendCfg), + .CVA6Cfg (CVA6ExtendCfg), + .IsRVFI (IsRVFI), .rvfi_probes_t(rvfi_probes_t) - ) i_cva6_rvfi_combi ( + ) i_cva6_rvfi_probes ( .flush_i (flush_ctrl_if), .issue_instr_ack_i (issue_instr_issue_id), @@ -1408,6 +1412,8 @@ module cva6 .debug_mode_i(debug_mode), .wdata_i (wdata_commit_id), + .csr_i(rvfi_csr), + .rvfi_probes_o(rvfi_probes_o) ); diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv index d4d9f103424..17d5ba4bddd 100644 --- a/core/cva6_rvfi.sv +++ b/core/cva6_rvfi.sv @@ -15,13 +15,16 @@ module cva6_rvfi parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type rvfi_instr_t = logic, parameter type rvfi_probes_t = logic + ) ( input logic clk_i, input logic rst_ni, input rvfi_probes_t rvfi_probes_i, - output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o + output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr_o, + output rvfi_csr_t rvfi_csr_o + ); @@ -146,6 +149,8 @@ module cva6_rvfi logic [ (riscv::XLEN/8)-1:0] lsu_wmask; logic [ TRANS_ID_BITS-1:0] lsu_addr_trans_id; + riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d; + assign flush = rvfi_probes_i.flush; assign issue_instr_ack = rvfi_probes_i.issue_instr_ack; assign fetch_entry_valid = rvfi_probes_i.fetch_entry_valid; @@ -263,33 +268,102 @@ module cva6_rvfi for (int i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin logic exception; exception = commit_instr[i].valid && ex_commit.valid; - rvfi_o[i].valid = (commit_ack[i] && !ex_commit.valid) || + rvfi_instr_o[i].valid = (commit_ack[i] && !ex_commit.valid) || (exception && (ex_commit.cause == riscv::ENV_CALL_MMODE || ex_commit.cause == riscv::ENV_CALL_SMODE || ex_commit.cause == riscv::ENV_CALL_UMODE)); - rvfi_o[i].insn = mem_q[commit_pointer[i]].instr; + rvfi_instr_o[i].insn = mem_q[commit_pointer[i]].instr; // when trap, the instruction is not executed - rvfi_o[i].trap = exception; - rvfi_o[i].cause = ex_commit.cause; - rvfi_o[i].mode = (CVA6ExtendCfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl; - rvfi_o[i].ixl = riscv::XLEN == 64 ? 2 : 1; - rvfi_o[i].rs1_addr = commit_instr[i].rs1[4:0]; - rvfi_o[i].rs2_addr = commit_instr[i].rs2[4:0]; - rvfi_o[i].rd_addr = commit_instr[i].rd[4:0]; - rvfi_o[i].rd_wdata = (CVA6ExtendCfg.FpPresent && is_rd_fpr(commit_instr[i].op)) ? + rvfi_instr_o[i].trap = exception; + rvfi_instr_o[i].cause = ex_commit.cause; + rvfi_instr_o[i].mode = (CVA6ExtendCfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl; + rvfi_instr_o[i].ixl = riscv::XLEN == 64 ? 2 : 1; + rvfi_instr_o[i].rs1_addr = commit_instr[i].rs1[4:0]; + rvfi_instr_o[i].rs2_addr = commit_instr[i].rs2[4:0]; + rvfi_instr_o[i].rd_addr = commit_instr[i].rd[4:0]; + rvfi_instr_o[i].rd_wdata = (CVA6ExtendCfg.FpPresent && is_rd_fpr(commit_instr[i].op)) ? commit_instr[i].result : wdata[i]; - rvfi_o[i].pc_rdata = commit_instr[i].pc; - rvfi_o[i].mem_addr = mem_q[commit_pointer[i]].lsu_addr; + rvfi_instr_o[i].pc_rdata = commit_instr[i].pc; + rvfi_instr_o[i].mem_addr = mem_q[commit_pointer[i]].lsu_addr; // So far, only write paddr is reported. TODO: read paddr - rvfi_o[i].mem_paddr = mem_paddr; - rvfi_o[i].mem_wmask = mem_q[commit_pointer[i]].lsu_wmask; - rvfi_o[i].mem_wdata = mem_q[commit_pointer[i]].lsu_wdata; - rvfi_o[i].mem_rmask = mem_q[commit_pointer[i]].lsu_rmask; - rvfi_o[i].mem_rdata = commit_instr[i].result; - rvfi_o[i].rs1_rdata = mem_q[commit_pointer[i]].rs1_rdata; - rvfi_o[i].rs2_rdata = mem_q[commit_pointer[i]].rs2_rdata; + rvfi_instr_o[i].mem_paddr = mem_paddr; + rvfi_instr_o[i].mem_wmask = mem_q[commit_pointer[i]].lsu_wmask; + rvfi_instr_o[i].mem_wdata = mem_q[commit_pointer[i]].lsu_wdata; + rvfi_instr_o[i].mem_rmask = mem_q[commit_pointer[i]].lsu_rmask; + rvfi_instr_o[i].mem_rdata = commit_instr[i].result; + rvfi_instr_o[i].rs1_rdata = mem_q[commit_pointer[i]].rs1_rdata; + rvfi_instr_o[i].rs2_rdata = mem_q[commit_pointer[i]].rs2_rdata; end end + //---------------------------------------------------------------------------------------------------------- + // CSR + //---------------------------------------------------------------------------------------------------------- + + always_comb begin + + rvfi_csr_o = rvfi_probes_i.csr; + + if (riscv::XLEN == 32) begin + pmpcfg_q[3:0] = rvfi_probes_i.csr.pmpcfg0.rdata; + pmpcfg_q[7:4] = rvfi_probes_i.csr.pmpcfg1.rdata; + pmpcfg_q[11:8] = rvfi_probes_i.csr.pmpcfg2.rdata; + pmpcfg_q[15:12] = rvfi_probes_i.csr.pmpcfg3.rdata; + pmpcfg_d[3:0] = rvfi_probes_i.csr.pmpcfg0.rdata; + pmpcfg_d[7:4] = rvfi_probes_i.csr.pmpcfg1.rdata; + pmpcfg_d[11:8] = rvfi_probes_i.csr.pmpcfg2.rdata; + pmpcfg_d[15:12] = rvfi_probes_i.csr.pmpcfg3.rdata; + pmpcfg_q[3:0] = rvfi_probes_i.csr.pmpcfg0.wdata; + pmpcfg_q[7:4] = rvfi_probes_i.csr.pmpcfg1.wdata; + pmpcfg_q[11:8] = rvfi_probes_i.csr.pmpcfg2.wdata; + pmpcfg_q[15:12] = rvfi_probes_i.csr.pmpcfg3.wdata; + pmpcfg_q[3:0] = rvfi_probes_i.csr.pmpcfg0.wdata; + pmpcfg_q[7:4] = rvfi_probes_i.csr.pmpcfg1.wdata; + pmpcfg_q[11:8] = rvfi_probes_i.csr.pmpcfg2.wdata; + pmpcfg_q[15:12] = rvfi_probes_i.csr.pmpcfg3.wdata; + end else begin + pmpcfg_q[7:0] = rvfi_probes_i.csr.pmpcfg0.rdata; + pmpcfg_q[15:8] = rvfi_probes_i.csr.pmpcfg0.rdata; + pmpcfg_d[7:0] = rvfi_probes_i.csr.pmpcfg0.wdata; + pmpcfg_d[15:8] = rvfi_probes_i.csr.pmpcfg0.wdata; + end + + rvfi_csr_o.pmpaddr0.rdata[0] = pmpcfg_q[0].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr0.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr1.rdata[0] = pmpcfg_q[1].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr1.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr2.rdata[0] = pmpcfg_q[2].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr2.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr3.rdata[0] = pmpcfg_q[3].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr3.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr4.rdata[0] = pmpcfg_q[4].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr4.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr5.rdata[0] = pmpcfg_q[5].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr5.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr6.rdata[0] = pmpcfg_q[6].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr6.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr7.rdata[0] = pmpcfg_q[7].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr7.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr8.rdata[0] = pmpcfg_q[8].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr8.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr9.rdata[0] = pmpcfg_q[9].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr9.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr10.rdata[0] = pmpcfg_q[10].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr10.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr11.rdata[0] = pmpcfg_q[11].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr11.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr12.rdata[0] = pmpcfg_q[12].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr12.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr13.rdata[0] = pmpcfg_q[13].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr13.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr14.rdata[0] = pmpcfg_q[14].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr14.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr15.rdata[0] = pmpcfg_q[15].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr15.rdata[0] : 1'b0; + + rvfi_csr_o.pmpaddr0.wdata[0] = pmpcfg_q[0].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr0.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr1.wdata[0] = pmpcfg_q[1].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr1.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr2.wdata[0] = pmpcfg_q[2].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr2.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr3.wdata[0] = pmpcfg_q[3].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr3.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr4.wdata[0] = pmpcfg_q[4].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr4.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr5.wdata[0] = pmpcfg_q[5].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr5.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr6.wdata[0] = pmpcfg_q[6].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr6.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr7.wdata[0] = pmpcfg_q[7].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr7.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr8.wdata[0] = pmpcfg_q[8].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr8.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr9.wdata[0] = pmpcfg_q[9].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr9.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr10.wdata[0] = pmpcfg_q[10].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr10.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr11.wdata[0] = pmpcfg_q[11].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr11.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr12.wdata[0] = pmpcfg_q[12].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr12.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr13.wdata[0] = pmpcfg_q[13].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr13.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr14.wdata[0] = pmpcfg_q[14].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr14.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr15.wdata[0] = pmpcfg_q[15].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr15.wdata[0] : 1'b0; + + end + + endmodule diff --git a/core/cva6_rvfi_probes.sv b/core/cva6_rvfi_probes.sv index 81d2c5df3df..0013fcf1740 100644 --- a/core/cva6_rvfi_probes.sv +++ b/core/cva6_rvfi_probes.sv @@ -14,6 +14,7 @@ module cva6_rvfi_probes #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type rvfi_probes_t = logic + ) ( input logic flush_i, @@ -36,13 +37,16 @@ module cva6_rvfi_probes input exception_t ex_commit_i, input riscv::priv_lvl_t priv_lvl_i, - input lsu_ctrl_t lsu_ctrl_i, - input logic [ CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, - input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, - input logic [ riscv::PLEN-1:0] mem_paddr_i, - input logic debug_mode_i, - input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i, - output rvfi_probes_t rvfi_probes_o + input lsu_ctrl_t lsu_ctrl_i, + input logic [ CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + input logic [ riscv::PLEN-1:0] mem_paddr_i, + input logic debug_mode_i, + input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i, + + input rvfi_csr_t csr_i, + + output rvfi_probes_t rvfi_probes_o ); always_comb begin @@ -75,6 +79,8 @@ module cva6_rvfi_probes rvfi_probes_o.debug_mode = debug_mode_i; rvfi_probes_o.wdata = wdata_i; + rvfi_probes_o.csr = csr_i; + end diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 1616fafa20a..b479af71ff4 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -675,6 +675,87 @@ package ariane_pkg; localparam RVFI = cva6_config_pkg::CVA6ConfigRvfiTrace; + // RVFI CSR element + typedef struct packed { + riscv::xlen_t rdata; + riscv::xlen_t rmask; + riscv::xlen_t wdata; + riscv::xlen_t wmask; + } rvfi_csr_elmt_t; + + // RVFI CSR structure + typedef struct packed { + rvfi_csr_elmt_t fflags; + rvfi_csr_elmt_t frm; + rvfi_csr_elmt_t fcsr; + rvfi_csr_elmt_t ftran; + rvfi_csr_elmt_t dcsr; + rvfi_csr_elmt_t dpc; + rvfi_csr_elmt_t dscratch0; + rvfi_csr_elmt_t dscratch1; + rvfi_csr_elmt_t sstatus; + rvfi_csr_elmt_t sie; + rvfi_csr_elmt_t sip; + rvfi_csr_elmt_t stvec; + rvfi_csr_elmt_t scounteren; + rvfi_csr_elmt_t sscratch; + rvfi_csr_elmt_t sepc; + rvfi_csr_elmt_t scause; + rvfi_csr_elmt_t stval; + rvfi_csr_elmt_t satp; + rvfi_csr_elmt_t mstatus; + rvfi_csr_elmt_t mstatush; + rvfi_csr_elmt_t misa; + rvfi_csr_elmt_t medeleg; + rvfi_csr_elmt_t mideleg; + rvfi_csr_elmt_t mie; + rvfi_csr_elmt_t mtvec; + rvfi_csr_elmt_t mcounteren; + rvfi_csr_elmt_t mscratch; + rvfi_csr_elmt_t mepc; + rvfi_csr_elmt_t mcause; + rvfi_csr_elmt_t mtval; + rvfi_csr_elmt_t mip; + rvfi_csr_elmt_t menvcfg; + rvfi_csr_elmt_t menvcfgh; + rvfi_csr_elmt_t mvendorid; + rvfi_csr_elmt_t marchid; + rvfi_csr_elmt_t mhartid; + rvfi_csr_elmt_t mcountinhibit; + rvfi_csr_elmt_t mcycle; + rvfi_csr_elmt_t mcycleh; + rvfi_csr_elmt_t minstret; + rvfi_csr_elmt_t minstreth; + rvfi_csr_elmt_t cycle; + rvfi_csr_elmt_t cycleh; + rvfi_csr_elmt_t instret; + rvfi_csr_elmt_t instreth; + rvfi_csr_elmt_t dcache; + rvfi_csr_elmt_t icache; + rvfi_csr_elmt_t acc_cons; + rvfi_csr_elmt_t pmpcfg0; + rvfi_csr_elmt_t pmpcfg1; + rvfi_csr_elmt_t pmpcfg2; + rvfi_csr_elmt_t pmpcfg3; + rvfi_csr_elmt_t pmpaddr0; + rvfi_csr_elmt_t pmpaddr1; + rvfi_csr_elmt_t pmpaddr2; + rvfi_csr_elmt_t pmpaddr3; + rvfi_csr_elmt_t pmpaddr4; + rvfi_csr_elmt_t pmpaddr5; + rvfi_csr_elmt_t pmpaddr6; + rvfi_csr_elmt_t pmpaddr7; + rvfi_csr_elmt_t pmpaddr8; + rvfi_csr_elmt_t pmpaddr9; + rvfi_csr_elmt_t pmpaddr10; + rvfi_csr_elmt_t pmpaddr11; + rvfi_csr_elmt_t pmpaddr12; + rvfi_csr_elmt_t pmpaddr13; + rvfi_csr_elmt_t pmpaddr14; + rvfi_csr_elmt_t pmpaddr15; + } rvfi_csr_t; + + typedef struct packed { logic [riscv::VLEN-1:0] pc; // PC of instruction logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv index 3530da0a9a7..37b84f8a6e0 100644 --- a/corev_apu/tb/ariane_testharness.sv +++ b/corev_apu/tb/ariane_testharness.sv @@ -36,6 +36,8 @@ module ariane_testharness #( localparam [7:0] hart_id = '0; + + // RVFI localparam type rvfi_instr_t = struct packed { logic [config_pkg::NRET-1:0] valid; logic [config_pkg::NRET*64-1:0] order; @@ -61,7 +63,7 @@ module ariane_testharness #( logic [config_pkg::NRET*riscv::XLEN-1:0] mem_rdata; logic [config_pkg::NRET*riscv::XLEN-1:0] mem_wdata; }; - + localparam type rvfi_probes_t = struct packed { logic [ariane_pkg::TRANS_ID_BITS-1:0] issue_pointer; logic [CVA6Cfg.NrCommitPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] commit_pointer; @@ -84,6 +86,7 @@ module ariane_testharness #( logic [riscv::PLEN-1:0] mem_paddr; logic debug_mode; logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata; + ariane_pkg::rvfi_csr_t csr; }; // disable test-enable @@ -651,6 +654,7 @@ module ariane_testharness #( ariane_axi::req_t axi_ariane_req; ariane_axi::resp_t axi_ariane_resp; rvfi_probes_t rvfi_probes; + ariane_pkg::rvfi_csr_t rvfi_csr; rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr; ariane #( @@ -698,6 +702,8 @@ module ariane_testharness #( end end + + cva6_rvfi #( .CVA6Cfg (CVA6Cfg), .rvfi_instr_t(rvfi_instr_t), @@ -706,7 +712,8 @@ module ariane_testharness #( .clk_i (clk_i), .rst_ni (rst_ni), .rvfi_probes_i(rvfi_probes), - .rvfi_o(rvfi_instr) + .rvfi_instr_o(rvfi_instr), + .rvfi_csr_o(rvfi_csr) ); rvfi_tracer #( @@ -720,6 +727,7 @@ module ariane_testharness #( .clk_i(clk_i), .rst_ni(rst_ni), .rvfi_i(rvfi_instr), + .rvfi_csr_i(rvfi_csr), .end_of_test_o(rvfi_exit) ); diff --git a/corev_apu/tb/rvfi_tracer.sv b/corev_apu/tb/rvfi_tracer.sv index 75f68beb576..a33b0585b20 100644 --- a/corev_apu/tb/rvfi_tracer.sv +++ b/corev_apu/tb/rvfi_tracer.sv @@ -10,6 +10,7 @@ module rvfi_tracer #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type rvfi_instr_t = logic, + parameter type rvfi_csr_t = logic, // parameter logic [7:0] HART_ID = '0, parameter int unsigned DEBUG_START = 0, @@ -18,6 +19,7 @@ module rvfi_tracer #( input logic clk_i, input logic rst_ni, input rvfi_instr_t[CVA6Cfg.NrCommitPorts-1:0] rvfi_i, + input ariane_pkg::rvfi_csr_t rvfi_csr_i, output logic[31:0] end_of_test_o ); diff --git a/pd/synth/cva6_synth.tcl b/pd/synth/cva6_synth.tcl index 5ba39d4234d..d05c2e2859c 100644 --- a/pd/synth/cva6_synth.tcl +++ b/pd/synth/cva6_synth.tcl @@ -58,6 +58,9 @@ set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcach set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] + +set_false_path -to [get_ports {rvfi_probes_o}] + # Check the current design for consistency check_design -summary > ${DCRM_CHECK_DESIGN_REPORT} diff --git a/verif/tb/uvmt/cva6_tb_wrapper.sv b/verif/tb/uvmt/cva6_tb_wrapper.sv index a63ebf0cd97..f60146941d2 100644 --- a/verif/tb/uvmt/cva6_tb_wrapper.sv +++ b/verif/tb/uvmt/cva6_tb_wrapper.sv @@ -47,6 +47,7 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( input logic [XLEN-1:0] boot_addr_i, output logic [31:0] tb_exit_o, output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o, + output ariane_pkg::rvfi_csr_t rvfi_csr_o, input cvxif_pkg::cvxif_resp_t cvxif_resp, output cvxif_pkg::cvxif_req_t cvxif_req, uvma_axi_intf axi_slave, @@ -77,6 +78,7 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( logic [riscv::PLEN-1:0] mem_paddr; logic debug_mode; logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata; + ariane_pkg::rvfi_csr_t csr; }; ariane_axi::req_t axi_ariane_req; @@ -87,8 +89,10 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr; rvfi_probes_t rvfi_probes; + ariane_pkg::rvfi_csr_t rvfi_csr; assign rvfi_o = rvfi_instr; - + assign rvfi_csr_o = rvfi_csr; + cva6 #( .CVA6Cfg ( CVA6Cfg ), .rvfi_probes_t ( rvfi_probes_t ), @@ -121,7 +125,8 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( .clk_i (clk_i), .rst_ni (rst_ni), .rvfi_probes_i(rvfi_probes), - .rvfi_o(rvfi_instr) + .rvfi_instr_o(rvfi_instr), + .rvfi_csr_o(rvfi_csr) ); rvfi_tracer #( @@ -135,6 +140,7 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( .clk_i(clk_i), .rst_ni(rst_ni), .rvfi_i(rvfi_instr), + .rvfi_csr_i(rvfi_csr), .end_of_test_o(tb_exit_o) ) ; diff --git a/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv b/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv index bd9d2b62029..42bd6243b60 100644 --- a/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv +++ b/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv @@ -31,7 +31,8 @@ module uvmt_cva6_dut_wrap # ( uvmt_default_inputs_intf default_inputs_vif, uvme_cva6_core_cntrl_if core_cntrl_if, output logic[31:0] tb_exit_o, - output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o + output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o, + output ariane_pkg::rvfi_csr_t rvfi_csr_o ); @@ -39,7 +40,7 @@ module uvmt_cva6_dut_wrap # ( cva6_tb_wrapper #( .CVA6Cfg ( CVA6Cfg ), .IsRVFI ( IsRVFI ), - .rvfi_instr_t ( rvfi_instr_t ), + .rvfi_instr_t ( rvfi_instr_t ), // .AXI_USER_EN (AXI_USER_EN), .NUM_WORDS (NUM_WORDS) @@ -54,6 +55,7 @@ module uvmt_cva6_dut_wrap # ( .axi_switch_vif ( axi_switch_vif ), .default_inputs_vif ( default_inputs_vif ), .tb_exit_o ( tb_exit_o ), + .rvfi_csr_o ( rvfi_csr_o ), .rvfi_o ( rvfi_o ) ); diff --git a/verif/tb/uvmt/uvmt_cva6_tb.sv b/verif/tb/uvmt/uvmt_cva6_tb.sv index 986f165f778..791ff681817 100644 --- a/verif/tb/uvmt/uvmt_cva6_tb.sv +++ b/verif/tb/uvmt/uvmt_cva6_tb.sv @@ -35,6 +35,9 @@ module uvmt_cva6_tb; // CVA6 config localparam config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg; localparam bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace); + + // RVFI + localparam type rvfi_instr_t = struct packed { logic [config_pkg::NRET-1:0] valid; logic [config_pkg::NRET*64-1:0] order; @@ -117,9 +120,9 @@ module uvmt_cva6_tb; */ uvmt_cva6_dut_wrap #( - .CVA6Cfg ( CVA6Cfg ), - .IsRVFI ( IsRVFI ), - .rvfi_instr_t ( rvfi_instr_t ), + .CVA6Cfg ( CVA6Cfg ), + .IsRVFI ( IsRVFI ), + .rvfi_instr_t ( rvfi_instr_t ), // .AXI_USER_EN (AXI_USER_EN), .NUM_WORDS (NUM_WORDS) @@ -131,7 +134,8 @@ module uvmt_cva6_tb; .default_inputs_vif (default_inputs_vif), .core_cntrl_if(core_cntrl_if), .tb_exit_o(rvfi_if.tb_exit_o), - .rvfi_o(rvfi_if.rvfi_o) + .rvfi_o(rvfi_if.rvfi_o), + .rvfi_csr_o() ); for (genvar i = 0; i < RVFI_NRET; i++) begin