From 2c6e8e3473c9121f6f817c485c14d6879fdd65df Mon Sep 17 00:00:00 2001 From: Jean-Roch Coulon Date: Wed, 7 Feb 2024 17:36:27 +0100 Subject: [PATCH] Fix Verible & co --- core/include/cv32a65x_config_pkg.sv | 4 --- core/issue_stage.sv | 2 +- docs/04_cv32a65x_design/source/port_bht.rst | 4 +-- docs/04_cv32a65x_design/source/port_btb.rst | 4 +-- docs/04_cv32a65x_design/source/port_cva6.rst | 6 ++-- .../source/port_frontend.rst | 8 ++--- .../source/port_id_stage.rst | 6 ++-- .../source/port_instr_queue.rst | 16 ++++----- .../source/port_instr_realign.rst | 10 +++--- .../source/port_instr_scan.rst | 6 ++-- .../source/port_issue_stage.rst | 36 +++++++++---------- docs/04_cv32a65x_design/source/port_ras.rst | 2 +- docs/scripts/table_port_builder.py | 8 +++-- 13 files changed, 55 insertions(+), 57 deletions(-) diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index 06cd5a1f93e..4fe74bfd03b 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -92,7 +92,6 @@ package cva6_config_pkg; XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn), - // Extended RVF: bit'(0), RVD: bit'(0), FpPresent: bit'(0), @@ -119,15 +118,12 @@ package cva6_config_pkg; PMPAddrRstVal: {16{64'h0}}, PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, - // idempotent region NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), NonIdempotentLength: 1024'({64'b0, 64'b0}), NrExecuteRegionRules: unsigned'(3), - // DRAM, Boot ROM, Debug Module ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), - // cached region NrCachedRegionRules: unsigned'(1), CachedRegionAddrBase: 1024'({64'h8000_0000}), CachedRegionLength: 1024'({64'h40000000}), diff --git a/core/issue_stage.sv b/core/issue_stage.sv index 5a1b0dc097a..b8dc224e1bf 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -108,7 +108,7 @@ module issue_stage // TO_BE_COMPLETED - EX_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i, // TO_BE_COMPLETED - COMMIT_STAGE - output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] COMMIT_STAGE, + output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o, // TO_BE_COMPLETED - COMMIT_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // Issue stall - PERF_COUNTERS diff --git a/docs/04_cv32a65x_design/source/port_bht.rst b/docs/04_cv32a65x_design/source/port_bht.rst index 052cfeb833e..66f695d0bc2 100644 --- a/docs/04_cv32a65x_design/source/port_bht.rst +++ b/docs/04_cv32a65x_design/source/port_bht.rst @@ -45,7 +45,7 @@ * - ``vpc_i`` - in - CACHE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Virtual PC * - ``bht_update_i`` @@ -57,5 +57,5 @@ * - ``bht_prediction_o`` - out - FRONTEND - - ariane_pkg::bht_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] + - ariane_pkg::bht_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0] - Prediction from bht diff --git a/docs/04_cv32a65x_design/source/port_btb.rst b/docs/04_cv32a65x_design/source/port_btb.rst index 7647655912f..cfb7362c2fc 100644 --- a/docs/04_cv32a65x_design/source/port_btb.rst +++ b/docs/04_cv32a65x_design/source/port_btb.rst @@ -45,7 +45,7 @@ * - ``vpc_i`` - in - CACHE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Virtual PC * - ``btb_update_i`` @@ -57,5 +57,5 @@ * - ``btb_prediction_o`` - out - FRONTEND - - ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] + - ariane_pkg::btb_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0] - BTB Prediction diff --git a/docs/04_cv32a65x_design/source/port_cva6.rst b/docs/04_cv32a65x_design/source/port_cva6.rst index bf1249f2d1c..2afd967873e 100644 --- a/docs/04_cv32a65x_design/source/port_cva6.rst +++ b/docs/04_cv32a65x_design/source/port_cva6.rst @@ -33,19 +33,19 @@ * - ``boot_addr_i`` - in - SUBSYSTEM - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Reset boot address * - ``hart_id_i`` - in - SUBSYSTEM - - logic [riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - Hard ID reflected as CSR * - ``irq_i`` - in - SUBSYSTEM - - logic [1:0] + - logic[1:0] - Level sensitive (async) interrupts * - ``ipi_i`` diff --git a/docs/04_cv32a65x_design/source/port_frontend.rst b/docs/04_cv32a65x_design/source/port_frontend.rst index 9306ba75fe2..1d8b6b31a38 100644 --- a/docs/04_cv32a65x_design/source/port_frontend.rst +++ b/docs/04_cv32a65x_design/source/port_frontend.rst @@ -57,7 +57,7 @@ * - ``boot_addr_i`` - in - SUBSYSTEM - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Next PC when reset * - ``resolved_branch_i`` @@ -75,13 +75,13 @@ * - ``pc_commit_i`` - in - COMMIT - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Next PC when flushing pipeline * - ``epc_i`` - in - CSR - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Next PC when returning from exception * - ``eret_i`` @@ -93,7 +93,7 @@ * - ``trap_vector_base_i`` - in - CSR - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Next PC when jumping into exception * - ``ex_valid_i`` diff --git a/docs/04_cv32a65x_design/source/port_id_stage.rst b/docs/04_cv32a65x_design/source/port_id_stage.rst index 4961073a27e..dccc51ed538 100644 --- a/docs/04_cv32a65x_design/source/port_id_stage.rst +++ b/docs/04_cv32a65x_design/source/port_id_stage.rst @@ -69,7 +69,7 @@ * - ``orig_instr_o`` - out - ISSUE - - logic [31:0] + - logic[31:0] - instruction value * - ``issue_entry_valid_o`` @@ -111,7 +111,7 @@ * - ``frm_i`` - in - CSR - - logic [2:0] + - logic[2:0] - Report floating point dynamic rounding mode * - ``vs_i`` @@ -123,7 +123,7 @@ * - ``irq_i`` - in - SUBSYSTEM - - logic [1:0] + - logic[1:0] - Level sensitive (async) interrupts * - ``irq_ctrl_i`` diff --git a/docs/04_cv32a65x_design/source/port_instr_queue.rst b/docs/04_cv32a65x_design/source/port_instr_queue.rst index 9daf85819b4..04c5d2818d3 100644 --- a/docs/04_cv32a65x_design/source/port_instr_queue.rst +++ b/docs/04_cv32a65x_design/source/port_instr_queue.rst @@ -39,19 +39,19 @@ * - ``instr_i`` - in - instr_realign - - logic [ariane_pkg::INSTR_PER_FETCH-1:0][31:0] + - logic[ariane_pkg::INSTR_PER_FETCH-1:0][31:0] - Instruction * - ``addr_i`` - in - instr_realign - - logic [ariane_pkg::INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] + - logic[ariane_pkg::INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] - Instruction address * - ``valid_i`` - in - instr_realign - - logic [ariane_pkg::INSTR_PER_FETCH-1:0] + - logic[ariane_pkg::INSTR_PER_FETCH-1:0] - Instruction is valid * - ``ready_o`` @@ -63,7 +63,7 @@ * - ``consumed_o`` - out - FRONTEND - - logic [ariane_pkg::INSTR_PER_FETCH-1:0] + - logic[ariane_pkg::INSTR_PER_FETCH-1:0] - Indicates instructions consummed, or popped by ID_STAGE * - ``exception_i`` @@ -75,19 +75,19 @@ * - ``exception_addr_i`` - in - CACHE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Exception address * - ``predict_address_i`` - in - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Branch predict * - ``cf_type_i`` - in - FRONTEND - - ariane_pkg::cf_t [ariane_pkg::INSTR_PER_FETCH-1:0] + - ariane_pkg::cf_t[ariane_pkg::INSTR_PER_FETCH-1:0] - Instruction predict address * - ``replay_o`` @@ -99,7 +99,7 @@ * - ``replay_addr_o`` - out - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Address at which to replay the fetch * - ``fetch_entry_o`` diff --git a/docs/04_cv32a65x_design/source/port_instr_realign.rst b/docs/04_cv32a65x_design/source/port_instr_realign.rst index dc1b2c5a409..30f87a5d0b0 100644 --- a/docs/04_cv32a65x_design/source/port_instr_realign.rst +++ b/docs/04_cv32a65x_design/source/port_instr_realign.rst @@ -51,29 +51,29 @@ * - ``address_i`` - in - CACHE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - 32-bit block address * - ``data_i`` - in - CACHE - - logic [FETCH_WIDTH-1:0] + - logic[FETCH_WIDTH-1:0] - 32-bit block * - ``valid_o`` - out - FRONTEND - - logic [INSTR_PER_FETCH-1:0] + - logic[INSTR_PER_FETCH-1:0] - instruction is valid * - ``addr_o`` - out - FRONTEND - - logic [INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] + - logic[INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] - Instruction address * - ``instr_o`` - out - none - - logic [INSTR_PER_FETCH-1:0][31:0] + - logic[INSTR_PER_FETCH-1:0][31:0] - none diff --git a/docs/04_cv32a65x_design/source/port_instr_scan.rst b/docs/04_cv32a65x_design/source/port_instr_scan.rst index 1fad65915a4..4a88596fb17 100644 --- a/docs/04_cv32a65x_design/source/port_instr_scan.rst +++ b/docs/04_cv32a65x_design/source/port_instr_scan.rst @@ -21,7 +21,7 @@ * - ``instr_i`` - in - instr_realign - - logic [31:0] + - logic[31:0] - Instruction to be predecoded * - ``rvi_return_o`` @@ -57,7 +57,7 @@ * - ``rvi_imm_o`` - out - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Instruction immediat * - ``rvc_branch_o`` @@ -99,5 +99,5 @@ * - ``rvc_imm_o`` - out - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Instruction compressed immediat diff --git a/docs/04_cv32a65x_design/source/port_issue_stage.rst b/docs/04_cv32a65x_design/source/port_issue_stage.rst index ef76c1493d6..8326d90c4b5 100644 --- a/docs/04_cv32a65x_design/source/port_issue_stage.rst +++ b/docs/04_cv32a65x_design/source/port_issue_stage.rst @@ -63,7 +63,7 @@ * - ``orig_instr_i`` - in - ID_STAGE - - logic [31:0] + - logic[31:0] - instruction value * - ``decoded_instr_valid_i`` @@ -105,7 +105,7 @@ * - ``pc_o`` - out - EX_STAGE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - TO_BE_COMPLETED * - ``is_compressed_instr_o`` @@ -177,13 +177,13 @@ * - ``fpu_fmt_o`` - out - EX_STAGE - - logic [1:0] + - logic[1:0] - Report FP fmt field * - ``fpu_rm_o`` - out - EX_STAGE - - logic [2:0] + - logic[2:0] - report FP rm field * - ``csr_valid_o`` @@ -207,7 +207,7 @@ * - ``x_off_instr_o`` - out - EX_STAGE - - logic [31:0] + - logic[31:0] - TO_BE_COMPLETED * - ``issue_instr_o`` @@ -225,7 +225,7 @@ * - ``trans_id_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrWbPorts-1:0][TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.NrWbPorts-1:0][TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``resolved_branch_i`` @@ -237,19 +237,19 @@ * - ``wbdata_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] - TO_BE_COMPLETED * - ``ex_ex_i`` - in - EX_STAGE - - exception_t [CVA6Cfg.NrWbPorts-1:0] + - exception_t[CVA6Cfg.NrWbPorts-1:0] - exception from execute stage or CVXIF offloaded instruction * - ``wt_valid_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrWbPorts-1:0] + - logic[CVA6Cfg.NrWbPorts-1:0] - TO_BE_COMPLETED * - ``x_we_i`` @@ -261,37 +261,37 @@ * - ``waddr_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0][4:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][4:0] - TO_BE_COMPLETED * - ``wdata_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] - TO_BE_COMPLETED * - ``we_gpr_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - TO_BE_COMPLETED * - ``we_fpr_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - TO_BE_COMPLETED - * - ``COMMIT_STAGE`` + * - ``commit_instr_o`` - out - COMMIT_STAGE - - scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] + - scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0] - TO_BE_COMPLETED * - ``commit_ack_i`` - in - COMMIT_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - TO_BE_COMPLETED * - ``stall_issue_o`` @@ -303,11 +303,11 @@ * - ``rvfi_issue_pointer_o`` - out - SUBSYSTEM - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - Information dedicated to RVFI * - ``rvfi_commit_pointer_o`` - out - SUBSYSTEM - - logic [CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] - Information dedicated to RVFI diff --git a/docs/04_cv32a65x_design/source/port_ras.rst b/docs/04_cv32a65x_design/source/port_ras.rst index f8a83cbbae0..f6d2372f23a 100644 --- a/docs/04_cv32a65x_design/source/port_ras.rst +++ b/docs/04_cv32a65x_design/source/port_ras.rst @@ -51,7 +51,7 @@ * - ``data_i`` - in - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Data to be pushed * - ``data_o`` diff --git a/docs/scripts/table_port_builder.py b/docs/scripts/table_port_builder.py index 29946243b39..abca98aa054 100755 --- a/docs/scripts/table_port_builder.py +++ b/docs/scripts/table_port_builder.py @@ -56,16 +56,18 @@ def __init__( description = "none" connection = "none" for line in fin: - e = re.match(r"^ +(?:(in|out))put ([\S]*(?: [\S]*|)) ([\S]*)\n", line) + e = re.match(r"^ +(?:(in|out))put +([\S]*(?: +.* *|)) ([\S]*)\n", line) d = re.match(r"^ +\/\/ (.*) - ([\S]*)\n", line) if d: description = d.group(1) connection = d.group(2) if e: name = e.group(3) - name = name.split(",") + name = name.replace(",", "") + data_type = e.group(2) + data_type = data_type.replace(" ", "") ports.append( - PortIO(name[0], e.group(1), e.group(2), description, connection) + PortIO(name, e.group(1), data_type, description, connection) ) description = "none" connection = "none"