diff --git a/core/commit_stage.sv b/core/commit_stage.sv
index 40b7dc0b91..37b69af04f 100644
--- a/core/commit_stage.sv
+++ b/core/commit_stage.sv
@@ -172,7 +172,7 @@ module commit_stage
       // sfence.vma is idempotent so we can safely re-execute it after returning
       // from interrupt service routine
       // check if this instruction was a SFENCE_VMA
-      if (commit_instr_i[0].op == SFENCE_VMA) begin
+      if (CVA6Cfg.RVS && commit_instr_i[0].op == SFENCE_VMA) begin
         // no store pending so we can flush the TLBs and pipeline
         sfence_vma_o = no_st_pending_i;
         // wait for the store buffer to drain until flushing the pipeline
diff --git a/core/controller.sv b/core/controller.sv
index 9dbba77128..eec20cb092 100644
--- a/core/controller.sv
+++ b/core/controller.sv
@@ -125,7 +125,7 @@ module controller
     // ---------------------------------
     // SFENCE.VMA
     // ---------------------------------
-    if (sfence_vma_i) begin
+    if (CVA6Cfg.RVS && sfence_vma_i) begin
       set_pc_commit_o        = 1'b1;
       flush_if_o             = 1'b1;
       flush_unissued_instr_o = 1'b1;
diff --git a/core/ex_stage.sv b/core/ex_stage.sv
index d0d81a9ac8..92f871c8e2 100644
--- a/core/ex_stage.sv
+++ b/core/ex_stage.sv
@@ -386,28 +386,34 @@ module ex_stage
     assign x_valid_o     = '0;
   end
 
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (~rst_ni) begin
-      current_instruction_is_sfence_vma <= 1'b0;
-    end else begin
-      if (flush_i) begin
+  if(CVA6Cfg.RVS) begin
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (~rst_ni) begin
         current_instruction_is_sfence_vma <= 1'b0;
-      end else if ((fu_data_i.operation == SFENCE_VMA) && csr_valid_i) begin
-        current_instruction_is_sfence_vma <= 1'b1;
+      end else begin
+        if (flush_i) begin
+          current_instruction_is_sfence_vma <= 1'b0;
+        end else if ((fu_data_i.operation == SFENCE_VMA) && csr_valid_i) begin
+          current_instruction_is_sfence_vma <= 1'b1;
+        end
       end
     end
-  end
 
-  // This process stores the rs1 and rs2 parameters of a SFENCE_VMA instruction.
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (~rst_ni) begin
-      asid_to_be_flushed  <= '0;
-      vaddr_to_be_flushed <= '0;
-      // if the current instruction in EX_STAGE is a sfence.vma, in the next cycle no writes will happen
-    end else if ((~current_instruction_is_sfence_vma) && (~((fu_data_i.operation == SFENCE_VMA) && csr_valid_i))) begin
-      vaddr_to_be_flushed <= rs1_forwarding_i;
-      asid_to_be_flushed  <= rs2_forwarding_i[ASID_WIDTH-1:0];
+    // This process stores the rs1 and rs2 parameters of a SFENCE_VMA instruction.
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (~rst_ni) begin
+        asid_to_be_flushed  <= '0;
+        vaddr_to_be_flushed <= '0;
+        // if the current instruction in EX_STAGE is a sfence.vma, in the next cycle no writes will happen
+      end else if ((~current_instruction_is_sfence_vma) && (~((fu_data_i.operation == SFENCE_VMA) && csr_valid_i))) begin
+        vaddr_to_be_flushed <= rs1_forwarding_i;
+        asid_to_be_flushed  <= rs2_forwarding_i[ASID_WIDTH-1:0];
+      end
     end
+  end else begin
+     assign current_instruction_is_sfence_vma = 1'b0;
+     assign asid_to_be_flushed                = '0;
+     assign vaddr_to_be_flushed               = '0;
   end
 
 endmodule
diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv
index f5c19d619c..c28e826627 100644
--- a/core/issue_read_operands.sv
+++ b/core/issue_read_operands.sv
@@ -184,7 +184,7 @@ module issue_read_operands
       if (rs1_valid_i && (CVA6Cfg.FpPresent && is_rs1_fpr(
               issue_instr_i.op
           ) ? 1'b1 : ((rd_clobber_gpr_i[issue_instr_i.rs1] != CSR) ||
-                      (issue_instr_i.op == SFENCE_VMA)))) begin
+                      (CVA6Cfg.RVS && issue_instr_i.op == SFENCE_VMA)))) begin
         forward_rs1 = 1'b1;
       end else begin  // the operand is not available -> stall
         stall = 1'b1;
@@ -199,7 +199,7 @@ module issue_read_operands
       if (rs2_valid_i && (CVA6Cfg.FpPresent && is_rs2_fpr(
               issue_instr_i.op
           ) ? 1'b1 : ((rd_clobber_gpr_i[issue_instr_i.rs2] != CSR) ||
-                      (issue_instr_i.op == SFENCE_VMA)))) begin
+                      (CVA6Cfg.RVS && issue_instr_i.op == SFENCE_VMA)))) begin
         forward_rs2 = 1'b1;
       end else begin  // the operand is not available -> stall
         stall = 1'b1;