From 227a3f4ff919f89ad27202f2fa6c669bda5a4077 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= <61976467+ASintzoff@users.noreply.github.com> Date: Fri, 31 May 2024 12:48:12 +0200 Subject: [PATCH] doc cv32a65x: update xPELP fields in mstatus (#2177) --- docs/06_cv32a65x_riscv/priv-isa-cv32a65x.html | 25 +++++++++++-------- docs/06_cv32a65x_riscv/src/machine.adoc | 7 +++++- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/docs/06_cv32a65x_riscv/priv-isa-cv32a65x.html b/docs/06_cv32a65x_riscv/priv-isa-cv32a65x.html index f6f05a3336..f309ff2ad3 100644 --- a/docs/06_cv32a65x_riscv/priv-isa-cv32a65x.html +++ b/docs/06_cv32a65x_riscv/priv-isa-cv32a65x.html @@ -487,6 +487,7 @@

The RISC-V Instruction Set Manual for CV32A65X: Volume II: Privileged Archit
  • 3.1.6.4. Endianness Control in mstatus and mstatush Registers
  • 3.1.6.5. Virtualization Support in mstatus Register
  • 3.1.6.6. Extension Context Status in mstatus Register
    • +
  • 3.1.6.7. Previous Expected Landing Pad (ELP) State in mstatus Register
  • 3.1.7. Machine Trap-Vector Base-Address (mtvec) Register
    • @@ -500,9 +501,8 @@

    The RISC-V Instruction Set Manual for CV32A65X: Volume II: Privileged Archit
  • 3.1.15. Machine Cause (mcause) Register
  • 3.1.16. Machine Trap Value (mtval) Register
  • 3.1.17. Machine Configuration Pointer (mconfigptr) Register
    • -
  • 3.1.18. Machine Configuration Pointer Register (mconfigptr)
    • -
  • 3.1.19. Machine Environment Configuration (menvcfg) Register
    • -
  • 3.1.20. Machine Security Configuration (mseccfg) Register
    • +
  • 3.1.18. Machine Environment Configuration (menvcfg) Register
    • +
  • 3.1.19. Machine Security Configuration (mseccfg) Register
  • 3.2. Machine-Level Memory-Mapped Registers @@ -3412,6 +3412,13 @@
    3.1.6.6. Extension Contex illegal-instruction exception.

    +
    +
    3.1.6.7. Previous Expected Landing Pad (ELP) State in mstatus Register
    +
    +

    [CV32A65X] As the Zicfilp extension is not supported, +the SPELP and MPELP fields are read-only zero.

    +
    +

    3.1.7. Machine Trap-Vector Base-Address (mtvec) Register

    @@ -3941,14 +3948,12 @@

    3.1.15. Machine Cause (mcause) Register

    3.1.16. Machine Trap Value (mtval) Register

    - +
    +

    [CV32A65X] The mtval register is an MXLEN-bit read-only 0 register.

    -
    -

    3.1.17. Machine Configuration Pointer (mconfigptr) Register

    -
    -

    3.1.18. Machine Configuration Pointer Register (mconfigptr)

    +

    3.1.17. Machine Configuration Pointer (mconfigptr) Register

    The mconfigptr register is an MXLEN-bit read-only CSR that holds the physical address of a configuration data structure.

    @@ -3959,7 +3964,7 @@

    3.1.18. Machine Conf

    -

    3.1.19. Machine Environment Configuration (menvcfg) Register

    +

    3.1.18. Machine Environment Configuration (menvcfg) Register

    The menvcfg CSR is a 64-bit read/write register that controls certain characteristics of the execution environment for modes less @@ -3975,7 +3980,7 @@

    3.1.19. Machine Environment Configuration (menvcfg

    -

    3.1.20. Machine Security Configuration (mseccfg) Register

    +

    3.1.19. Machine Security Configuration (mseccfg) Register

    mseccfg is an optional 64-bit read/write register, that controls security features.

    diff --git a/docs/06_cv32a65x_riscv/src/machine.adoc b/docs/06_cv32a65x_riscv/src/machine.adoc index 1e0ec43940..2c89e9f27b 100644 --- a/docs/06_cv32a65x_riscv/src/machine.adoc +++ b/docs/06_cv32a65x_riscv/src/machine.adoc @@ -1398,9 +1398,9 @@ interrupts, unless the interrupt results in a user-level context swap. ==== endif::[] -ifeval::[{ohg-config} != CV32A65X] ===== Previous Expected Landing Pad (ELP) State in `mstatus` Register +ifeval::[{RVZicfilp} == true] The Zicfilp extension adds the `SPELP` and `MPELP` fields that hold the previous `ELP`, and are updated as specified in <>. The *__x__*`PELP` fields are encoded as follows: @@ -1409,6 +1409,11 @@ The Zicfilp extension adds the `SPELP` and `MPELP` fields that hold the previous * 1 - `LP_EXPECTED` - a landing pad instruction is expected. endif::[] +ifeval::[{RVZicfilp} == false] +[{ohg-config}] As the Zicfilp extension is not supported, +the `SPELP` and `MPELP` fields are read-only zero. +endif::[] + ==== Machine Trap-Vector Base-Address (`mtvec`) Register The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds