diff --git a/verif/core-v-verif b/verif/core-v-verif index 4a70806f3c..b92d30f4d3 160000 --- a/verif/core-v-verif +++ b/verif/core-v-verif @@ -1 +1 @@ -Subproject commit 4a70806f3cd8ddb5d693f4bfb99d16a4fbd2a15e +Subproject commit b92d30f4d3f4f5f50056e5267a03d02a66b7b6da diff --git a/verif/env/uvme/cov/uvme_axi_covg.sv b/verif/env/uvme/cov/uvme_axi_covg.sv index c9d00a6eb3..78b9d23968 100644 --- a/verif/env/uvme/cov/uvme_axi_covg.sv +++ b/verif/env/uvme/cov/uvme_axi_covg.sv @@ -22,25 +22,25 @@ covergroup cg_axi_w_channel(string name) option.per_instance = 1; option.name = name; - awready_to_valid: coverpoint (item.aw_delay) { + awready_to_valid: coverpoint (item.ready_delay_cycle_chan_ax) { bins dly[] = {[0:16]}; } - wready_to_valid: coverpoint (item.w_data_trs[0].w_delay) { + wready_to_valid: coverpoint (item.ready_delay_cycle_chan_w[0]) { bins dly[] = {[0:16]}; } - awsize: coverpoint (item.aw_size){ + awsize: coverpoint (item.m_size){ bins size[] = {[0:3]}; ignore_bins IGN_SIZE3 = {3} iff(uvme_cva6_pkg::XLEN == 32); } - awlock: coverpoint (item.aw_lock){ + awlock: coverpoint (item.m_lock){ bins lock[] = {[0:1]}; ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA); } - wstrb: coverpoint (item.w_data_trs[0].w_strb) { + wstrb: coverpoint (item.m_wstrb[0]) { bins strb1 = {1}; bins strb2 = {2}; bins strb3 = {3}; @@ -72,12 +72,12 @@ covergroup cg_axi_b_channel(string name) option.per_instance = 1; option.name = name; - bid: coverpoint (item.b_id){ + bid: coverpoint (item.m_id){ bins one = {[1:3]} iff(!hpdcache); illegal_bins ILLEGAL_BINS = {2} iff(!hpdcache); ignore_bins IGN_EXID = {3} iff(!RVA && !hpdcache); } - bresp: coverpoint (item.b_resp){ + bresp: coverpoint (item.m_resp[0]){ bins zero = {0}; bins one = {1}; bins two = {2}; @@ -93,23 +93,23 @@ covergroup cg_axi_ar_channel(string name) option.per_instance = 1; option.name = name; - arid: coverpoint (item.ar_id) { + arid: coverpoint (item.m_id) { bins ID[] = {[0:1]} iff(!hpdcache); } - arlen: coverpoint (item.ar_len) { + arlen: coverpoint (item.m_len) { bins LEN[] = {[0:1]}; } - arsize: coverpoint (item.ar_size) { - bins SIZE[] = {[0:3]} iff(item.ar_len == 0); + arsize: coverpoint (item.m_size) { + bins SIZE[] = {[0:3]} iff(item.m_len == 0); } - arready_to_valid: coverpoint (item.ar_delay) { + arready_to_valid: coverpoint (item.ready_delay_cycle_chan_ax) { bins dly[] = {[0:16]}; } - arlock: coverpoint (item.ar_lock){ + arlock: coverpoint (item.m_lock){ bins lock[] = {[0:1]}; ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA); } @@ -136,15 +136,15 @@ covergroup cg_axi_r_channel(string name) option.per_instance = 1; option.name = name; - rid: coverpoint (item.r_data_trs[index].r_id) { + rid: coverpoint (item.m_id) { bins ID[] = {[0:3]} iff(!hpdcache); illegal_bins ILLEGAL_BINS = {2} iff(!hpdcache); ignore_bins IGN_EXID = {3} iff(!RVA && !hpdcache); } - rlast: coverpoint (item.r_data_trs[index].r_last); + rlast: coverpoint (item.m_last[index]); - rresp: coverpoint (item.r_data_trs[index].r_resp){ + rresp: coverpoint (item.m_resp[index]){ bins zero = {0}; bins one = {1}; bins two = {2}; @@ -168,7 +168,10 @@ class uvme_axi_covg_c extends uvm_component; bit HPDCache; // TLM - uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_resp_fifo; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_aw_req_fifo; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_b_resp_fifo; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_ar_req_fifo; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_r_resp_fifo; // Covergroup instances cg_axi_w_channel w_axi_cg; @@ -229,7 +232,10 @@ function void uvme_axi_covg_c::build_phase(uvm_phase phase); RVA = cfg.ext_a_supported; HPDCache = cfg.HPDCache_supported; - uvme_axi_cov_resp_fifo = new("uvme_axi_cov_resp_fifo" , this); + uvme_axi_cov_b_resp_fifo = new("uvme_axi_cov_b_resp_fifo" , this); + uvme_axi_cov_r_resp_fifo = new("uvme_axi_cov_r_resp_fifo" , this); + uvme_axi_cov_ar_req_fifo = new("uvme_axi_cov_ar_req_fifo" , this); + uvme_axi_cov_aw_req_fifo = new("uvme_axi_cov_aw_req_fifo" , this); w_axi_cg = new("w_axi_cg"); b_axi_cg = new("b_axi_cg"); @@ -244,25 +250,40 @@ task uvme_axi_covg_c::run_phase(uvm_phase phase); `uvm_info(get_type_name(), $sformatf("cov_model_enabled = %d", cfg.cov_model_enabled), UVM_HIGH) `uvm_info(get_type_name(), $sformatf("ATOMIC ENABLE = %d", RVA), UVM_HIGH) forever begin - uvma_axi_transaction_c resp_item; - - uvme_axi_cov_resp_fifo.get(resp_item); - case (resp_item.access_type) - UVMA_AXI_ACCESS_WRITE : begin - - w_axi_cg.sample(resp_item, RVA); - b_axi_cg.sample(resp_item, RVA, HPDCache); - - end - UVMA_AXI_ACCESS_READ : begin - - ar_axi_cg.sample(resp_item, RVA, HPDCache); - for(int i = 0; i <= resp_item.ar_len; i++) begin - r_axi_cg.sample(resp_item, i, RVA, HPDCache); - end - + uvma_axi_transaction_c aw_item; + uvma_axi_transaction_c b_item; + uvma_axi_transaction_c ar_item; + uvma_axi_transaction_c r_item; + + fork + uvme_axi_cov_b_resp_fifo.get(b_item); + uvme_axi_cov_r_resp_fifo.get(r_item); + uvme_axi_cov_ar_req_fifo.get(ar_item); + uvme_axi_cov_aw_req_fifo.get(aw_item); + join_any + disable fork; + + if(aw_item != null) begin + `uvm_info(get_type_name(), $sformatf("WRITE REQ ITEM DETECTED"), UVM_LOW) + w_axi_cg.sample(aw_item, RVA); + end + + if(b_item != null) begin + `uvm_info(get_type_name(), $sformatf("WRITE RESP ITEM DETECTED"), UVM_LOW) + b_axi_cg.sample(b_item, RVA, HPDCache); + end + + if(ar_item != null) begin + `uvm_info(get_type_name(), $sformatf("READ ADDRESS ITEM DETECTED"), UVM_LOW) + ar_axi_cg.sample(ar_item, RVA, HPDCache); + end + + if(r_item != null) begin + `uvm_info(get_type_name(), $sformatf("READ DATA ITEM DETECTED"), UVM_LOW) + for(int i = 0; i <= r_item.m_len; i++) begin + r_axi_cg.sample(r_item, i, RVA, HPDCache); end - endcase + end end diff --git a/verif/env/uvme/cov/uvme_axi_ext_covg.sv b/verif/env/uvme/cov/uvme_axi_ext_covg.sv index 149d2a9520..10e725b1ad 100644 --- a/verif/env/uvme/cov/uvme_axi_ext_covg.sv +++ b/verif/env/uvme/cov/uvme_axi_ext_covg.sv @@ -17,7 +17,7 @@ */ covergroup cg_axi_aw_order(string name) - with function sample(uvma_axi_transaction_c item[], int t_b1_to_aw, int t_w1_to_aw, bit RVA); + with function sample(int t_b1_to_aw, int t_w1_to_aw); option.per_instance = 1; option.name = name; @@ -27,21 +27,10 @@ covergroup cg_axi_aw_order(string name) bins outstanding = {1}; } - awlock1: coverpoint (item[0].aw_lock){ - bins lock[] = {[0:1]}; - ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA); - } - - awlock2: coverpoint (item[1].aw_lock){ - bins lock[] = {[0:1]}; - ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA); - } - - aw_axi_cross: cross outstanding_resp, awlock1, awlock2; endgroup : cg_axi_aw_order covergroup cg_axi_ar_order(string name) - with function sample(uvma_axi_transaction_c item[], int t_r1_to_ar, int t_r1l_to_ar, int t_r1_to_r2, int t_r1l_to_r2l, bit RVA); + with function sample(uvma_axi_transaction_c item[], int t_r1_to_ar, int t_r1l_to_ar, int t_r1_to_r2, int t_r1l_to_r2l); option.per_instance = 1; option.name = name; @@ -57,57 +46,47 @@ covergroup cg_axi_ar_order(string name) } outoforder_resp_id0: coverpoint (t_r1_to_r2 < 0){ - bins normal = {0} iff(item[0].ar_id == 0); - bins outoforder = {1} iff(item[0].ar_id == 0); + bins normal = {0} iff(item[0].m_id == 0); + bins outoforder = {1} iff(item[0].m_id == 0); } outoforder_resp_id1: coverpoint (t_r1_to_r2 < 0){ - bins normal = {0} iff(item[0].ar_id == 1); - bins outoforder = {1} iff(item[0].ar_id == 1); + bins normal = {0} iff(item[0].m_id == 1); + bins outoforder = {1} iff(item[0].m_id == 1); } outoforder_last_resp_id0: coverpoint (t_r1l_to_r2l < 0){ - bins normal = {0} iff(item[0].ar_id == 0); - bins outoforder = {1} iff(item[0].ar_id == 0); + bins normal = {0} iff(item[0].m_id == 0); + bins outoforder = {1} iff(item[0].m_id == 0); } outoforder_last_resp_id1: coverpoint (t_r1l_to_r2l < 0){ - bins normal = {0} iff(item[0].ar_id == 1); - bins outoforder = {1} iff(item[0].ar_id == 1); + bins normal = {0} iff(item[0].m_id == 1); + bins outoforder = {1} iff(item[0].m_id == 1); } - arid1: coverpoint (item[0].ar_id){ + arid1: coverpoint (item[0].m_id){ bins id[] = {[0:1]}; } - arlen1: coverpoint (item[0].ar_len){ + arlen1: coverpoint (item[0].m_len){ bins len[] = {[0:1]}; } - arlock1: coverpoint (item[0].ar_lock){ - bins lock[] = {[0:1]}; - ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA); - } - - arid2: coverpoint (item[1].ar_id){ + arid2: coverpoint (item[1].m_id){ bins id[] = {[0:1]}; } - arlen2: coverpoint (item[1].ar_len){ + arlen2: coverpoint (item[1].m_len){ bins len[] = {[0:1]}; } - arlock2: coverpoint (item[1].ar_lock){ - bins lock[] = {[0:1]}; - ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA); - } - - ar_axi_outstanding_cross: cross outstanding_resp, outstanding_last_resp, arid1, arlen1, arlock1, arid2, arlen2, arlock2{ + ar_axi_outstanding_cross: cross outstanding_resp, outstanding_last_resp, arid1, arlen1, arid2, arlen2{ ignore_bins IGN_CROSS1 = binsof(outstanding_resp) intersect{1} && binsof(outstanding_last_resp) intersect{1}; } - aw_axi_outoforder_id0_cross: cross outoforder_resp_id0, outoforder_last_resp_id0, arlen1, arlock1, arlen2, arlock2{ + aw_axi_outoforder_id0_cross: cross outoforder_resp_id0, outoforder_last_resp_id0, arlen1, arlen2{ ignore_bins IGN_CROSS1 = binsof(outoforder_resp_id0) intersect{1} && binsof(outoforder_last_resp_id0) intersect{0} && binsof(arlen2) intersect{0}; @@ -116,7 +95,7 @@ covergroup cg_axi_ar_order(string name) binsof(arlen1) intersect{0}; } - aw_axi_outoforder_id1_cross: cross outoforder_resp_id1, outoforder_last_resp_id1, arlen1, arlock1, arlen2, arlock2{ + aw_axi_outoforder_id1_cross: cross outoforder_resp_id1, outoforder_last_resp_id1, arlen1, arlen2{ ignore_bins IGN_CROSS1 = binsof(outoforder_resp_id1) intersect{1} && binsof(outoforder_last_resp_id1) intersect{0} && binsof(arlen2) intersect{0}; @@ -131,11 +110,6 @@ endgroup : cg_axi_ar_order */ class uvme_axi_ext_covg_c extends uvm_component; - // Objects - uvme_cva6_cntxt_c cntxt; - uvme_cva6_cfg_c cfg; - bit RVA; - // Time between write transfer int t_b1_to_aw; // <0 (outstanding) int t_w1_to_aw; // <0 (outstanding) @@ -145,6 +119,9 @@ class uvme_axi_ext_covg_c extends uvm_component; int t_r1l_to_ar; // <0 (outstanding) int t_r1_to_r2; // <0 (r2 run before r1) int t_r1l_to_r2l; // <0 (last r2 run before last r1) + + int write_resp_status = 0; + int read_resp_status = 0; // Covergroup instances cg_axi_aw_order aw_axi_order_cg; @@ -154,10 +131,11 @@ class uvme_axi_ext_covg_c extends uvm_component; uvma_axi_transaction_c aw_trs_fifo[]; uvma_axi_transaction_c ar_trs_fifo[]; - int order_resp; - // TLM - uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_fifo; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_aw_req_fifo; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_b_resp_fifo; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_ar_req_fifo; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_r_resp_fifo; `uvm_component_utils_begin(uvme_axi_ext_covg_c) `uvm_component_utils_end @@ -168,8 +146,7 @@ class uvme_axi_ext_covg_c extends uvm_component; extern function new(string name="uvme_axi_ext_covg", uvm_component parent=null); /** - * 1. Ensures cfg & cntxt handles are not null. - * 2. Builds fifos. + * Builds fifos. */ extern virtual function void build_phase(uvm_phase phase); @@ -178,15 +155,35 @@ class uvme_axi_ext_covg_c extends uvm_component; */ extern virtual task run_phase(uvm_phase phase); + /** + * get transaction from monitor + */ + extern virtual task get_ar_item(); + + /** + * get transaction from monitor + */ + extern virtual task get_r_item(); + + /** + * get transaction from monitor + */ + extern virtual task get_aw_item(); + + /** + * get transaction from monitor + */ + extern virtual task get_b_item(); + /** * Forks all sampling loops */ - extern virtual function int aw_time_operations(); + extern virtual function void aw_time_operations(); /** * Forks all sampling loops */ - extern virtual function int ar_time_operations(); + extern virtual function void ar_time_operations(); endclass : uvme_axi_ext_covg_c @@ -201,22 +198,13 @@ function void uvme_axi_ext_covg_c::build_phase(uvm_phase phase); super.build_phase(phase); - void'(uvm_config_db#(uvme_cva6_cfg_c)::get(this, "", "cfg", cfg)); - if (cfg == null) begin - `uvm_fatal("cfg", "Context handle is null") - end - - void'(uvm_config_db#(uvme_cva6_cntxt_c)::get(this, "", "cntxt", cntxt)); - if (cntxt == null) begin - `uvm_fatal("CNTXT", "Context handle is null") - end - - RVA = cfg.ext_a_supported; - aw_axi_order_cg = new("aw_axi_order_cg"); ar_axi_order_cg = new("ar_axi_order_cg"); - uvme_axi_cov_fifo = new("uvme_axi_cov_fifo" , this); + uvme_axi_cov_b_resp_fifo = new("uvme_axi_cov_b_resp_fifo" , this); + uvme_axi_cov_r_resp_fifo = new("uvme_axi_cov_r_resp_fifo" , this); + uvme_axi_cov_ar_req_fifo = new("uvme_axi_cov_ar_req_fifo" , this); + uvme_axi_cov_aw_req_fifo = new("uvme_axi_cov_aw_req_fifo" , this); endfunction : build_phase @@ -224,82 +212,109 @@ task uvme_axi_ext_covg_c::run_phase(uvm_phase phase); super.run_phase(phase); forever begin - uvma_axi_transaction_c resp_item; - uvme_axi_cov_fifo.get(resp_item); - case (resp_item.access_type) + fork + get_aw_item(); + get_b_item(); + get_ar_item(); + get_r_item(); + join_any + + if(aw_trs_fifo.size() == 2 && write_resp_status == 2) begin + aw_time_operations(); + aw_axi_order_cg.sample(t_b1_to_aw, t_w1_to_aw); + aw_trs_fifo = new [aw_trs_fifo.size()-1] (aw_trs_fifo); + write_resp_status--; + end + + if(ar_trs_fifo.size() == 2 && read_resp_status == 2) begin + ar_time_operations(); + ar_axi_order_cg.sample(ar_trs_fifo, t_r1_to_ar, t_r1l_to_ar, t_r1_to_r2, t_r1l_to_r2l); + ar_trs_fifo = new [ar_trs_fifo.size()-1] (ar_trs_fifo); + read_resp_status--; + end + + disable fork; + end - UVMA_AXI_ACCESS_WRITE : begin +endtask : run_phase - aw_trs_fifo = new [aw_trs_fifo.size()+1] (aw_trs_fifo); - aw_trs_fifo[aw_trs_fifo.size()-1] = new resp_item; - if(aw_trs_fifo.size() == 2) begin - order_resp = aw_time_operations(); - aw_axi_order_cg.sample(aw_trs_fifo, t_b1_to_aw, t_w1_to_aw, RVA); - if(order_resp == 1) aw_trs_fifo[0] = new aw_trs_fifo[1]; - aw_trs_fifo = new [aw_trs_fifo.size()-1] (aw_trs_fifo); - end - end - UVMA_AXI_ACCESS_READ : begin +task uvme_axi_ext_covg_c::get_aw_item(); - ar_trs_fifo = new [ar_trs_fifo.size()+1] (ar_trs_fifo); - ar_trs_fifo[ar_trs_fifo.size()-1] = new resp_item; + uvma_axi_transaction_c aw_item; + uvme_axi_cov_aw_req_fifo.get(aw_item); + `uvm_info(get_type_name(), $sformatf("WRITE REQ ITEM DETECTED"), UVM_LOW) + aw_trs_fifo = new [aw_trs_fifo.size()+1] (aw_trs_fifo); + aw_trs_fifo[aw_trs_fifo.size()-1] = new aw_item; - if(ar_trs_fifo.size() == 2) begin +endtask : get_aw_item - order_resp = ar_time_operations(); - ar_axi_order_cg.sample(ar_trs_fifo, t_r1_to_ar, t_r1l_to_ar, t_r1_to_r2, t_r1l_to_r2l, RVA); - if(order_resp == 1) ar_trs_fifo[0] = new ar_trs_fifo[1]; - ar_trs_fifo = new [ar_trs_fifo.size()-1] (ar_trs_fifo); - end +task uvme_axi_ext_covg_c::get_ar_item(); - end - endcase - end + uvma_axi_transaction_c ar_item; + uvme_axi_cov_ar_req_fifo.get(ar_item); + `uvm_info(get_type_name(), $sformatf("READ REQ ITEM DETECTED"), UVM_LOW) + ar_trs_fifo = new [ar_trs_fifo.size()+1] (ar_trs_fifo); + ar_trs_fifo[ar_trs_fifo.size()-1] = new ar_item; -endtask : run_phase - -function int uvme_axi_ext_covg_c::ar_time_operations(); - int order_resp = 1; - uvma_axi_transaction_c axi_transaction; +endtask : get_ar_item - if(ar_trs_fifo[0].ar_start_time > ar_trs_fifo[1].ar_start_time) begin - axi_transaction = new ar_trs_fifo[0]; - ar_trs_fifo[0] = new ar_trs_fifo[1]; - ar_trs_fifo[1] = new axi_transaction; - order_resp = 0; +task uvme_axi_ext_covg_c::get_b_item(); + uvma_axi_transaction_c b_item; + uvme_axi_cov_b_resp_fifo.get(b_item); + `uvm_info(get_type_name(), $sformatf("WRITE RESP ITEM DETECTED"), UVM_LOW) + foreach(aw_trs_fifo[i]) begin + if (aw_trs_fifo[i].m_id == b_item.m_id) begin + aw_trs_fifo[i].m_resp = b_item.m_resp; + aw_trs_fifo[i].m_timestamp_b = b_item.m_timestamp_b; + aw_trs_fifo = new [aw_trs_fifo.size()+1] (aw_trs_fifo); + aw_trs_fifo[aw_trs_fifo.size()-1] = new aw_trs_fifo[i]; + write_resp_status++; + break; + end end - t_r1_to_ar = ar_trs_fifo[1].ar_start_time - ar_trs_fifo[0].r_data_trs[0].r_start_time; - t_r1l_to_ar = ar_trs_fifo[1].ar_start_time - ar_trs_fifo[0].r_data_trs[ar_trs_fifo[0].r_data_trs.size()-1].r_start_time; - t_r1_to_r2 = ar_trs_fifo[1].r_data_trs[0].r_start_time - ar_trs_fifo[0].r_data_trs[0].r_start_time; - t_r1l_to_r2l = ar_trs_fifo[1].r_data_trs[ar_trs_fifo[1].r_data_trs.size()-1].r_start_time - ar_trs_fifo[0].r_data_trs[ar_trs_fifo[0].r_data_trs.size()-1].r_start_time; +endtask : get_b_item - return order_resp; -endfunction : ar_time_operations +task uvme_axi_ext_covg_c::get_r_item(); -function int uvme_axi_ext_covg_c::aw_time_operations(); - int order_resp = 1; - uvma_axi_transaction_c axi_transaction; + uvma_axi_transaction_c r_item; + uvme_axi_cov_r_resp_fifo.get(r_item); + `uvm_info(get_type_name(), $sformatf("READ RESP ITEM DETECTED"), UVM_LOW) + foreach(ar_trs_fifo[i]) begin + if (ar_trs_fifo[i].m_id == r_item.m_id) begin + ar_trs_fifo[i].m_resp.push_back(r_item.m_resp[0]); + ar_trs_fifo[i].m_data.push_back(r_item.m_data[0]); + ar_trs_fifo[i].m_timestamp_x.push_back(r_item.m_timestamp_x[0]); + ar_trs_fifo = new [ar_trs_fifo.size()+1] (ar_trs_fifo); + ar_trs_fifo[ar_trs_fifo.size()-1] = new ar_trs_fifo[i]; + read_resp_status++; + break; + end + end - if(aw_trs_fifo[0].aw_start_time > aw_trs_fifo[1].aw_start_time) begin +endtask : get_r_item - axi_transaction = new aw_trs_fifo[0]; - aw_trs_fifo[0] = new aw_trs_fifo[1]; - aw_trs_fifo[1] = new axi_transaction; - order_resp = 0; - end +function void uvme_axi_ext_covg_c::ar_time_operations(); + + t_r1_to_ar = ar_trs_fifo[1].m_timestamp_ax - ar_trs_fifo[0].m_timestamp_x[0]; + t_r1l_to_ar = ar_trs_fifo[1].m_timestamp_ax - ar_trs_fifo[0].m_timestamp_x[ar_trs_fifo[0].m_timestamp_x.size()-1]; + t_r1_to_r2 = ar_trs_fifo[1].m_timestamp_x[0] - ar_trs_fifo[0].m_timestamp_x[0]; + t_r1l_to_r2l = ar_trs_fifo[1].m_timestamp_x[ar_trs_fifo[1].m_timestamp_x.size()-1] - ar_trs_fifo[0].m_timestamp_x[ar_trs_fifo[0].m_timestamp_x.size()-1]; + +endfunction : ar_time_operations + - t_b1_to_aw = aw_trs_fifo[1].aw_start_time - aw_trs_fifo[0].b_start_time; - t_w1_to_aw = aw_trs_fifo[1].aw_start_time - aw_trs_fifo[0].w_data_trs[0].w_start_time; +function void uvme_axi_ext_covg_c::aw_time_operations(); - return order_resp; + t_b1_to_aw = aw_trs_fifo[1].m_timestamp_ax - aw_trs_fifo[0].m_timestamp_b; + t_w1_to_aw = aw_trs_fifo[1].m_timestamp_ax - aw_trs_fifo[0].m_timestamp_x[0]; endfunction : aw_time_operations diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv index efde17646c..06d791a6d6 100644 --- a/verif/env/uvme/uvme_cva6_cfg.sv +++ b/verif/env/uvme/uvme_cva6_cfg.sv @@ -188,6 +188,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; isacov_cfg.reg_hazards_enabled == 1; rvfi_cfg.nret == CVA6Cfg.NrCommitPorts; unified_traps == 0; + axi_cfg.rand_channel_delay_enabled == 0; if (is_active == UVM_ACTIVE) { clknrst_cfg.is_active == UVM_ACTIVE; diff --git a/verif/env/uvme/uvme_cva6_env.sv b/verif/env/uvme/uvme_cva6_env.sv index efde8c8f02..b964be5306 100644 --- a/verif/env/uvme/uvme_cva6_env.sv +++ b/verif/env/uvme/uvme_cva6_env.sv @@ -395,8 +395,15 @@ function void uvme_cva6_env_c::connect_coverage_model(); rvfi_agent.rvfi_core_ap.connect(isacov_agent.monitor.rvfi_instr_imp); if(cfg.axi_cfg.cov_model_enabled) begin - axi_agent.vsequencer.synchronizer.uvma_sqr_trs_port.connect(cov_model.axi_covg.uvme_axi_cov_resp_fifo.analysis_export); - axi_agent.vsequencer.synchronizer.uvma_sqr_trs_port.connect(cov_model.axi_ext_covg.uvme_axi_cov_fifo.analysis_export); + axi_agent.monitor.m_axi_superset_write_rsp_packets_collected.connect(cov_model.axi_covg.uvme_axi_cov_b_resp_fifo.analysis_export); + axi_agent.monitor.m_axi_superset_read_rsp_packets_collected .connect(cov_model.axi_covg.uvme_axi_cov_r_resp_fifo.analysis_export); + axi_agent.monitor.m_axi_superset_read_req_packets_collected .connect(cov_model.axi_covg.uvme_axi_cov_ar_req_fifo.analysis_export); + axi_agent.monitor.m_axi_superset_write_req_packets_collected.connect(cov_model.axi_covg.uvme_axi_cov_aw_req_fifo.analysis_export); + + axi_agent.monitor.m_axi_superset_write_rsp_packets_collected.connect(cov_model.axi_ext_covg.uvme_axi_cov_b_resp_fifo.analysis_export); + axi_agent.monitor.m_axi_superset_read_rsp_packets_collected . connect(cov_model.axi_ext_covg.uvme_axi_cov_r_resp_fifo.analysis_export); + axi_agent.monitor.m_axi_superset_read_req_packets_collected .connect(cov_model.axi_ext_covg.uvme_axi_cov_ar_req_fifo.analysis_export); + axi_agent.monitor.m_axi_superset_write_req_packets_collected.connect(cov_model.axi_ext_covg.uvme_axi_cov_aw_req_fifo.analysis_export); end endfunction: connect_coverage_model diff --git a/verif/tb/uvmt/uvmt_cva6_pkg.sv b/verif/tb/uvmt/uvmt_cva6_pkg.sv index e0a19b659e..1b2e36eddc 100644 --- a/verif/tb/uvmt/uvmt_cva6_pkg.sv +++ b/verif/tb/uvmt/uvmt_cva6_pkg.sv @@ -29,6 +29,7 @@ `include "uvmt_axi_switch_intf.sv" `include "uvmt_default_inputs_intf.sv" +`include "uvma_axi_intf.sv" /** * Encapsulates all the types and test cases for the verification of an diff --git a/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv b/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv index 63dc3628ac..66c4bd8e16 100644 --- a/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv +++ b/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv @@ -241,26 +241,17 @@ function void uvmt_cva6_base_test_c::build_phase(uvm_phase phase); create_env (); create_components(); - `uvm_info("BASE TEST", $sformatf("AXI config version = %s", env_cfg.axi_cfg.version), UVM_LOW) - factory = uvm_factory::get(); - case (env_cfg.axi_cfg.version) - UVMA_AXI_VERSION_1P2 : begin - factory.set_type_override_by_name("uvma_axi_synchronizer_c", "uvma_axi_ext_synchronizer_c"); - `uvm_info("BASE TEST", $sformatf("AXI EXT SYNCHRONIZER"), UVM_LOW) - end - UVMA_AXI_VERSION_1P3 : begin - factory.set_type_override_by_name("uvma_axi_synchronizer_c", "uvma_axi_amo_synchronizer_c"); - `uvm_info("BASE TEST", $sformatf("AXI AMO SYNCHRONIZER"), UVM_LOW) - end - endcase + if(env_cfg.axi_cfg.version == 1) begin + factory.set_type_override_by_name("uvma_axi_synchronizer_c", "uvma_axi_amo_synchronizer_c"); + `uvm_info("BASE TEST", $sformatf("AXI AMO SYNCHRONIZER"), UVM_LOW) + end if(!env_cfg.axi_cfg.preload_mem) begin factory.set_type_override_by_name("uvma_axi_fw_preload_seq_c", "uvme_axi_fw_preload_seq_c"); end - endfunction : build_phase