From 1c3bde4908939ab5807b941d7a42803c164fc66a Mon Sep 17 00:00:00 2001 From: Florian Zaruba Date: Wed, 13 Sep 2023 08:22:24 +0200 Subject: [PATCH] Add `HaltAddress` and `ExceptionAddress` to all configs --- core/include/cv32a60x_config_pkg.sv | 4 +++- core/include/cv32a6_embedded_config_pkg.sv | 4 +++- core/include/cv32a6_ima_sv32_fpga_config_pkg.sv | 4 +++- core/include/cv32a6_imac_sv0_config_pkg.sv | 4 +++- core/include/cv32a6_imac_sv32_config_pkg.sv | 4 +++- core/include/cv32a6_imafc_sv32_config_pkg.sv | 4 +++- core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv | 4 +++- core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 4 +++- core/include/cv64a6_imafdcv_sv39_config_pkg.sv | 4 +++- 9 files changed, 27 insertions(+), 9 deletions(-) diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index eb1e9d8afd..bd478f60c4 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv32a6_embedded_config_pkg.sv b/core/include/cv32a6_embedded_config_pkg.sv index 0a845f2aa6..afd84b22bc 100644 --- a/core/include/cv32a6_embedded_config_pkg.sv +++ b/core/include/cv32a6_embedded_config_pkg.sv @@ -102,7 +102,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 451f774604..6fc140d91f 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 52f645e0f4..81d493047e 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 4c6c98926c..2b36b7572b 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index 71dab67b58..67d87c5e91 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index b24360fa9a..11d497f045 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 412fe2880b..9fd8921e69 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index a76a54cb3a..ee7da96375 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage