From 1b54f2e7cea1dee28deb368d7b26dc0d42129e42 Mon Sep 17 00:00:00 2001 From: AngelaGonzalezMarino Date: Mon, 19 Feb 2024 13:44:42 +0100 Subject: [PATCH] linting --- core/mmu_unify/cva6_mmu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/mmu_unify/cva6_mmu.sv b/core/mmu_unify/cva6_mmu.sv index bdf04490a0..55f369e384 100644 --- a/core/mmu_unify/cva6_mmu.sv +++ b/core/mmu_unify/cva6_mmu.sv @@ -397,9 +397,9 @@ module cva6_mmu riscv::INSTR_ACCESS_FAULT,{{riscv::XLEN - riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},1'b1 }; icache_areq_o.fetch_valid = 1'b0; - // --------- + // ---------// // ITLB Hit - // -------- + // --------// // if we hit the ITLB output the request signal immediately if (itlb_lu_hit) begin icache_areq_o.fetch_valid = icache_areq_i.fetch_req;