From 17ea49439f3db26f7e81228775d3c98ad7ebfba9 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski <107464696+zchamski@users.noreply.github.com> Date: Wed, 19 Jun 2024 12:08:15 +0200 Subject: [PATCH] [riscv-config] Update riscv-config tool, CV32A65X specs and the rendering of CSRs. (#2270) --- .../cv32a65x/csr/csr.rst | 244 +++++++++--------- .../scripts/libs/csr_updater.py | 7 +- .../scripts/libs/utils.py | 187 +++++++++----- .../updaters/cv32a65x/csr_updater.yaml | 17 -- .../cv32a65x/generated/isa_gen.yaml | 38 ++- .../riscv-config/cv32a65x/spec/isa_spec.yaml | 18 +- ...0004-fix-mstatush-and-nonascii-chars.patch | 25 ++ .../0005-add-csr-schema-for-mconfigptr.patch | 60 +++++ .../riscv_config/schemas/schema_isa.yaml | 55 +++- 9 files changed, 429 insertions(+), 222 deletions(-) create mode 100644 vendor/patches/riscv/riscv-config/0004-fix-mstatush-and-nonascii-chars.patch create mode 100644 vendor/patches/riscv/riscv-config/0005-add-csr-schema-for-mconfigptr.patch diff --git a/config/gen_from_riscv_config/cv32a65x/csr/csr.rst b/config/gen_from_riscv_config/cv32a65x/csr/csr.rst index 969e468aad..e376cfd97e 100644 --- a/config/gen_from_riscv_config/cv32a65x/csr/csr.rst +++ b/config/gen_from_riscv_config/cv32a65x/csr/csr.rst @@ -45,15 +45,15 @@ Register Summary +=============+=====================+=============+====================================================================================================+ | 0x300 | MSTATUS_ | MRW | The mstatus register keeps track of and controls the hart's current operating state. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x301 | MISA_ | MRO | misa is a read-write register reporting the ISA supported by the hart. | +| 0x301 | MISA_ | MRW | misa is a read-write register reporting the ISA supported by the hart. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ | 0x304 | MIE_ | MRW | The mie register is an MXLEN-bit read/write register containing interrupt enable bits. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ | 0x305 | MTVEC_ | MRW | MXLEN-bit read/write register that holds trap vector configuration. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x310 | MSTATUSH_ | MRO | The mstatush register keeps track of and controls the hart’s current operating state. | +| 0x310 | MSTATUSH_ | MRW | The mstatush register keeps track of and controls the hart’s current operating state. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x323-0x33f | MHPMEVENT[3-31]_ | MRO | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. | +| 0x323-0x33f | MHPMEVENT[3-31]_ | MRW | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ | 0x340 | MSCRATCH_ | MRW | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ @@ -61,9 +61,9 @@ Register Summary +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ | 0x342 | MCAUSE_ | MRW | The mcause register stores the information regarding the trap. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x343 | MTVAL_ | MRO | The mtval is a warl register that holds the address of the instruction which caused the exception. | +| 0x343 | MTVAL_ | MRW | The mtval is a warl register that holds the address of the instruction which caused the exception. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x344 | MIP_ | MRO | The mip register is an MXLEN-bit read/write register containing information on pending interrupts. | +| 0x344 | MIP_ | MRW | The mip register is an MXLEN-bit read/write register containing information on pending interrupts. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ | 0x3a0-0x3a3 | PMPCFG[0-3]_ | MRW | PMP configuration register | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ @@ -73,13 +73,13 @@ Register Summary +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ | 0xb02 | MINSTRET_ | MRW | Counts the number of instructions completed from an arbitrary point in time. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xb03-0xb1f | MHPMCOUNTER[3-31]_ | MRO | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. | +| 0xb03-0xb1f | MHPMCOUNTER[3-31]_ | MRW | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ | 0xb80 | MCYCLEH_ | MRW | upper 32 bits of mcycle | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ | 0xb82 | MINSTRETH_ | MRW | Upper 32 bits of minstret. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xb83-0xb9f | MHPMCOUNTER[3-31]H_ | MRO | The mhpmcounterh returns the upper half word in RV32I systems. | +| 0xb83-0xb9f | MHPMCOUNTER[3-31]H_ | MRW | The mhpmcounterh returns the upper half word in RV32I systems. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ | 0xf11 | MVENDORID_ | MRO | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. | +-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ @@ -106,49 +106,49 @@ MSTATUS +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ | Bits | Field Name | Reset Value | Type | Legal Values | Description | +=========+==============+===============+========+================+=================================================================================================================+ -| 0 | UIE | 0x0 | ROCST | | Stores the state of the user mode interrupts. | +| 0 | UIE | 0x0 | ROCST | 0x0 | Stores the state of the user mode interrupts. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 1 | SIE | 0x0 | ROCST | | Stores the state of the supervisor mode interrupts. | +| 1 | SIE | 0x0 | ROCST | 0x0 | Stores the state of the supervisor mode interrupts. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 2 | RESERVED_2 | 0x0 | WPRI | | Reserved | +| 2 | RESERVED_2 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 3 | MIE | 0x0 | WLRL | [0 , 1] | Stores the state of the machine mode interrupts. | +| 3 | MIE | 0x0 | WLRL | 0 - 1 | Stores the state of the machine mode interrupts. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 4 | UPIE | 0x0 | ROCST | | Stores the state of the user mode interrupts prior to the trap. | +| 4 | UPIE | 0x0 | ROCST | 0x0 | Stores the state of the user mode interrupts prior to the trap. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 5 | SPIE | 0x0 | ROCST | | Stores the state of the supervisor mode interrupts prior to the trap. | +| 5 | SPIE | 0x0 | ROCST | 0x0 | Stores the state of the supervisor mode interrupts prior to the trap. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 6 | UBE | 0x0 | ROCST | | control the endianness of memory accesses other than instruction fetches for user mode | +| 6 | UBE | 0x0 | ROCST | 0x0 | control the endianness of memory accesses other than instruction fetches for user mode | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 7 | MPIE | 0x0 | WLRL | [0 , 1] | Stores the state of the machine mode interrupts prior to the trap. | +| 7 | MPIE | 0x0 | WLRL | 0 - 1 | Stores the state of the machine mode interrupts prior to the trap. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 8 | SPP | 0x0 | ROCST | | Stores the previous priority mode for supervisor. | +| 8 | SPP | 0x0 | ROCST | 0x0 | Stores the previous priority mode for supervisor. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| [10:9] | RESERVED_9 | 0x0 | WPRI | | Reserved | +| [10:9] | RESERVED_9 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| [12:11] | MPP | 0x3 | WARL | [0x3] | Stores the previous priority mode for machine. | +| [12:11] | MPP | 0x3 | WARL | 0x3 | Stores the previous priority mode for machine. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| [14:13] | FS | 0x0 | ROCST | | Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers. | +| [14:13] | FS | 0x0 | ROCST | 0x0 | Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| [16:15] | XS | 0x0 | ROCST | | Encodes the status of additional user-mode extensions and associated state. | +| [16:15] | XS | 0x0 | ROCST | 0x0 | Encodes the status of additional user-mode extensions and associated state. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 17 | MPRV | 0x0 | ROCST | | Modifies the privilege level at which loads and stores execute in all privilege modes. | +| 17 | MPRV | 0x0 | ROCST | 0x0 | Modifies the privilege level at which loads and stores execute in all privilege modes. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 18 | SUM | 0x0 | ROCST | | Modifies the privilege with which S-mode loads and stores access virtual memory. | +| 18 | SUM | 0x0 | ROCST | 0x0 | Modifies the privilege with which S-mode loads and stores access virtual memory. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 19 | MXR | 0x0 | ROCST | | Modifies the privilege with which loads access virtual memory. | +| 19 | MXR | 0x0 | ROCST | 0x0 | Modifies the privilege with which loads access virtual memory. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 20 | TVM | 0x0 | ROCST | | Supports intercepting supervisor virtual-memory management operations. | +| 20 | TVM | 0x0 | ROCST | 0x0 | Supports intercepting supervisor virtual-memory management operations. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 21 | TW | 0x0 | ROCST | | Supports intercepting the WFI instruction. | +| 21 | TW | 0x0 | ROCST | 0x0 | Supports intercepting the WFI instruction. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 22 | TSR | 0x0 | ROCST | | Supports intercepting the supervisor exception return instruction. | +| 22 | TSR | 0x0 | ROCST | 0x0 | Supports intercepting the supervisor exception return instruction. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 23 | SPELP | 0x0 | ROCST | | Supervisor mode previous expected-landing-pad (ELP) state. | +| 23 | SPELP | 0x0 | ROCST | 0x0 | Supervisor mode previous expected-landing-pad (ELP) state. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| [30:24] | RESERVED_24 | 0x0 | WPRI | | Reserved | +| [30:24] | RESERVED_24 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 31 | SD | 0x0 | ROCST | | Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state. | +| 31 | SD | 0x0 | ROCST | 0x0 | Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ MISA @@ -156,7 +156,7 @@ MISA :Address: 0x301 :Reset Value: 0x40001106 -:Privilege: MRO +:Privilege: MRW :Description: misa is a read-write register reporting the ISA supported by the hart. @@ -165,9 +165,9 @@ MISA +=========+==============+===============+========+================+================================================================================================+ | [25:0] | EXTENSIONS | 0x1106 | ROCST | 0x1106 | Encodes the presence of the standard extensions, with a single bit per letter of the alphabet. | +---------+--------------+---------------+--------+----------------+------------------------------------------------------------------------------------------------+ -| [29:26] | RESERVED_26 | 0x0 | WPRI | | Reserved | +| [29:26] | RESERVED_26 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+------------------------------------------------------------------------------------------------+ -| [31:30] | MXL | 0x1 | ROCST | 0x1 | Encodes the native base integer ISA width. | +| [31:30] | MXL | 0x1 | WARL | 0x1 | Encodes the native base integer ISA width. | +---------+--------------+---------------+--------+----------------+------------------------------------------------------------------------------------------------+ MIE @@ -182,33 +182,33 @@ MIE +---------+--------------+---------------+--------+----------------+---------------------------------------+ | Bits | Field Name | Reset Value | Type | Legal Values | Description | +=========+==============+===============+========+================+=======================================+ -| 0 | USIE | 0x0 | ROCST | | User Software Interrupt enable. | +| 0 | USIE | 0x0 | ROCST | 0x0 | User Software Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 1 | SSIE | 0x0 | ROCST | | Supervisor Software Interrupt enable. | +| 1 | SSIE | 0x0 | ROCST | 0x0 | Supervisor Software Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 2 | VSSIE | 0x0 | ROCST | | VS-level Software Interrupt enable. | +| 2 | VSSIE | 0x0 | ROCST | 0x0 | VS-level Software Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 3 | MSIE | 0x0 | ROCST | | Machine Software Interrupt enable. | +| 3 | MSIE | 0x0 | ROCST | 0x0 | Machine Software Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 4 | UTIE | 0x0 | ROCST | | User Timer Interrupt enable. | +| 4 | UTIE | 0x0 | ROCST | 0x0 | User Timer Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 5 | STIE | 0x0 | ROCST | | Supervisor Timer Interrupt enable. | +| 5 | STIE | 0x0 | ROCST | 0x0 | Supervisor Timer Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 6 | VSTIE | 0x0 | ROCST | | VS-level Timer Interrupt enable. | +| 6 | VSTIE | 0x0 | ROCST | 0x0 | VS-level Timer Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 7 | MTIE | 0x0 | WLRL | [0 , 1] | Machine Timer Interrupt enable. | +| 7 | MTIE | 0x0 | WLRL | 0 - 1 | Machine Timer Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 8 | UEIE | 0x0 | ROCST | | User External Interrupt enable. | +| 8 | UEIE | 0x0 | ROCST | 0x0 | User External Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 9 | SEIE | 0x0 | ROCST | | Supervisor External Interrupt enable. | +| 9 | SEIE | 0x0 | ROCST | 0x0 | Supervisor External Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 10 | VSEIE | 0x0 | ROCST | | VS-level External Interrupt enable. | +| 10 | VSEIE | 0x0 | ROCST | 0x0 | VS-level External Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 11 | MEIE | 0x0 | WLRL | [0 , 1] | Machine External Interrupt enable. | +| 11 | MEIE | 0x0 | WLRL | 0 - 1 | Machine External Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 12 | SGEIE | 0x0 | ROCST | | HS-level External Interrupt enable. | +| 12 | SGEIE | 0x0 | ROCST | 0x0 | HS-level External Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| [31:13] | RESERVED_13 | 0x0 | WPRI | | Reserved | +| [31:13] | RESERVED_13 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+---------------------------------------+ MTVEC @@ -220,41 +220,41 @@ MTVEC :Description: MXLEN-bit read/write register that holds trap vector configuration. -+--------+--------------+---------------+--------+-----------------------------------+----------------------+ -| Bits | Field Name | Reset Value | Type | Legal Values | Description | -+========+==============+===============+========+===================================+======================+ -| [1:0] | MODE | 0x0 | WARL | [0x0] | Vector mode. | -+--------+--------------+---------------+--------+-----------------------------------+----------------------+ -| [31:2] | BASE | 0x20004000 | WARL | masked: & 0x3FFFFFFE | 0x00000000 | Vector base address. | -+--------+--------------+---------------+--------+-----------------------------------+----------------------+ ++--------+--------------+---------------+--------+-------------------------+----------------------+ +| Bits | Field Name | Reset Value | Type | Legal Values | Description | ++========+==============+===============+========+=========================+======================+ +| [1:0] | MODE | 0x0 | WARL | 0x0 | Vector mode. | ++--------+--------------+---------------+--------+-------------------------+----------------------+ +| [31:2] | BASE | 0x20004000 | WARL | 0x00000000 - 0x3FFFFFFF | Vector base address. | ++--------+--------------+---------------+--------+-------------------------+----------------------+ MSTATUSH -------- :Address: 0x310 :Reset Value: 0x00000000 -:Privilege: MRO +:Privilege: MRW :Description: The mstatush register keeps track of and controls the hart’s current operating state. +---------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------+ | Bits | Field Name | Reset Value | Type | Legal Values | Description | +=========+==============+===============+========+================+==============================================================================================+ -| [3:0] | RESERVED_0 | 0x0 | WPRI | | Reserved | +| [3:0] | RESERVED_0 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------+ -| 4 | SBE | 0x0 | ROCST | | control the endianness of memory accesses other than instruction fetches for supervisor mode | +| 4 | SBE | 0x0 | ROCST | 0x0 | control the endianness of memory accesses other than instruction fetches for supervisor mode | +---------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------+ -| 5 | MBE | 0x0 | ROCST | | control the endianness of memory accesses other than instruction fetches for machine mode | +| 5 | MBE | 0x0 | ROCST | 0x0 | control the endianness of memory accesses other than instruction fetches for machine mode | +---------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------+ -| 6 | GVA | 0x0 | ROCST | | Stores the state of the supervisor mode interrupts. | +| 6 | GVA | 0x0 | ROCST | 0x0 | Stores the state of the supervisor mode interrupts. | +---------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------+ -| 7 | MPV | 0x0 | ROCST | | Stores the state of the user mode interrupts. | +| 7 | MPV | 0x0 | ROCST | 0x0 | Stores the state of the user mode interrupts. | +---------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------+ -| 8 | RESERVED_8 | 0x0 | WPRI | | Reserved | +| 8 | RESERVED_8 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------+ -| 9 | MPELP | 0x0 | ROCST | | Machine mode previous expected-landing-pad (ELP) state. | +| 9 | MPELP | 0x0 | ROCST | 0x0 | Machine mode previous expected-landing-pad (ELP) state. | +---------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------+ -| [31:10] | RESERVED_10 | 0x0 | WPRI | | Reserved | +| [31:10] | RESERVED_10 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------+ MHPMEVENT[3-31] @@ -262,7 +262,7 @@ MHPMEVENT[3-31] :Address: 0x323-0x33f :Reset Value: 0x00000000 -:Privilege: MRO +:Privilege: MRW :Description: The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. @@ -281,11 +281,11 @@ MSCRATCH :Description: The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. -+--------+--------------+---------------+--------+---------------------------+----------------------------------------------------------------------------------------------+ -| Bits | Field Name | Reset Value | Type | Legal Values | Description | -+========+==============+===============+========+===========================+==============================================================================================+ -| [31:0] | MSCRATCH | 0x00000000 | WARL | [0x00000000 , 0xFFFFFFFF] | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. | -+--------+--------------+---------------+--------+---------------------------+----------------------------------------------------------------------------------------------+ ++--------+--------------+---------------+--------+-------------------------+----------------------------------------------------------------------------------------------+ +| Bits | Field Name | Reset Value | Type | Legal Values | Description | ++========+==============+===============+========+=========================+==============================================================================================+ +| [31:0] | MSCRATCH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. | ++--------+--------------+---------------+--------+-------------------------+----------------------------------------------------------------------------------------------+ MEPC ---- @@ -296,11 +296,11 @@ MEPC :Description: The mepc is a warl register that must be able to hold all valid physical and virtual addresses. -+--------+--------------+---------------+--------+---------------------------+-------------------------------------------------------------------------------------------------+ -| Bits | Field Name | Reset Value | Type | Legal Values | Description | -+========+==============+===============+========+===========================+=================================================================================================+ -| [31:0] | MEPC | 0x00000000 | WARL | [0x00000000 , 0xFFFFFFFF] | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. | -+--------+--------------+---------------+--------+---------------------------+-------------------------------------------------------------------------------------------------+ ++--------+--------------+---------------+--------+-------------------------+-------------------------------------------------------------------------------------------------+ +| Bits | Field Name | Reset Value | Type | Legal Values | Description | ++========+==============+===============+========+=========================+=================================================================================================+ +| [31:0] | MEPC | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. | ++--------+--------------+---------------+--------+-------------------------+-------------------------------------------------------------------------------------------------+ MCAUSE ------ @@ -314,9 +314,9 @@ MCAUSE +--------+----------------+---------------+--------+----------------+-----------------------------------------------------+ | Bits | Field Name | Reset Value | Type | Legal Values | Description | +========+================+===============+========+================+=====================================================+ -| [30:0] | EXCEPTION_CODE | 0x0 | WLRL | [0 , 15] | Encodes the exception code. | +| [30:0] | EXCEPTION_CODE | 0x0 | WLRL | 0 - 15 | Encodes the exception code. | +--------+----------------+---------------+--------+----------------+-----------------------------------------------------+ -| 31 | INTERRUPT | 0x0 | WLRL | [0x0 , 0x1] | Indicates whether the trap was due to an interrupt. | +| 31 | INTERRUPT | 0x0 | WLRL | 0x0 - 0x1 | Indicates whether the trap was due to an interrupt. | +--------+----------------+---------------+--------+----------------+-----------------------------------------------------+ MTVAL @@ -324,7 +324,7 @@ MTVAL :Address: 0x343 :Reset Value: 0x00000000 -:Privilege: MRO +:Privilege: MRW :Description: The mtval is a warl register that holds the address of the instruction which caused the exception. @@ -339,40 +339,40 @@ MIP :Address: 0x344 :Reset Value: 0x00000000 -:Privilege: MRO +:Privilege: MRW :Description: The mip register is an MXLEN-bit read/write register containing information on pending interrupts. +---------+--------------+---------------+--------+----------------+----------------------------------------+ | Bits | Field Name | Reset Value | Type | Legal Values | Description | +=========+==============+===============+========+================+========================================+ -| 0 | USIP | 0x0 | ROCST | | User Software Interrupt Pending. | +| 0 | USIP | 0x0 | ROCST | 0x0 | User Software Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 1 | SSIP | 0x0 | ROCST | | Supervisor Software Interrupt Pending. | +| 1 | SSIP | 0x0 | ROCST | 0x0 | Supervisor Software Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 2 | VSSIP | 0x0 | ROCST | | VS-level Software Interrupt Pending. | +| 2 | VSSIP | 0x0 | ROCST | 0x0 | VS-level Software Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 3 | MSIP | 0x0 | ROCST | | Machine Software Interrupt Pending. | +| 3 | MSIP | 0x0 | ROCST | 0x0 | Machine Software Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 4 | UTIP | 0x0 | ROCST | | User Timer Interrupt Pending. | +| 4 | UTIP | 0x0 | ROCST | 0x0 | User Timer Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 5 | STIP | 0x0 | ROCST | | Supervisor Timer Interrupt Pending. | +| 5 | STIP | 0x0 | ROCST | 0x0 | Supervisor Timer Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 6 | VSTIP | 0x0 | ROCST | | VS-level Timer Interrupt Pending. | +| 6 | VSTIP | 0x0 | ROCST | 0x0 | VS-level Timer Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 7 | MTIP | 0x0 | ROVAR | [0 , 1] | Machine Timer Interrupt Pending. | +| 7 | MTIP | 0x0 | ROVAR | 0 - 1 | Machine Timer Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 8 | UEIP | 0x0 | ROCST | | User External Interrupt Pending. | +| 8 | UEIP | 0x0 | ROCST | 0x0 | User External Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 9 | SEIP | 0x0 | ROCST | | Supervisor External Interrupt Pending. | +| 9 | SEIP | 0x0 | ROCST | 0x0 | Supervisor External Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 10 | VSEIP | 0x0 | ROCST | | VS-level External Interrupt Pending. | +| 10 | VSEIP | 0x0 | ROCST | 0x0 | VS-level External Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 11 | MEIP | 0x0 | ROVAR | [0 , 1] | Machine External Interrupt Pending. | +| 11 | MEIP | 0x0 | ROVAR | 0 - 1 | Machine External Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 12 | SGEIP | 0x0 | ROCST | | HS-level External Interrupt Pending. | +| 12 | SGEIP | 0x0 | ROCST | 0x0 | HS-level External Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| [31:13] | RESERVED_13 | 0x0 | WPRI | | Reserved | +| [31:13] | RESERVED_13 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+----------------------------------------+ PMPCFG[0-3] @@ -386,13 +386,13 @@ PMPCFG[0-3] +---------+-----------------+---------------+--------+----------------+------------------------+ | Bits | Field Name | Reset Value | Type | Legal Values | Description | +=========+=================+===============+========+================+========================+ -| [7:0] | PMP[I*4 + 0]CFG | 0x0 | WARL | [0x00:0xFF] | pmp configuration bits | +| [7:0] | PMP[I*4 + 0]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits | +---------+-----------------+---------------+--------+----------------+------------------------+ -| [15:8] | PMP[I*4 + 1]CFG | 0x0 | WARL | [0x00:0xFF] | pmp configuration bits | +| [15:8] | PMP[I*4 + 1]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits | +---------+-----------------+---------------+--------+----------------+------------------------+ -| [23:16] | PMP[I*4 + 2]CFG | 0x0 | WARL | [0x00:0xFF] | pmp configuration bits | +| [23:16] | PMP[I*4 + 2]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits | +---------+-----------------+---------------+--------+----------------+------------------------+ -| [31:24] | PMP[I*4 + 3]CFG | 0x0 | WARL | [0x00:0xFF] | pmp configuration bits | +| [31:24] | PMP[I*4 + 3]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits | +---------+-----------------+---------------+--------+----------------+------------------------+ PMPADDR[0-15] @@ -403,11 +403,11 @@ PMPADDR[0-15] :Privilege: MRW :Description: Physical memory protection address register -+--------+--------------+---------------+--------+---------------------------+---------------------------------------------+ -| Bits | Field Name | Reset Value | Type | Legal Values | Description | -+========+==============+===============+========+===========================+=============================================+ -| [31:0] | PMPADDR[I] | 0x00000000 | WARL | [0x00000000 , 0xFFFFFFFF] | Physical memory protection address register | -+--------+--------------+---------------+--------+---------------------------+---------------------------------------------+ ++--------+--------------+---------------+--------+-------------------------+---------------------------------------------+ +| Bits | Field Name | Reset Value | Type | Legal Values | Description | ++========+==============+===============+========+=========================+=============================================+ +| [31:0] | PMPADDR[I] | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Physical memory protection address register | ++--------+--------------+---------------+--------+-------------------------+---------------------------------------------+ MCYCLE ------ @@ -418,11 +418,11 @@ MCYCLE :Description: Counts the number of clock cycles executed from an arbitrary point in time. -+--------+--------------+---------------+--------+---------------------------+-----------------------------------------------------------------------------+ -| Bits | Field Name | Reset Value | Type | Legal Values | Description | -+========+==============+===============+========+===========================+=============================================================================+ -| [31:0] | MCYCLE | 0x00000000 | WARL | [0x00000000 , 0xFFFFFFFF] | Counts the number of clock cycles executed from an arbitrary point in time. | -+--------+--------------+---------------+--------+---------------------------+-----------------------------------------------------------------------------+ ++--------+--------------+---------------+--------+-------------------------+-----------------------------------------------------------------------------+ +| Bits | Field Name | Reset Value | Type | Legal Values | Description | ++========+==============+===============+========+=========================+=============================================================================+ +| [31:0] | MCYCLE | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Counts the number of clock cycles executed from an arbitrary point in time. | ++--------+--------------+---------------+--------+-------------------------+-----------------------------------------------------------------------------+ MINSTRET -------- @@ -433,18 +433,18 @@ MINSTRET :Description: Counts the number of instructions completed from an arbitrary point in time. -+--------+--------------+---------------+--------+---------------------------+------------------------------------------------------------------------------+ -| Bits | Field Name | Reset Value | Type | Legal Values | Description | -+========+==============+===============+========+===========================+==============================================================================+ -| [31:0] | MINSTRET | 0x00000000 | WARL | [0x00000000 , 0xFFFFFFFF] | Counts the number of instructions completed from an arbitrary point in time. | -+--------+--------------+---------------+--------+---------------------------+------------------------------------------------------------------------------+ ++--------+--------------+---------------+--------+-------------------------+------------------------------------------------------------------------------+ +| Bits | Field Name | Reset Value | Type | Legal Values | Description | ++========+==============+===============+========+=========================+==============================================================================+ +| [31:0] | MINSTRET | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Counts the number of instructions completed from an arbitrary point in time. | ++--------+--------------+---------------+--------+-------------------------+------------------------------------------------------------------------------+ MHPMCOUNTER[3-31] ----------------- :Address: 0xb03-0xb1f :Reset Value: 0x00000000 -:Privilege: MRO +:Privilege: MRW :Description: The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. @@ -462,11 +462,11 @@ MCYCLEH :Privilege: MRW :Description: upper 32 bits of mcycle -+--------+--------------+---------------+--------+---------------------------+-------------------------+ -| Bits | Field Name | Reset Value | Type | Legal Values | Description | -+========+==============+===============+========+===========================+=========================+ -| [31:0] | MCYCLEH | 0x00000000 | WARL | [0x00000000 , 0xFFFFFFFF] | upper 32 bits of mcycle | -+--------+--------------+---------------+--------+---------------------------+-------------------------+ ++--------+--------------+---------------+--------+-------------------------+-------------------------+ +| Bits | Field Name | Reset Value | Type | Legal Values | Description | ++========+==============+===============+========+=========================+=========================+ +| [31:0] | MCYCLEH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | upper 32 bits of mcycle | ++--------+--------------+---------------+--------+-------------------------+-------------------------+ MINSTRETH --------- @@ -476,18 +476,18 @@ MINSTRETH :Privilege: MRW :Description: Upper 32 bits of minstret. -+--------+--------------+---------------+--------+---------------------------+----------------------------+ -| Bits | Field Name | Reset Value | Type | Legal Values | Description | -+========+==============+===============+========+===========================+============================+ -| [31:0] | MINSTRETH | 0x00000000 | WARL | [0x00000000 , 0xFFFFFFFF] | Upper 32 bits of minstret. | -+--------+--------------+---------------+--------+---------------------------+----------------------------+ ++--------+--------------+---------------+--------+-------------------------+----------------------------+ +| Bits | Field Name | Reset Value | Type | Legal Values | Description | ++========+==============+===============+========+=========================+============================+ +| [31:0] | MINSTRETH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Upper 32 bits of minstret. | ++--------+--------------+---------------+--------+-------------------------+----------------------------+ MHPMCOUNTER[3-31]H ------------------ :Address: 0xb83-0xb9f :Reset Value: 0x00000000 -:Privilege: MRO +:Privilege: MRW :Description: The mhpmcounterh returns the upper half word in RV32I systems. diff --git a/config/gen_from_riscv_config/scripts/libs/csr_updater.py b/config/gen_from_riscv_config/scripts/libs/csr_updater.py index d77e2e17e4..08e05b0489 100644 --- a/config/gen_from_riscv_config/scripts/libs/csr_updater.py +++ b/config/gen_from_riscv_config/scripts/libs/csr_updater.py @@ -1,6 +1,7 @@ import re import yaml + def csr_recursive_update(original_dict, csr_update): """ Gets the data of the RISC-V Config Yaml file and @@ -14,7 +15,7 @@ def csr_recursive_update(original_dict, csr_update): if key in original_dict: if isinstance(value, dict) and isinstance(original_dict[key], dict): # If both are dicts, recurse - if key == 'type': + if key == "type": # Replace the entire type dictionary original_dict[key] = value else: @@ -22,6 +23,8 @@ def csr_recursive_update(original_dict, csr_update): else: # Replace the original value with the update value original_dict[key] = value + + def csr_formatter(srcfile, modifile): # Read original dictionary from YAML source file with open(srcfile, "r", encoding="utf-8") as file: @@ -31,7 +34,7 @@ def csr_formatter(srcfile, modifile): if modifile is not None: with open(modifile, "r", encoding="utf-8") as file: updated_values = yaml.safe_load(file) - + # Update original_dict with values from updated_values recursively csr_recursive_update(original_dict["hart0"], updated_values) diff --git a/config/gen_from_riscv_config/scripts/libs/utils.py b/config/gen_from_riscv_config/scripts/libs/utils.py index cf37818c8b..5bbe9b1a33 100644 --- a/config/gen_from_riscv_config/scripts/libs/utils.py +++ b/config/gen_from_riscv_config/scripts/libs/utils.py @@ -126,6 +126,42 @@ def __init__( self.orMask = orMask +# --------------------------------------------------------------# +class Render: + """Collection of general rendering methods which can be overridden if needed + for a specific output format.""" + + @staticmethod + def range(start, end): + """Return a string representing the range START..END, inclusive. + START and END are strings representing numerical values.""" + return f"{start} - {end}" + + @staticmethod + def value_set(values): + """Return a string representing the set of values in VALUES. + VALUES is a list of strings.""" + return ", ".join(values) + + @staticmethod + def bitmask(andMask, orMask): + """Return a string representing the masking pattern defined by ANDMASK and ORMASK. + ANDMASK and ORMASK are strings representing AND and OR mask values, respectively. + """ + return f"masked: & {andMask} | {orMask}" + + @staticmethod + def fieldtype(typ): + """Return a string representing the printable type of a register field.""" + upcased = typ.upper() + if upcased == "RO_CONSTANT": + return "ROCST" + elif upcased == "RO_VARIABLE": + return "ROVAR" + else: + return upcased + + # --------------------------------------------------------------# class ISAdocumentClass: """ISA document class""" @@ -214,20 +250,14 @@ def sort_address(self): return int(start, 16), int(end, 16) return int(reg.address, 16), int(reg.address, 16) - def get_access(self, reg): - register_access = "RO" - for field in reg.field: - if field.fieldaccess == "WARL" or field.fieldaccess == "WLRL": - register_access = "RW" - break - return register_access - - def change_access(self, field): - switcher = { - "RO_CONSTANT": "ROCST", - "RO_VARIABLE": "ROVAR", - } - return switcher.get(field.fieldaccess, field.fieldaccess) + def get_access_privilege(self, reg): + """Registers with address bits [11:10] == 2'b11 are Read-Only + as per privileged ISA spec.""" + # Handle register address ranges separated by dashes. + if (int(reg.address.split("-")[0], 0) & 0xC00) == 0xC00: + return "RO" + else: + return "RW" def returnAsString(self): registerlist = sorted(self.registerList, key=lambda reg: reg.address) @@ -235,7 +265,7 @@ def returnAsString(self): regNameList = [reg.name for reg in registerlist] regAddressList = [reg.address for reg in registerlist] regPrivModeList = [reg.access for reg in registerlist] - regAccessList = [self.get_access(reg) for reg in registerlist] + regPrivAccessList = [self.get_access_privilege(reg) for reg in registerlist] regDescrList = [reg.desc for reg in registerlist] regRV32List = [reg.RV32 for reg in registerlist] regRV64List = [reg.RV64 for reg in registerlist] @@ -299,7 +329,10 @@ def returnAsString(self): [ regAddressList[i], str(regNameList[i]).upper() + "_", - regPrivModeList[i] + regAccessList[i], + # RW or RO privileges are set in the official RISC-V specification + # and are encoded in bits [11:10] of the reg's address (2'b11 == "RO"). + # See Tables 4 through 8 in section 2.2 of the Priv spec v20240411. + regPrivModeList[i] + regPrivAccessList[i], str(regDescrList[i]), ] ) @@ -321,9 +354,8 @@ def returnAsString(self): "Reset Value", "0x" + f"{reg.resetValue[2:].zfill(int(reg.size/4))}", ) - # TODO FIXME: Add CSR privilege information to riscv-config schemas as implicit info. - # TODO FIXME: Handle the RO privilege of the Zicntr/Zihpm registers. - r.field("Privilege", reg.access + self.get_access(reg)) + # RO/RW privileges are encoded in register address. + r.field("Privilege", reg.access + self.get_access_privilege(reg)) r.field("Description", reg.desc) for field in reg.field: if field.bitWidth == 1: # only one bit -> no range needed @@ -334,9 +366,9 @@ def returnAsString(self): bits, field.name.upper(), field.fieldreset, - self.change_access(field), + field.fieldaccess, ( - f"masked: & {field.andMask} | {field.orMask}" + Render.bitmask(field.andMask, field.orMask) if field.andMask and field.orMask else field.bitlegal ), @@ -422,7 +454,7 @@ def returnAsString(self): class InstmdBlock(InstructionBlockClass): - """Generates a ISA Markdown file from a RISC Config Yaml register description""" + """Generates an ISA Markdown file from a RISC Config Yaml register description""" def __init__(self, name): super().__init__("isa") @@ -486,7 +518,7 @@ def returnAsString(self): for fieldIndex in list(range(len(reg.Name))): reg_table.append(reg.Name[fieldIndex].ljust(15)) reg.Format[fieldIndex] = ( - reg.Format[fieldIndex] + f"[{reg.Format[fieldIndex]}](#{reg.Format[fieldIndex]})" ) reg_table.append(reg.Format[fieldIndex]) reg.pseudocode[fieldIndex] = str( @@ -533,28 +565,15 @@ def parse_bits(self, bits): msb = lsb = int(bits.strip("[]").split(":")[0]) return msb, lsb - def get_access(self, reg): - register_access = "RO" - for field in reg.field: - if field.fieldaccess == "WARL": - register_access = "RW" - break - return register_access - - def change_access(self, field): - switcher = { - "RO_CONSTANT": "ROCST", - "RO_VARIABLE": "ROVAR", - } - return switcher.get(field.fieldaccess, field.fieldaccess) - def returnAsString(self): registerlist = sorted(self.registerList, key=lambda reg: reg.address) regNameList = [reg.name for reg in registerlist if reg.RV32 | reg.RV64] regAddressList = [reg.address for reg in registerlist if reg.RV32 | reg.RV64] regDescrList = [reg.desc for reg in registerlist if reg.RV32 | reg.RV64] regAccessList = [ - self.get_access(reg) for reg in registerlist if reg.RV32 | reg.RV64 + self.get_access_privilege(reg) + for reg in registerlist + if reg.RV32 | reg.RV64 ] regPrivModeList = [reg.access for reg in registerlist if reg.RV32 | reg.RV64] licence = [ @@ -600,7 +619,7 @@ def returnAsString(self): reg.address, reg.resetValue, reg.desc, - reg.access + self.get_access(reg), + reg.access + self.get_access_privilege(reg), ) reg_table = [] _line = [] @@ -614,7 +633,7 @@ def returnAsString(self): bits, field.name.upper(), field.fieldreset, - self.change_access(field), + field.fieldaccess, field.bitlegal, field.fieldDesc, ] @@ -643,7 +662,7 @@ def returnMdRegDesc(self, name, address, resetValue, desc, access): if resetValue: # display the resetvalue in hex notation in the full length of the register self.mdFile.new_line("**Reset Value** " + resetValue) - self.mdFile.new_line("**Privilege ** " + access) + self.mdFile.new_line("**Privilege** " + access) self.mdFile.new_line("**Description** " + desc) @@ -691,15 +710,20 @@ def returnRegister( ) fieldaccess = "" legal = registerElem.get("rv32", "")[item].get("type", None) - print(legal) + implemented = registerElem.get("rv32", "")[item].get( + "implemented", None + ) if legal is None: - bitlegal = "" + if not implemented: + bitlegal = "0x0" + else: + bitlegal = "" fieldaccess = "ROCST" fieldDesc = fieldDesc else: warl = re.findall(pattern_warl, str(legal.keys())) if warl: - fieldaccess = warl[0].upper() + fieldaccess = Render.fieldtype(warl[0]) legal_2 = ( registerElem.get("rv32", "")[item] .get("type", None) @@ -709,25 +733,52 @@ def returnRegister( bitlegal = "No Legal values" else: if isinstance(legal_2, dict): + # TODO: Need a pattern that supports arbitrary lists of values in matches(3). pattern = r"([\w\[\]:]+)\s*(\w+)\s*(\[\s*((?:0x)?[0-9A-Fa-f]+)\s*\D+\s*(?:((?:0x)?[0-9A-Fa-f]+))?\s*])" matches = re.search( pattern, str(legal_2["legal"][0]) ) if matches: expr_type = str(matches.group(2)) - legal_value = matches.group(3) - bitlegal = legal_value if expr_type == "bitmask": + # legal_value is left at default, cf. Render.bitmask(). andMask = str(matches.group(4)) orMask = str(matches.group(5)) + elif expr_type == "in": + if matches.group(3).find(",") >= 0: + # list ==> set of values + legal_value = Render.value_set( + matches.group(3) + .strip("[]") + .split(",") + ) + elif matches.group(3).find(":") >= 0: + # Range + (start, end) = ( + matches.group(3) + .strip("[]") + .split(":") + ) + legal_value = Render.range(start, end) + else: + # Singleton + legal_value = matches.group(3).strip( + "[]" + ) + else: + legal_value = matches.group(3) + bitlegal = legal_value elif isinstance(legal_2, list): pattern = r"\s*((?:0x)?[0-9A-Fa-f]+)\s*(.)\s*((?:0x)?[0-9A-Fa-f]+)\s*" matches = re.search(pattern, legal_2[0]) if matches: legal_value = ( - f"[{matches.group(1)} , {matches.group(3)}]" + Render.range( + matches.group(1), matches.group(3) + ) + if matches.group(2) == ":" + else Render.value_set(legal_2[0].split(",")) ) - bitlegal = legal_value else: legal_value = hex(legal_2) @@ -765,7 +816,7 @@ def returnRegister( legal = "" fieldaccess = "WPRI" bitWidth = int(item_[len(item_) - 1]) - int(item_[0]) + 1 - fieldDesc = "Reserved" + fieldDesc = "*Reserved*" bitlegal = legal fieldreset = hex( int(resetValue, 16) >> (bitlsb) & ((1 << ((bitWidth))) - 1) @@ -814,7 +865,7 @@ def returnRegister( else: warl = re.findall(pattern_warl, str(legal.keys())) if warl: - fieldaccess = warl[0].upper() + fieldaccess = Render.fieldtype(warl[0]) legal_2 = ( registerElem.get("rv32", "") .get("type", None) @@ -823,31 +874,47 @@ def returnRegister( if legal_2 is None: bitlegal = "No Legal values" else: - print(legal_2) if isinstance(legal_2, dict): pattern = r"([\w\[\]:]+\s*(\w+)\s*)(\[\s*((?:0x)?[0-9A-Fa-f]+)\s*\D+\s*(?:((?:0x)?[0-9A-Fa-f]+))?\s*])" matches = re.search(pattern, str(legal_2["legal"][0])) if matches: - legal_value = ( - f"[{matches.group(4)} , {matches.group(5)}]" + legal_value = Render.range( + matches.group(4), matches.group(5) ) - expr_type = str(matches.group(3)) + expr_type = str(matches.group(2)) mask = matches.group(5) bitmask = mask bitlegal = legal_value if expr_type == "bitmask": andMask = str(matches.group(4)) orMask = str(matches.group(5)) + elif expr_type == "in": + if matches.group(3).find(",") >= 0: + # list ==> set of values + legal_value = Render.value_set( + matches.group(3).strip("[]").split(",") + ) + elif matches.group(3).find(":") >= 0: + # Range + (start, end) = ( + matches.group(3).strip("[]").split(":") + ) + legal_value = Render.range(start, end) + else: + # Singleton + legal_value = matches.group(3).strip("[]") + else: + legal_value = matches.group(3) + bitlegal = legal_value elif isinstance(legal_2, list): - pattern = r"([0-9A-Fa-f]+).*([0-9A-Fa-f]+)" - + pattern = r"\s*((?:0x)?[0-9A-Fa-f]+)\s*(.)\s*((?:0x)?[0-9A-Fa-f]+)\s*" matches = re.search(pattern, legal_2[0]) if matches: legal_value = ( - f"[{matches.group(1)} , {matches.group(2)}]" + Render.range(matches.group(1), matches.group(3)) + if matches.group(2) == ":" + else Render.value_set(legal_2[0].split(",")) ) - mask = matches.group(2) - bitmask = mask bitlegal = legal_value else: bitmask = 0 diff --git a/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml b/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml index 60b3ef546b..fd9092025a 100644 --- a/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml +++ b/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml @@ -3,11 +3,6 @@ # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # Author: Abdessamii Oukalrazqou -misa: - rv32: - mxl: - type: - ro_constant: 0x1 mip: rv32: meip: @@ -18,19 +13,7 @@ mip: type: ro_variable: - 0:1 -mstatush: - address: 784 -mcountinhibit: - rv32 : - accessible : false - -# Range control -pmpaddr : - range: 16 - -pmpcfg : - range : 4 # Exclude mode exclude : key : priv_mode diff --git a/config/riscv-config/cv32a65x/generated/isa_gen.yaml b/config/riscv-config/cv32a65x/generated/isa_gen.yaml index 66f7fb3567..0b3ea13925 100644 --- a/config/riscv-config/cv32a65x/generated/isa_gen.yaml +++ b/config/riscv-config/cv32a65x/generated/isa_gen.yaml @@ -90,8 +90,9 @@ hart0: warl: dependency_fields: [] legal: - # All bits writable (first value of bitmask w/o cleared bits) - - base[29:0] bitmask [0x3FFFFFFF, 0x00000000] + # The 30 bits of 'base' are suffixed with 2'b00 + # ==> all values are legal, alignment 4 bytes is implied + - base[29:0] in [0x00000000:0x3FFFFFFF] wr_illegal: - Unchanged description: Vector base address. @@ -105,6 +106,7 @@ hart0: warl: dependency_fields: [] legal: + # Only Direct mode. - mode[1:0] in [0x0] wr_illegal: - Unchanged @@ -334,9 +336,9 @@ hart0: lsb: 23 rv64: accessible: false - description: The mstatus register keeps track of and controls the hart’s current + description: The mstatus register keeps track of and controls the hart's current operating state. - address: 768 + address: 0x300 priv_mode: M mip: reset-val: 0 @@ -711,6 +713,23 @@ hart0: hardware thread running the code. address: 3860 priv_mode: M + mconfigptr: + rv32: + accessible: true + type: + ro_constant: 0x0 + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + rv64: + accessible: false + reset-val: 0x0 + description: MXLEN-bit read-only register that holds the physical address + of a configuration data structure. + address: 0xF15 + priv_mode: M mscratch: rv32: accessible: true @@ -1692,14 +1711,7 @@ hart0: priv_mode: M mcountinhibit: rv32: - accessible: true - type: - ro_constant: 0x0 - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0x0 @@ -3515,7 +3527,7 @@ hart0: accessible: false description: The mstatush register keeps track of and controls the hart’s current operating state. - address: 768 + address: 0x310 priv_mode: M reset-val: 0 mideleg: diff --git a/config/riscv-config/cv32a65x/spec/isa_spec.yaml b/config/riscv-config/cv32a65x/spec/isa_spec.yaml index 1da7a13f70..9b25133aaa 100644 --- a/config/riscv-config/cv32a65x/spec/isa_spec.yaml +++ b/config/riscv-config/cv32a65x/spec/isa_spec.yaml @@ -56,8 +56,9 @@ hart0: &hart0 warl: dependency_fields: [] legal: - # All bits writable (first value of bitmask w/o cleared bits) - - base[29:0] bitmask [0x3FFFFFFF, 0x00000000] + # The 30 bits of 'base' are suffixed with 2'b00 + # ==> all values are legal, alignment 4 bytes is implied + - base[29:0] in [0x00000000:0x3FFFFFFF] wr_illegal: - Unchanged mode: @@ -66,6 +67,7 @@ hart0: &hart0 warl: dependency_fields: [] legal: + # Only Direct mode. - mode[1:0] in [0x0] wr_illegal: - Unchanged @@ -250,6 +252,14 @@ hart0: &hart0 rv64: accessible: false reset-val: 0x00 + mconfigptr: + rv32: + accessible: true + type: + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0x0 mscratch: rv32: accessible: true @@ -729,9 +739,7 @@ hart0: &hart0 reset-val: 0x0 mcountinhibit: rv32: - accessible: true - type: - ro_constant: 0x0 + accessible: false rv64: accessible: false reset-val: 0x0 diff --git a/vendor/patches/riscv/riscv-config/0004-fix-mstatush-and-nonascii-chars.patch b/vendor/patches/riscv/riscv-config/0004-fix-mstatush-and-nonascii-chars.patch new file mode 100644 index 0000000000..1bafa96ad4 --- /dev/null +++ b/vendor/patches/riscv/riscv-config/0004-fix-mstatush-and-nonascii-chars.patch @@ -0,0 +1,25 @@ +diff --git a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml +index a7536375f..27e88d16f 100644 +--- a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml ++++ b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml +@@ -523,9 +523,9 @@ hart_schema: + schema: + description: + type: string +- default: The mstatus register keeps track of and controls the hart’s current ++ default: The mstatus register keeps track of and controls the hart's current + operating state. +- address: {type: integer, default: 768, allowed: [768]} ++ address: {type: integer, default: 0x300, allowed: [0x300]} + priv_mode: {type: string, default: M, allowed: [M]} + reset-val: + type: integer +@@ -1506,7 +1506,7 @@ hart_schema: + type: string + default: The mstatush register keeps track of and controls the hart’s current + operating state. +- address: {type: integer, default: 768, allowed: [768]} ++ address: {type: integer, default: 0x310, allowed: [0x310]} + priv_mode: {type: string, default: M, allowed: [M]} + reset-val: + type: integer diff --git a/vendor/patches/riscv/riscv-config/0005-add-csr-schema-for-mconfigptr.patch b/vendor/patches/riscv/riscv-config/0005-add-csr-schema-for-mconfigptr.patch new file mode 100644 index 0000000000..16903a3ed6 --- /dev/null +++ b/vendor/patches/riscv/riscv-config/0005-add-csr-schema-for-mconfigptr.patch @@ -0,0 +1,60 @@ +diff --git a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml +index 27e88d16f..9c67bbcb7 100644 +--- a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml ++++ b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml +@@ -1819,6 +1819,55 @@ hart_schema: + default: true + check_with: rv64_check + default: {accessible: false} ++ mconfigptr: ++ type: dict ++ schema: ++ description: ++ type: string ++ default: MXLEN-bit read-only register that holds the physical address ++ of a configuration data structure. ++ address: {type: integer, default: 0xF15, allowed: [0xF15]} ++ priv_mode: {type: string, default: M, allowed: [M]} ++ reset-val: ++ type: integer ++ default: 0 ++ check_with: max_length ++ rv32: ++ type: dict ++ schema: ++ fields: {type: list, default: []} ++ shadow: {type: string, default: , nullable: True} ++ shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']} ++ msb: {type: integer, default: 31, allowed: [31]} ++ lsb: {type: integer, default: 0, allowed: [0]} ++ type: ++ type: dict ++ schema: {ro_constant: {type: integer, max: 0xFFFFFFFF}} ++ default: ++ ro_constant: 0 ++ accessible: ++ type: boolean ++ default: true ++ check_with: rv32_check ++ default: {accessible: false} ++ rv64: ++ type: dict ++ schema: ++ fields: {type: list, default: []} ++ shadow: {type: string, default: , nullable: True} ++ shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']} ++ msb: {type: integer, default: 63, allowed: [63]} ++ lsb: {type: integer, default: 0, allowed: [0]} ++ type: ++ type: dict ++ schema: {ro_constant: {type: integer, max: 0xFFFFFFFFFFFFFFFF}} ++ default: ++ ro_constant: 0 ++ accessible: ++ type: boolean ++ default: true ++ check_with: rv64_check ++ default: {accessible: false} + mtvec: + type: dict + schema: diff --git a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml index a7536375f5..9c67bbcb73 100644 --- a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml +++ b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml @@ -523,9 +523,9 @@ hart_schema: schema: description: type: string - default: The mstatus register keeps track of and controls the hart’s current + default: The mstatus register keeps track of and controls the hart's current operating state. - address: {type: integer, default: 768, allowed: [768]} + address: {type: integer, default: 0x300, allowed: [0x300]} priv_mode: {type: string, default: M, allowed: [M]} reset-val: type: integer @@ -1506,7 +1506,7 @@ hart_schema: type: string default: The mstatush register keeps track of and controls the hart’s current operating state. - address: {type: integer, default: 768, allowed: [768]} + address: {type: integer, default: 0x310, allowed: [0x310]} priv_mode: {type: string, default: M, allowed: [M]} reset-val: type: integer @@ -1819,6 +1819,55 @@ hart_schema: default: true check_with: rv64_check default: {accessible: false} + mconfigptr: + type: dict + schema: + description: + type: string + default: MXLEN-bit read-only register that holds the physical address + of a configuration data structure. + address: {type: integer, default: 0xF15, allowed: [0xF15]} + priv_mode: {type: string, default: M, allowed: [M]} + reset-val: + type: integer + default: 0 + check_with: max_length + rv32: + type: dict + schema: + fields: {type: list, default: []} + shadow: {type: string, default: , nullable: True} + shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']} + msb: {type: integer, default: 31, allowed: [31]} + lsb: {type: integer, default: 0, allowed: [0]} + type: + type: dict + schema: {ro_constant: {type: integer, max: 0xFFFFFFFF}} + default: + ro_constant: 0 + accessible: + type: boolean + default: true + check_with: rv32_check + default: {accessible: false} + rv64: + type: dict + schema: + fields: {type: list, default: []} + shadow: {type: string, default: , nullable: True} + shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']} + msb: {type: integer, default: 63, allowed: [63]} + lsb: {type: integer, default: 0, allowed: [0]} + type: + type: dict + schema: {ro_constant: {type: integer, max: 0xFFFFFFFFFFFFFFFF}} + default: + ro_constant: 0 + accessible: + type: boolean + default: true + check_with: rv64_check + default: {accessible: false} mtvec: type: dict schema: