From 14be0af7f017eef8fec615308c1d161584b45f07 Mon Sep 17 00:00:00 2001 From: Asmaa Kassimi <163407779+Asmaa-Kassimi@users.noreply.github.com> Date: Wed, 24 Jul 2024 11:09:25 +0100 Subject: [PATCH] solve simple lint errors (#2388) --- core/csr_regfile.sv | 30 ++++++++++++++++++++++-------- spyglass/reference_summary.rpt | 19 ++++++++++--------- 2 files changed, 32 insertions(+), 17 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 8dbfe038f3..252c771f55 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -2415,8 +2415,10 @@ module csr_regfile epc_o = mepc_q[CVA6Cfg.VLEN-1:0]; // we are returning from supervisor or virtual supervisor mode, so take the sepc register - if (CVA6Cfg.RVS && sret) begin - epc_o = (CVA6Cfg.RVH && v_q) ? vsepc_q[CVA6Cfg.VLEN-1:0] : sepc_q[CVA6Cfg.VLEN-1:0]; + if (CVA6Cfg.RVS) begin + if (sret) begin + epc_o = (CVA6Cfg.RVH && v_q) ? vsepc_q[CVA6Cfg.VLEN-1:0] : sepc_q[CVA6Cfg.VLEN-1:0]; + end end // we are returning from debug mode, to take the dpc register if (CVA6Cfg.DebugEn) begin @@ -2457,10 +2459,14 @@ module csr_regfile assign frm_o = fcsr_q.frm; assign fprec_o = fcsr_q.fprec; // MMU outputs - assign satp_ppn_o = satp_q.ppn; + assign satp_ppn_o = CVA6Cfg.RVS ? satp_q.ppn : '0; assign vsatp_ppn_o = CVA6Cfg.RVH ? vsatp_q.ppn : '0; assign hgatp_ppn_o = CVA6Cfg.RVH ? hgatp_q.ppn : '0; - assign asid_o = satp_q.asid[CVA6Cfg.ASID_WIDTH-1:0]; + if (CVA6Cfg.RVS) begin + assign asid_o = satp_q.asid[CVA6Cfg.ASID_WIDTH-1:0]; + end else begin + assign asid_o = '0; + end assign vs_asid_o = CVA6Cfg.RVH ? vsatp_q.asid[CVA6Cfg.ASID_WIDTH-1:0] : '0; assign vmid_o = CVA6Cfg.RVH ? hgatp_q.vmid[CVA6Cfg.VMID_WIDTH-1:0] : '0; assign sum_o = mstatus_q.sum; @@ -2483,12 +2489,20 @@ module csr_regfile : 1'b0; assign en_g_translation_o = 1'b0; end - assign mxr_o = mstatus_q.mxr; + assign mxr_o = mstatus_q.mxr; assign vmxr_o = CVA6Cfg.RVH ? vsstatus_q.mxr : '0; - assign tvm_o = (CVA6Cfg.RVH && v_q) ? hstatus_q.vtvm : mstatus_q.tvm; - assign tw_o = mstatus_q.tw; + if (CVA6Cfg.RVH) begin + assign tvm_o = (v_q) ? hstatus_q.vtvm : mstatus_q.tvm; + end else begin + assign tvm_o = mstatus_q.tvm; + end + assign tw_o = mstatus_q.tw; assign vtw_o = CVA6Cfg.RVH ? hstatus_q.vtw : '0; - assign tsr_o = (CVA6Cfg.RVH && v_q) ? hstatus_q.vtsr : mstatus_q.tsr; + if (CVA6Cfg.RVH) begin + assign tsr_o = (v_q) ? hstatus_q.vtsr : mstatus_q.tsr; + end else begin + assign tsr_o = mstatus_q.tsr; + end assign halt_csr_o = wfi_q; `ifdef PITON_ARIANE assign icache_en_o = icache_q[0]; diff --git a/spyglass/reference_summary.rpt b/spyglass/reference_summary.rpt index 1287fb11db..c383d57efa 100644 --- a/spyglass/reference_summary.rpt +++ b/spyglass/reference_summary.rpt @@ -4,7 +4,8 @@ # This file has been generated by SpyGlass: # Report Name : summary # Report Created by: akassimi -# Report Created on: Tue Jul 9 11:39:13 2024 +# Report Created on: Tue Jul 16 15:53:46 2024 +# Working Directory: /home/akassimi/rhel8/cva6_synthesis/cva6/spyglass # SpyGlass Version : SpyGlass_vS-2021.09-SP2-3 # Policy Name : SpyGlass(SpyGlass_vS-2021.09-SP2-03) # clock-reset(SpyGlass_vS-2021.09-SP2-03) @@ -19,9 +20,9 @@ # starc2005(SpyGlass_vS-2021.09-SP2-03) # txv(SpyGlass_vS-2021.09-SP2-03) # -# Total Number of Generated Messages : 1490 +# Total Number of Generated Messages : 1501 # Number of Waived Messages : 2 -# Number of Reported Messages : 1488 +# Number of Reported Messages : 1499 # Number of Overlimit Messages : 0 # # @@ -56,7 +57,7 @@ INFO HdlLibDuCheck_03 1 Reports that 'hdllibdu' is not required +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Severity Rule Name Count Short Help =============================================================================== -WARNING SYNTH_12605 4 Used Priority/Unique Type case/if +WARNING SYNTH_12605 5 Used Priority/Unique Type case/if statement but all the conditions are not covered WARNING SYNTH_12608 1 The logic of the always block @@ -86,9 +87,9 @@ INFO ElabSummary 1 Generates Elaborated design units Severity Rule Name Count Short Help =============================================================================== ERROR InferLatch 2 Latch inferred -ERROR UndrivenInTerm-ML 4 Undriven but loaded input terminal of +ERROR UndrivenInTerm-ML 3 Undriven but loaded input terminal of an instance detected -ERROR W123 18 A signal or variable has been read but +ERROR W123 11 A signal or variable has been read but is not set ERROR W416 1 Width of return type and return value of a function should be same (Verilog) @@ -114,17 +115,17 @@ WARNING STARC05-2.2.3.3 14 Do not assign over the same signal in circuits WARNING W224 1 Multi-bit expression found when one-bit expression expected -WARNING W240 297 An input has been declared but is not +WARNING W240 323 An input has been declared but is not read WARNING W263 4 A case expression width does not match case select expression width WARNING W287b 32 Output port of an instance is not connected -WARNING W415a 536 Signal may be multiply assigned (beside +WARNING W415a 526 Signal may be multiply assigned (beside initialization) in the same scope. WARNING W480 3 Loop index is not of type integer WARNING W486 2 Shift overflow - some bits may be lost -WARNING W528 481 A signal or variable is set but never +WARNING W528 483 A signal or variable is set but never read INFO W240 1 An input has been declared but is not read