From 13a4a092ab7c27d48581d5c471f81844d888b1c9 Mon Sep 17 00:00:00 2001
From: Guillaume Chauvon <94678394+Gchauvon@users.noreply.github.com>
Date: Thu, 25 Jan 2024 10:05:57 +0100
Subject: [PATCH] Check that User mode is enable to set MPP to U-mode (fix
 #1756) (#1781)

---
 core/csr_regfile.sv | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
index 88c16444a4..8198b5a259 100644
--- a/core/csr_regfile.sv
+++ b/core/csr_regfile.sv
@@ -1031,7 +1031,9 @@ module csr_regfile
 
     mstatus_d.sxl = riscv::XLEN_64;
     mstatus_d.uxl = riscv::XLEN_64;
-
+    if (!CVA6Cfg.RVU) begin
+      mstatus_d.mpp = riscv::PRIV_LVL_M;
+    end
     // mark the floating point extension register as dirty
     if (CVA6Cfg.FpPresent && (dirty_fp_state_csr || dirty_fp_state_i)) begin
       mstatus_d.fs = riscv::Dirty;
@@ -1248,14 +1250,17 @@ module csr_regfile
     // mode is changed to y; xPIE is set to 1; and xPP is set to U
     if (mret) begin
       // return from exception, IF doesn't care from where we are returning
-      eret_o         = 1'b1;
+      eret_o        = 1'b1;
       // return to the previous privilege level and restore all enable flags
       // get the previous machine interrupt enable flag
-      mstatus_d.mie  = mstatus_q.mpie;
+      mstatus_d.mie = mstatus_q.mpie;
       // restore the previous privilege level
-      priv_lvl_d     = mstatus_q.mpp;
-      // set mpp to user mode
-      mstatus_d.mpp  = riscv::PRIV_LVL_U;
+      priv_lvl_d    = mstatus_q.mpp;
+      mstatus_d.mpp = riscv::PRIV_LVL_M;
+      if (CVA6Cfg.RVU) begin
+        // set mpp to user mode
+        mstatus_d.mpp = riscv::PRIV_LVL_U;
+      end
       // set mpie to 1
       mstatus_d.mpie = 1'b1;
     end