From 0bd8b8693ac981a9b6a3f125bd52aea848a29be6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= <61976467+ASintzoff@users.noreply.github.com> Date: Fri, 5 Jul 2024 12:06:16 +0200 Subject: [PATCH] update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 (#2323) since last riscv-isa-manual update (CVA6 commit 105d3601b): - minor documentation changes - use of docs-resources submodule inside riscv-isa-manual - requires asciidoctor-lists --- docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html | 45 ++-- .../riscv/unpriv-isa-cv32a65x.html | 87 ++++--- .../riscv/priv-isa-cv64a6_mmu.html | 180 ++++++++------- .../riscv/unpriv-isa-cv64a6_mmu.html | 212 ++++++++++-------- docs/riscv-isa/build.mk | 8 +- docs/riscv-isa/riscv-isa-manual | 2 +- docs/riscv-isa/src/colophon.adoc | 5 +- docs/riscv-isa/src/config_define.adoc | 4 + docs/riscv-isa/src/machine.adoc | 177 ++++----------- docs/riscv-isa/src/priv-preface.adoc | 26 ++- docs/riscv-isa/src/riscv-privileged.adoc | 15 +- docs/riscv-isa/src/riscv-unprivileged.adoc | 17 +- docs/riscv-isa/src/supervisor.adoc | 127 +++++++++-- 13 files changed, 485 insertions(+), 420 deletions(-) diff --git a/docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html b/docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html index 4d068862cb..c9fac12d44 100644 --- a/docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html +++ b/docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html @@ -440,7 +440,7 @@
@@ -803,6 +809,10 @@

Preface

  • Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.

    • +
  • +

    Clarified that timer and count-overflow interrupts' arrival in +interrupt-pending registers is not immediate.

    +
    • @@ -4061,8 +4071,9 @@

    3.2.1. Machine Timer (Figure 20. Machine time compare register (memory-mapped control register).

    -

    Writes to mtime and mtimecmp are guaranteed to be reflected in MTIP -eventually, but not necessarily immediately.

    +

    If the result of the comparison between mtime and mtimecmp changes, it is +guaranteed to be reflected in MTIP eventually, but not necessarily +immediately.

    In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part @@ -4089,7 +4100,7 @@

    3.3. Machine-Mode Privileged Inst

    3.3.1. Environment Call and Breakpoint

    -Diagram +Diagram
    @@ -4120,7 +4131,7 @@

    3.3.2. Trap-Return Instructions

    -Diagram +Diagram
    @@ -4143,7 +4154,7 @@

    3.3.3. Wait for Interrupt

    -Diagram +Diagram
    @@ -4752,7 +4763,7 @@

    Bibliography

    diff --git a/docs/04_cv32a65x/riscv/unpriv-isa-cv32a65x.html b/docs/04_cv32a65x/riscv/unpriv-isa-cv32a65x.html index 442a23f8e9..811ff5e2c8 100644 --- a/docs/04_cv32a65x/riscv/unpriv-isa-cv32a65x.html +++ b/docs/04_cv32a65x/riscv/unpriv-isa-cv32a65x.html @@ -5,7 +5,7 @@ - + The RISC-V Instruction Set Manual for CV32A65X: Volume I - Unprivileged Architecture