diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
index e500ac834d..86b0342172 100644
--- a/core/csr_regfile.sv
+++ b/core/csr_regfile.sv
@@ -789,6 +789,7 @@ module csr_regfile
           mstatus_d.wpri1 = 1'b0;
           mstatus_d.wpri2 = 1'b0;
           mstatus_d.wpri0 = 1'b0;
+          mstatus_d.ube   = 1'b0;  // CVA6 is little-endian
           // this register has side-effects on other registers, flush the pipeline
           flush_o         = 1'b1;
         end