diff --git a/cv32e40p_fpu_manifest.flist b/cv32e40p_fpu_manifest.flist index aca8c41b2..28119c311 100644 --- a/cv32e40p_fpu_manifest.flist +++ b/cv32e40p_fpu_manifest.flist @@ -57,9 +57,9 @@ ${DESIGN_RTL_DIR}/cv32e40p_prefetch_controller.sv ${DESIGN_RTL_DIR}/cv32e40p_sleep_unit.sv ${DESIGN_RTL_DIR}/cv32e40p_core.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/src/cf_math_pkg.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/src/rr_arb_tree.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/src/lzc.sv +${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/common_cells/src/cf_math_pkg.sv +${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/common_cells/src/rr_arb_tree.sv +${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/common_cells/src/lzc.sv ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_pkg.sv ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v diff --git a/rtl/vendor/pulp_platform_fpnew.lock.hjson b/rtl/vendor/pulp_platform_fpnew.lock.hjson index e150bcb2f..5a9ffb052 100644 --- a/rtl/vendor/pulp_platform_fpnew.lock.hjson +++ b/rtl/vendor/pulp_platform_fpnew.lock.hjson @@ -8,7 +8,7 @@ { upstream: { - url: https://github.com/pulp-platform/fpnew.git - rev: 11659d7ff3580ac3226c6d56a90ef717cdc530e3 + url: https://github.com/davideschiavone/fpnew.git + rev: 3e5deb84382f93232cb0f0d79fed9208ee7dc7b6 } } diff --git a/rtl/vendor/pulp_platform_fpnew.vendor.hjson b/rtl/vendor/pulp_platform_fpnew.vendor.hjson index e76745d51..ac8300848 100644 --- a/rtl/vendor/pulp_platform_fpnew.vendor.hjson +++ b/rtl/vendor/pulp_platform_fpnew.vendor.hjson @@ -6,8 +6,8 @@ target_dir: "pulp_platform_fpnew", upstream: { - url: "https://github.com/pulp-platform/fpnew.git", - rev: "11659d7ff3580ac3226c6d56a90ef717cdc530e3", + url: "https://github.com/davideschiavone/fpnew.git", + rev: "3e5deb84382f93232cb0f0d79fed9208ee7dc7b6", }, exclude_from_upstream: [ @@ -16,7 +16,6 @@ "CITATION.cff", "README.md", "Bender.yml", - "src/common_cells", "src/fpu_div_sqrt_mvp", "tb", "ips_list.yml", diff --git a/rtl/vendor/pulp_platform_common_cells.lock.hjson b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells.lock.hjson similarity index 100% rename from rtl/vendor/pulp_platform_common_cells.lock.hjson rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells.lock.hjson diff --git a/rtl/vendor/pulp_platform_common_cells.vendor.hjson b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells.vendor.hjson similarity index 82% rename from rtl/vendor/pulp_platform_common_cells.vendor.hjson rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells.vendor.hjson index fa06ba7e7..84fe28b83 100644 --- a/rtl/vendor/pulp_platform_common_cells.vendor.hjson +++ b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells.vendor.hjson @@ -1,9 +1,9 @@ -// Copyright 2022 OpenHW Group +// Copyright 2023 OpenHW Group // Solderpad Hardware License, Version 2.1, see LICENSE.md for details. // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 { - name: "pulp_platform_common_cells", - target_dir: "pulp_platform_common_cells", + name: "common_cells", + target_dir: "common_cells", upstream: { url: "https://github.com/pulp-platform/common_cells.git", @@ -29,4 +29,4 @@ "test" ] -} +} \ No newline at end of file diff --git a/rtl/vendor/pulp_platform_common_cells/common_cells.core b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/common_cells.core similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/common_cells.core rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/common_cells.core diff --git a/rtl/vendor/pulp_platform_common_cells/include/common_cells/assertions.svh b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/include/common_cells/assertions.svh similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/include/common_cells/assertions.svh rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/include/common_cells/assertions.svh diff --git a/rtl/vendor/pulp_platform_common_cells/include/common_cells/registers.svh b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/include/common_cells/registers.svh similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/include/common_cells/registers.svh rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/include/common_cells/registers.svh diff --git a/rtl/vendor/pulp_platform_common_cells/src/addr_decode.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/addr_decode.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/addr_decode.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/addr_decode.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/binary_to_gray.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/binary_to_gray.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/binary_to_gray.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/binary_to_gray.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/cb_filter.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cb_filter.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/cb_filter.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cb_filter.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/cb_filter_pkg.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cb_filter_pkg.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/cb_filter_pkg.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cb_filter_pkg.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/cdc_2phase.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cdc_2phase.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/cdc_2phase.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cdc_2phase.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/cdc_fifo_2phase.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cdc_fifo_2phase.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/cdc_fifo_2phase.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cdc_fifo_2phase.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/cdc_fifo_gray.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cdc_fifo_gray.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/cdc_fifo_gray.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cdc_fifo_gray.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/cf_math_pkg.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cf_math_pkg.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/cf_math_pkg.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/cf_math_pkg.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/clk_div.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/clk_div.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/clk_div.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/clk_div.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/counter.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/counter.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/counter.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/counter.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/delta_counter.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/delta_counter.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/delta_counter.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/delta_counter.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/clock_divider.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/clock_divider.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/clock_divider.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/clock_divider.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/clock_divider_counter.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/clock_divider_counter.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/clock_divider_counter.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/clock_divider_counter.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/fifo_v1.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/fifo_v1.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/fifo_v1.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/fifo_v1.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/fifo_v2.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/fifo_v2.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/fifo_v2.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/fifo_v2.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/find_first_one.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/find_first_one.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/find_first_one.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/find_first_one.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/generic_LFSR_8bit.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/generic_LFSR_8bit.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/generic_LFSR_8bit.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/generic_LFSR_8bit.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/generic_fifo.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/generic_fifo.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/generic_fifo.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/generic_fifo.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/generic_fifo_adv.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/generic_fifo_adv.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/generic_fifo_adv.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/generic_fifo_adv.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/prioarbiter.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/prioarbiter.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/prioarbiter.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/prioarbiter.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/pulp_sync.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/pulp_sync.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/pulp_sync.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/pulp_sync.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/pulp_sync_wedge.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/pulp_sync_wedge.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/pulp_sync_wedge.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/pulp_sync_wedge.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/rrarbiter.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/rrarbiter.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/rrarbiter.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/rrarbiter.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/deprecated/sram.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/sram.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/deprecated/sram.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/deprecated/sram.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/ecc_decode.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/ecc_decode.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/ecc_decode.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/ecc_decode.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/ecc_encode.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/ecc_encode.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/ecc_encode.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/ecc_encode.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/ecc_pkg.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/ecc_pkg.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/ecc_pkg.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/ecc_pkg.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/edge_detect.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/edge_detect.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/edge_detect.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/edge_detect.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/edge_propagator.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/edge_propagator.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/edge_propagator.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/edge_propagator.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/edge_propagator_rx.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/edge_propagator_rx.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/edge_propagator_rx.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/edge_propagator_rx.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/edge_propagator_tx.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/edge_propagator_tx.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/edge_propagator_tx.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/edge_propagator_tx.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/exp_backoff.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/exp_backoff.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/exp_backoff.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/exp_backoff.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/fall_through_register.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/fall_through_register.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/fall_through_register.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/fall_through_register.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/fifo_v3.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/fifo_v3.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/fifo_v3.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/fifo_v3.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/gray_to_binary.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/gray_to_binary.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/gray_to_binary.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/gray_to_binary.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/id_queue.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/id_queue.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/id_queue.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/id_queue.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/isochronous_spill_register.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/isochronous_spill_register.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/isochronous_spill_register.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/isochronous_spill_register.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/lfsr.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/lfsr.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/lfsr.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/lfsr.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/lfsr_16bit.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/lfsr_16bit.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/lfsr_16bit.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/lfsr_16bit.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/lfsr_8bit.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/lfsr_8bit.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/lfsr_8bit.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/lfsr_8bit.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/lzc.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/lzc.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/lzc.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/lzc.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/max_counter.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/max_counter.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/max_counter.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/max_counter.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/mv_filter.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/mv_filter.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/mv_filter.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/mv_filter.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/onehot_to_bin.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/onehot_to_bin.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/onehot_to_bin.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/onehot_to_bin.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/plru_tree.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/plru_tree.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/plru_tree.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/plru_tree.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/popcount.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/popcount.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/popcount.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/popcount.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/rr_arb_tree.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/rr_arb_tree.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/rr_arb_tree.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/rr_arb_tree.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/rstgen.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/rstgen.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/rstgen.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/rstgen.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/rstgen_bypass.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/rstgen_bypass.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/rstgen_bypass.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/rstgen_bypass.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/serial_deglitch.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/serial_deglitch.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/serial_deglitch.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/serial_deglitch.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/shift_reg.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/shift_reg.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/shift_reg.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/shift_reg.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/spill_register.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/spill_register.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/spill_register.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/spill_register.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_arbiter.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_arbiter.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_arbiter.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_arbiter.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_arbiter_flushable.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_arbiter_flushable.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_arbiter_flushable.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_arbiter_flushable.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_delay.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_delay.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_delay.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_delay.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_demux.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_demux.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_demux.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_demux.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_fifo.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_fifo.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_fifo.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_fifo.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_filter.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_filter.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_filter.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_filter.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_fork.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_fork.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_fork.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_fork.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_fork_dynamic.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_fork_dynamic.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_fork_dynamic.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_fork_dynamic.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_intf.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_intf.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_intf.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_intf.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_join.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_join.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_join.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_join.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_mux.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_mux.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_mux.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_mux.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_omega_net.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_omega_net.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_omega_net.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_omega_net.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_register.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_register.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_register.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_register.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_to_mem.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_to_mem.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_to_mem.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_to_mem.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/stream_xbar.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_xbar.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/stream_xbar.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/stream_xbar.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/sub_per_hash.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/sub_per_hash.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/sub_per_hash.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/sub_per_hash.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/sync.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/sync.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/sync.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/sync.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/sync_wedge.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/sync_wedge.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/sync_wedge.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/sync_wedge.sv diff --git a/rtl/vendor/pulp_platform_common_cells/src/unread.sv b/rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/unread.sv similarity index 100% rename from rtl/vendor/pulp_platform_common_cells/src/unread.sv rename to rtl/vendor/pulp_platform_fpnew/vendor/common_cells/src/unread.sv diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.lock.hjson b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.lock.hjson deleted file mode 100644 index f9ec4482c..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.lock.hjson +++ /dev/null @@ -1,14 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// This file is generated by the util/vendor script. Please do not modify it -// manually. - -{ - upstream: - { - url: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git - rev: 86e1f558b3c95e91577c41b2fc452c86b04e85ac - } -} diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.vendor.hjson b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.vendor.hjson deleted file mode 100644 index 4e10e4e1a..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.vendor.hjson +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2022 OpenHW Group -// Solderpad Hardware License, Version 2.1, see LICENSE.md for details. -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -{ - name: "pulp_platform_fpu_div_sqrt_mvp", - target_dir: "pulp_platform_fpu_div_sqrt_mvp", - - upstream: { - url: "https://github.com/pulp-platform/fpu_div_sqrt_mvp.git", - rev: "86e1f558b3c95e91577c41b2fc452c86b04e85ac", - }, - - exclude_from_upstream: [ - "CHANGELOG.md", - "Bender.yml", - "src_files.yml", - "document" - ] -} diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/LICENSE b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/LICENSE deleted file mode 100644 index 18e4f6769..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/LICENSE +++ /dev/null @@ -1,176 +0,0 @@ -SOLDERPAD HARDWARE LICENSE version 0.51 - -This license is based closely on the Apache License Version 2.0, but is not -approved or endorsed by the Apache Foundation. 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You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 04/03/2018 // -// Design Name: FPU // -// Module Name: control_mvp.sv // -// Project Name: Private FPU // -// Language: SystemVerilog // -// // -// Description: the control logic of div and sqrt // -// // -// Revision Date: 12/04/2018 // -// Lei Li // -// To address some requirements by Stefan and add low power // -// control for special cases // -// Revision Date: 13/04/2018 // -// Lei Li // -// To fix some bug found in Control FSM // -// when Iteration_unit_num_S = 2'b10 // -// // -// // -// // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module control_mvp - - (//Input - input logic Clk_CI, - input logic Rst_RBI, - input logic Div_start_SI , - input logic Sqrt_start_SI, - input logic Start_SI, - input logic Kill_SI, - input logic Special_case_SBI, - input logic Special_case_dly_SBI, - input logic [C_PC-1:0] Precision_ctl_SI, - input logic [1:0] Format_sel_SI, - input logic [C_MANT_FP64:0] Numerator_DI, - input logic [C_EXP_FP64:0] Exp_num_DI, - input logic [C_MANT_FP64:0] Denominator_DI, - input logic [C_EXP_FP64:0] Exp_den_DI, - - - output logic Div_start_dly_SO , - output logic Sqrt_start_dly_SO, - output logic Div_enable_SO, - output logic Sqrt_enable_SO, - - - //To next stage - output logic Full_precision_SO, - output logic FP32_SO, - output logic FP64_SO, - output logic FP16_SO, - output logic FP16ALT_SO, - - output logic Ready_SO, - output logic Done_SO, - - output logic [C_MANT_FP64+4:0] Mant_result_prenorm_DO, - // output logic [3:0] Round_bit_DO, - output logic [C_EXP_FP64+1:0] Exp_result_prenorm_DO - ); - - logic [C_MANT_FP64+1+4:0] Partial_remainder_DN,Partial_remainder_DP; //58bits,r=q+2 - logic [C_MANT_FP64+4:0] Quotient_DP; //57bits - ///////////////////////////////////////////////////////////////////////////// - // Assign Inputs // - ///////////////////////////////////////////////////////////////////////////// - logic [C_MANT_FP64+1:0] Numerator_se_D; //sign extension and hidden bit - logic [C_MANT_FP64+1:0] Denominator_se_D; //signa extension and hidden bit - logic [C_MANT_FP64+1:0] Denominator_se_DB; //1's complement - - assign Numerator_se_D={1'b0,Numerator_DI}; - - assign Denominator_se_D={1'b0,Denominator_DI}; - - always_comb - begin - if(FP32_SO) - begin - Denominator_se_DB={~Denominator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP32], {(C_MANT_FP64-C_MANT_FP32){1'b0}} }; - end - else if(FP64_SO) begin - Denominator_se_DB=~Denominator_se_D; - end - else if(FP16_SO) begin - Denominator_se_DB={~Denominator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16], {(C_MANT_FP64-C_MANT_FP16){1'b0}} }; - end - else begin - Denominator_se_DB={~Denominator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16ALT], {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; - end - end - - - logic [C_MANT_FP64+1:0] Mant_D_sqrt_Norm; - - assign Mant_D_sqrt_Norm=Exp_num_DI[0]?{1'b0,Numerator_DI}:{Numerator_DI,1'b0}; //for sqrt - - ///////////////////////////////////////////////////////////////////////////// - // Format Selection // - ///////////////////////////////////////////////////////////////////////////// - logic [1:0] Format_sel_S; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Format_sel_S<='b0; - end - else if(Start_SI&&Ready_SO) - begin - Format_sel_S<=Format_sel_SI; - end - else - begin - Format_sel_S<=Format_sel_S; - end - end - - assign FP32_SO = (Format_sel_S==2'b00); - assign FP64_SO = (Format_sel_S==2'b01); - assign FP16_SO = (Format_sel_S==2'b10); - assign FP16ALT_SO = (Format_sel_S==2'b11); - - - - ///////////////////////////////////////////////////////////////////////////// - // Precision Control // - ///////////////////////////////////////////////////////////////////////////// - - logic [C_PC-1:0] Precision_ctl_S; - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Precision_ctl_S<='b0; - end - else if(Start_SI&&Ready_SO) - begin - Precision_ctl_S<=Precision_ctl_SI; - end - else - begin - Precision_ctl_S<=Precision_ctl_S; - end - end - assign Full_precision_SO = (Precision_ctl_S==6'h00); - - - - logic [5:0] State_ctl_S; - logic [5:0] State_Two_iteration_unit_S; - logic [5:0] State_Four_iteration_unit_S; - - assign State_Two_iteration_unit_S = Precision_ctl_S[C_PC-1:1]; //Two iteration units - assign State_Four_iteration_unit_S = Precision_ctl_S[C_PC-1:2]; //Four iteration units - always_comb - begin - case(Iteration_unit_num_S) -//////////////////////one iteration unit, start/////////////////////////////////////// - 2'b00: //one iteration unit - begin - case(Format_sel_S) - 2'b00: //FP32 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h1b; //24+4 more iterations for rounding bits - end - else - begin - State_ctl_S = Precision_ctl_S; - end - end - 2'b01: //FP64 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h38; //53+4 more iterations for rounding bits - end - else - begin - State_ctl_S = Precision_ctl_S; - end - end - 2'b10: //FP16 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h0e; //11+4 more iterations for rounding bits - end - else - begin - State_ctl_S = Precision_ctl_S; - end - end - 2'b11: //FP16ALT - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h0b; //8+4 more iterations for rounding bits - end - else - begin - State_ctl_S = Precision_ctl_S; - end - end - endcase - end -//////////////////////one iteration unit, end/////////////////////////////////////// - -//////////////////////two iteration units, start/////////////////////////////////////// - 2'b01: //two iteration units - begin - case(Format_sel_S) - 2'b00: //FP32 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h0d; //24+4 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Two_iteration_unit_S; - end - end - 2'b01: //FP64 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h1b; //53+3 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Two_iteration_unit_S; - end - end - 2'b10: //FP16 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h06; //11+3 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Two_iteration_unit_S; - end - end - 2'b11: //FP16ALT - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h05; //8+4 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Two_iteration_unit_S; - end - end - endcase - end -//////////////////////two iteration units, end/////////////////////////////////////// - -//////////////////////three iteration units, start/////////////////////////////////////// - 2'b10: //three iteration units - begin - case(Format_sel_S) - 2'b00: //FP32 - begin - case(Precision_ctl_S) - 6'h00: - begin - State_ctl_S = 6'h08; //24+3 more iterations for rounding bits - end - 6'h06,6'h07,6'h08: - begin - State_ctl_S = 6'h02; - end - 6'h09,6'h0a,6'h0b: - begin - State_ctl_S = 6'h03; - end - 6'h0c,6'h0d,6'h0e: - begin - State_ctl_S = 6'h04; - end - 6'h0f,6'h10,6'h11: - begin - State_ctl_S = 6'h05; - end - 6'h12,6'h13,6'h14: - begin - State_ctl_S = 6'h06; - end - 6'h15,6'h16,6'h17: - begin - State_ctl_S = 6'h07; - end - default: - begin - State_ctl_S = 6'h08; //24+3 more iterations for rounding bits - end - endcase - end - 2'b01: //FP64 - begin - case(Precision_ctl_S) - 6'h00: - begin - State_ctl_S = 6'h12; //53+4 more iterations for rounding bits - end - 6'h06,6'h07,6'h08: - begin - State_ctl_S = 6'h02; - end - 6'h09,6'h0a,6'h0b: - begin - State_ctl_S = 6'h03; - end - 6'h0c,6'h0d,6'h0e: - begin - State_ctl_S = 6'h04; - end - 6'h0f,6'h10,6'h11: - begin - State_ctl_S = 6'h05; - end - 6'h12,6'h13,6'h14: - begin - State_ctl_S = 6'h06; - end - 6'h15,6'h16,6'h17: - begin - State_ctl_S = 6'h07; - end - 6'h18,6'h19,6'h1a: - begin - State_ctl_S = 6'h08; - end - 6'h1b,6'h1c,6'h1d: - begin - State_ctl_S = 6'h09; - end - 6'h1e,6'h1f,6'h20: - begin - State_ctl_S = 6'h0a; - end - 6'h21,6'h22,6'h23: - begin - State_ctl_S = 6'h0b; - end - 6'h24,6'h25,6'h26: - begin - State_ctl_S = 6'h0c; - end - 6'h27,6'h28,6'h29: - begin - State_ctl_S = 6'h0d; - end - 6'h2a,6'h2b,6'h2c: - begin - State_ctl_S = 6'h0e; - end - 6'h2d,6'h2e,6'h2f: - begin - State_ctl_S = 6'h0f; - end - 6'h30,6'h31,6'h32: - begin - State_ctl_S = 6'h10; - end - 6'h33,6'h34,6'h35: - begin - State_ctl_S = 6'h11; - end - default: - begin - State_ctl_S = 6'h12; //53+4 more iterations for rounding bits - end - endcase - end - 2'b10: //FP16 - begin - case(Precision_ctl_S) - 6'h00: - begin - State_ctl_S = 6'h04; //12+3 more iterations for rounding bits - end - 6'h06,6'h07,6'h08: - begin - State_ctl_S = 6'h02; - end - 6'h09,6'h0a,6'h0b: - begin - State_ctl_S = 6'h03; - end - default: - begin - State_ctl_S = 6'h04; //12+3 more iterations for rounding bits - end - endcase - end - 2'b11: //FP16ALT - begin - case(Precision_ctl_S) - 6'h00: - begin - State_ctl_S = 6'h03; //8+4 more iterations for rounding bits - end - 6'h06,6'h07,6'h08: - begin - State_ctl_S = 6'h02; - end - default: - begin - State_ctl_S = 6'h03; //8+4 more iterations for rounding bits - end - endcase - end - endcase - end -//////////////////////three iteration units, end/////////////////////////////////////// - -//////////////////////four iteration units, start/////////////////////////////////////// - 2'b11: //four iteration units - begin - case(Format_sel_S) - 2'b00: //FP32 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h06; //24+4 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Four_iteration_unit_S; - end - end - 2'b01: //FP64 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h0d; //53+3 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Four_iteration_unit_S; - end - end - 2'b10: //FP16 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h03; //11+4 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Four_iteration_unit_S; - end - end - 2'b11: //FP16ALT - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h02; //8+4 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Four_iteration_unit_S; - end - end - endcase - end -//////////////////////four iteration units, end/////////////////////////////////////// - - endcase - end - - - ///////////////////////////////////////////////////////////////////////////// - // control logic // - ///////////////////////////////////////////////////////////////////////////// - - logic Div_start_dly_S; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) // generate Div_start_dly_S signal - begin - if(~Rst_RBI) - begin - Div_start_dly_S<=1'b0; - end - else if(Div_start_SI&&Ready_SO) - begin - Div_start_dly_S<=1'b1; - end - else - begin - Div_start_dly_S<=1'b0; - end - end - - assign Div_start_dly_SO=Div_start_dly_S; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) begin // generate Div_enable_SO signal - if(~Rst_RBI) - Div_enable_SO<=1'b0; - // Synchronous reset with Flush - else if (Kill_SI) - Div_enable_SO <= 1'b0; - else if(Div_start_SI&&Ready_SO) - Div_enable_SO<=1'b1; - else if(Done_SO) - Div_enable_SO<=1'b0; - else - Div_enable_SO<=Div_enable_SO; - end - - logic Sqrt_start_dly_S; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) // generate Sqrt_start_dly_SI signal - begin - if(~Rst_RBI) - begin - Sqrt_start_dly_S<=1'b0; - end - else if(Sqrt_start_SI&&Ready_SO) - begin - Sqrt_start_dly_S<=1'b1; - end - else - begin - Sqrt_start_dly_S<=1'b0; - end - end - assign Sqrt_start_dly_SO=Sqrt_start_dly_S; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) begin // generate Sqrt_enable_SO signal - if(~Rst_RBI) - Sqrt_enable_SO<=1'b0; - else if (Kill_SI) - Sqrt_enable_SO <= 1'b0; - else if(Sqrt_start_SI&&Ready_SO) - Sqrt_enable_SO<=1'b1; - else if(Done_SO) - Sqrt_enable_SO<=1'b0; - else - Sqrt_enable_SO<=Sqrt_enable_SO; - end - - logic [5:0] Crtl_cnt_S; - logic Start_dly_S; - - assign Start_dly_S=Div_start_dly_S |Sqrt_start_dly_S; - - logic Fsm_enable_S; - assign Fsm_enable_S=( (Start_dly_S | (| Crtl_cnt_S)) && (~Kill_SI) && Special_case_dly_SBI); - - logic Final_state_S; - assign Final_state_S= (Crtl_cnt_S==State_ctl_S); - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) //control_FSM - begin - if (~Rst_RBI) - begin - Crtl_cnt_S <= '0; - end - else if (Final_state_S | Kill_SI) - begin - Crtl_cnt_S <= '0; - end - else if(Fsm_enable_S) // one cycle Start_SI - begin - Crtl_cnt_S <= Crtl_cnt_S+1; - end - else - begin - Crtl_cnt_S <= '0; - end - end // always_ff - - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) //Generate Done_SO, they can share this Done_SO. - begin - if(~Rst_RBI) - begin - Done_SO<=1'b0; - end - else if(Start_SI&&Ready_SO) - begin - if(~Special_case_SBI) - begin - Done_SO<=1'b1; - end - else - begin - Done_SO<=1'b0; - end - end - else if(Final_state_S) - begin - Done_SO<=1'b1; - end - else - begin - Done_SO<=1'b0; - end - end - - - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) //Generate Ready_SO - begin - if(~Rst_RBI) - begin - Ready_SO<=1'b1; - end - - else if(Start_SI&&Ready_SO) - begin - if(~Special_case_SBI) - begin - Ready_SO<=1'b1; - end - else - begin - Ready_SO<=1'b0; - end - end - else if(Final_state_S | Kill_SI) - begin - Ready_SO<=1'b1; - end - else - begin - Ready_SO<=Ready_SO; - end - end - - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b00, start // - //////////////////////////////////////////////////////////////////////////// - - logic Qcnt_one_0; - logic Qcnt_one_1; - logic [1:0] Qcnt_one_2; - logic [2:0] Qcnt_one_3; - logic [3:0] Qcnt_one_4; - logic [4:0] Qcnt_one_5; - logic [5:0] Qcnt_one_6; - logic [6:0] Qcnt_one_7; - logic [7:0] Qcnt_one_8; - logic [8:0] Qcnt_one_9; - logic [9:0] Qcnt_one_10; - logic [10:0] Qcnt_one_11; - logic [11:0] Qcnt_one_12; - logic [12:0] Qcnt_one_13; - logic [13:0] Qcnt_one_14; - logic [14:0] Qcnt_one_15; - logic [15:0] Qcnt_one_16; - logic [16:0] Qcnt_one_17; - logic [17:0] Qcnt_one_18; - logic [18:0] Qcnt_one_19; - logic [19:0] Qcnt_one_20; - logic [20:0] Qcnt_one_21; - logic [21:0] Qcnt_one_22; - logic [22:0] Qcnt_one_23; - logic [23:0] Qcnt_one_24; - logic [24:0] Qcnt_one_25; - logic [25:0] Qcnt_one_26; - logic [26:0] Qcnt_one_27; - logic [27:0] Qcnt_one_28; - logic [28:0] Qcnt_one_29; - logic [29:0] Qcnt_one_30; - logic [30:0] Qcnt_one_31; - logic [31:0] Qcnt_one_32; - logic [32:0] Qcnt_one_33; - logic [33:0] Qcnt_one_34; - logic [34:0] Qcnt_one_35; - logic [35:0] Qcnt_one_36; - logic [36:0] Qcnt_one_37; - logic [37:0] Qcnt_one_38; - logic [38:0] Qcnt_one_39; - logic [39:0] Qcnt_one_40; - logic [40:0] Qcnt_one_41; - logic [41:0] Qcnt_one_42; - logic [42:0] Qcnt_one_43; - logic [43:0] Qcnt_one_44; - logic [44:0] Qcnt_one_45; - logic [45:0] Qcnt_one_46; - logic [46:0] Qcnt_one_47; - logic [47:0] Qcnt_one_48; - logic [48:0] Qcnt_one_49; - logic [49:0] Qcnt_one_50; - logic [50:0] Qcnt_one_51; - logic [51:0] Qcnt_one_52; - logic [52:0] Qcnt_one_53; - logic [53:0] Qcnt_one_54; - logic [54:0] Qcnt_one_55; - logic [55:0] Qcnt_one_56; - logic [56:0] Qcnt_one_57; - logic [57:0] Qcnt_one_58; - logic [58:0] Qcnt_one_59; - logic [59:0] Qcnt_one_60; - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b00, end // - //////////////////////////////////////////////////////////////////////////// - - - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b01, start // - //////////////////////////////////////////////////////////////////////////// - logic [1:0] Qcnt_two_0; - logic [2:0] Qcnt_two_1; - logic [4:0] Qcnt_two_2; - logic [6:0] Qcnt_two_3; - logic [8:0] Qcnt_two_4; - logic [10:0] Qcnt_two_5; - logic [12:0] Qcnt_two_6; - logic [14:0] Qcnt_two_7; - logic [16:0] Qcnt_two_8; - logic [18:0] Qcnt_two_9; - logic [20:0] Qcnt_two_10; - logic [22:0] Qcnt_two_11; - logic [24:0] Qcnt_two_12; - logic [26:0] Qcnt_two_13; - logic [28:0] Qcnt_two_14; - logic [30:0] Qcnt_two_15; - logic [32:0] Qcnt_two_16; - logic [34:0] Qcnt_two_17; - logic [36:0] Qcnt_two_18; - logic [38:0] Qcnt_two_19; - logic [40:0] Qcnt_two_20; - logic [42:0] Qcnt_two_21; - logic [44:0] Qcnt_two_22; - logic [46:0] Qcnt_two_23; - logic [48:0] Qcnt_two_24; - logic [50:0] Qcnt_two_25; - logic [52:0] Qcnt_two_26; - logic [54:0] Qcnt_two_27; - logic [56:0] Qcnt_two_28; - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b01, end // - //////////////////////////////////////////////////////////////////////////// - - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b10, start // - //////////////////////////////////////////////////////////////////////////// - logic [2:0] Qcnt_three_0; - logic [4:0] Qcnt_three_1; - logic [7:0] Qcnt_three_2; - logic [10:0] Qcnt_three_3; - logic [13:0] Qcnt_three_4; - logic [16:0] Qcnt_three_5; - logic [19:0] Qcnt_three_6; - logic [22:0] Qcnt_three_7; - logic [25:0] Qcnt_three_8; - logic [28:0] Qcnt_three_9; - logic [31:0] Qcnt_three_10; - logic [34:0] Qcnt_three_11; - logic [37:0] Qcnt_three_12; - logic [40:0] Qcnt_three_13; - logic [43:0] Qcnt_three_14; - logic [46:0] Qcnt_three_15; - logic [49:0] Qcnt_three_16; - logic [52:0] Qcnt_three_17; - logic [55:0] Qcnt_three_18; - logic [58:0] Qcnt_three_19; - logic [61:0] Qcnt_three_20; - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b10, end // - //////////////////////////////////////////////////////////////////////////// - - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b11, start // - //////////////////////////////////////////////////////////////////////////// - logic [3:0] Qcnt_four_0; - logic [6:0] Qcnt_four_1; - logic [10:0] Qcnt_four_2; - logic [14:0] Qcnt_four_3; - logic [18:0] Qcnt_four_4; - logic [22:0] Qcnt_four_5; - logic [26:0] Qcnt_four_6; - logic [30:0] Qcnt_four_7; - logic [34:0] Qcnt_four_8; - logic [38:0] Qcnt_four_9; - logic [42:0] Qcnt_four_10; - logic [46:0] Qcnt_four_11; - logic [50:0] Qcnt_four_12; - logic [54:0] Qcnt_four_13; - logic [58:0] Qcnt_four_14; - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b11, end // - //////////////////////////////////////////////////////////////////////////// - - - - logic [C_MANT_FP64+1+4:0] Sqrt_R0,Sqrt_Q0,Q_sqrt0,Q_sqrt_com_0; - logic [C_MANT_FP64+1+4:0] Sqrt_R1,Sqrt_Q1,Q_sqrt1,Q_sqrt_com_1; - logic [C_MANT_FP64+1+4:0] Sqrt_R2,Sqrt_Q2,Q_sqrt2,Q_sqrt_com_2; - logic [C_MANT_FP64+1+4:0] Sqrt_R3,Sqrt_Q3,Q_sqrt3,Q_sqrt_com_3,Sqrt_R4; //Sqrt_Q4; - - - logic [1:0] Sqrt_DI [3:0]; - logic [1:0] Sqrt_DO [3:0]; - logic Sqrt_carry_DO; - - - logic [C_MANT_FP64+1+4:0] Iteration_cell_a_D [3:0]; - logic [C_MANT_FP64+1+4:0] Iteration_cell_b_D [3:0]; - logic [C_MANT_FP64+1+4:0] Iteration_cell_a_BMASK_D [3:0]; - logic [C_MANT_FP64+1+4:0] Iteration_cell_b_BMASK_D [3:0]; - logic Iteration_cell_carry_D [3:0]; - logic [C_MANT_FP64+1+4:0] Iteration_cell_sum_D [3:0]; - logic [C_MANT_FP64+1+4:0] Iteration_cell_sum_AMASK_D [3:0]; - - - logic [3:0] Sqrt_quotinent_S; - - - always_comb - begin // - case (Format_sel_S) - 2'b00: - begin - Sqrt_quotinent_S = {(~Iteration_cell_sum_AMASK_D[0][C_MANT_FP32+5]),(~Iteration_cell_sum_AMASK_D[1][C_MANT_FP32+5]),(~Iteration_cell_sum_AMASK_D[2][C_MANT_FP32+5]),(~Iteration_cell_sum_AMASK_D[3][C_MANT_FP32+5])}; - Q_sqrt_com_0 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt0[C_MANT_FP32+5:0] }; - Q_sqrt_com_1 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt1[C_MANT_FP32+5:0] }; - Q_sqrt_com_2 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt2[C_MANT_FP32+5:0] }; - Q_sqrt_com_3 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt3[C_MANT_FP32+5:0] }; - end - 2'b01: - begin - Sqrt_quotinent_S = {Iteration_cell_carry_D[0],Iteration_cell_carry_D[1],Iteration_cell_carry_D[2],Iteration_cell_carry_D[3]}; - Q_sqrt_com_0=~Q_sqrt0; - Q_sqrt_com_1=~Q_sqrt1; - Q_sqrt_com_2=~Q_sqrt2; - Q_sqrt_com_3=~Q_sqrt3; - end - 2'b10: - begin - Sqrt_quotinent_S = {(~Iteration_cell_sum_AMASK_D[0][C_MANT_FP16+5]),(~Iteration_cell_sum_AMASK_D[1][C_MANT_FP16+5]),(~Iteration_cell_sum_AMASK_D[2][C_MANT_FP16+5]),(~Iteration_cell_sum_AMASK_D[3][C_MANT_FP16+5])}; - Q_sqrt_com_0 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt0[C_MANT_FP16+5:0] }; - Q_sqrt_com_1 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt1[C_MANT_FP16+5:0] }; - Q_sqrt_com_2 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt2[C_MANT_FP16+5:0] }; - Q_sqrt_com_3 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt3[C_MANT_FP16+5:0] }; - end - 2'b11: - begin - Sqrt_quotinent_S = {(~Iteration_cell_sum_AMASK_D[0][C_MANT_FP16ALT+5]),(~Iteration_cell_sum_AMASK_D[1][C_MANT_FP16ALT+5]),(~Iteration_cell_sum_AMASK_D[2][C_MANT_FP16ALT+5]),(~Iteration_cell_sum_AMASK_D[3][C_MANT_FP16ALT+5])}; - Q_sqrt_com_0 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt0[C_MANT_FP16ALT+5:0] }; - Q_sqrt_com_1 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt1[C_MANT_FP16ALT+5:0] }; - Q_sqrt_com_2 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt2[C_MANT_FP16ALT+5:0] }; - Q_sqrt_com_3 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt3[C_MANT_FP16ALT+5:0] }; - end - endcase - end - - - - assign Qcnt_one_0= {1'b0}; //qk for each feedback - assign Qcnt_one_1= {Quotient_DP[0]}; - assign Qcnt_one_2= {Quotient_DP[1:0]}; - assign Qcnt_one_3= {Quotient_DP[2:0]}; - assign Qcnt_one_4= {Quotient_DP[3:0]}; - assign Qcnt_one_5= {Quotient_DP[4:0]}; - assign Qcnt_one_6= {Quotient_DP[5:0]}; - assign Qcnt_one_7= {Quotient_DP[6:0]}; - assign Qcnt_one_8= {Quotient_DP[7:0]}; - assign Qcnt_one_9= {Quotient_DP[8:0]}; - assign Qcnt_one_10= {Quotient_DP[9:0]}; - assign Qcnt_one_11= {Quotient_DP[10:0]}; - assign Qcnt_one_12= {Quotient_DP[11:0]}; - assign Qcnt_one_13= {Quotient_DP[12:0]}; - assign Qcnt_one_14= {Quotient_DP[13:0]}; - assign Qcnt_one_15= {Quotient_DP[14:0]}; - assign Qcnt_one_16= {Quotient_DP[15:0]}; - assign Qcnt_one_17= {Quotient_DP[16:0]}; - assign Qcnt_one_18= {Quotient_DP[17:0]}; - assign Qcnt_one_19= {Quotient_DP[18:0]}; - assign Qcnt_one_20= {Quotient_DP[19:0]}; - assign Qcnt_one_21= {Quotient_DP[20:0]}; - assign Qcnt_one_22= {Quotient_DP[21:0]}; - assign Qcnt_one_23= {Quotient_DP[22:0]}; - assign Qcnt_one_24= {Quotient_DP[23:0]}; - assign Qcnt_one_25= {Quotient_DP[24:0]}; - assign Qcnt_one_26= {Quotient_DP[25:0]}; - assign Qcnt_one_27= {Quotient_DP[26:0]}; - assign Qcnt_one_28= {Quotient_DP[27:0]}; - assign Qcnt_one_29= {Quotient_DP[28:0]}; - assign Qcnt_one_30= {Quotient_DP[29:0]}; - assign Qcnt_one_31= {Quotient_DP[30:0]}; - assign Qcnt_one_32= {Quotient_DP[31:0]}; - assign Qcnt_one_33= {Quotient_DP[32:0]}; - assign Qcnt_one_34= {Quotient_DP[33:0]}; - assign Qcnt_one_35= {Quotient_DP[34:0]}; - assign Qcnt_one_36= {Quotient_DP[35:0]}; - assign Qcnt_one_37= {Quotient_DP[36:0]}; - assign Qcnt_one_38= {Quotient_DP[37:0]}; - assign Qcnt_one_39= {Quotient_DP[38:0]}; - assign Qcnt_one_40= {Quotient_DP[39:0]}; - assign Qcnt_one_41= {Quotient_DP[40:0]}; - assign Qcnt_one_42= {Quotient_DP[41:0]}; - assign Qcnt_one_43= {Quotient_DP[42:0]}; - assign Qcnt_one_44= {Quotient_DP[43:0]}; - assign Qcnt_one_45= {Quotient_DP[44:0]}; - assign Qcnt_one_46= {Quotient_DP[45:0]}; - assign Qcnt_one_47= {Quotient_DP[46:0]}; - assign Qcnt_one_48= {Quotient_DP[47:0]}; - assign Qcnt_one_49= {Quotient_DP[48:0]}; - assign Qcnt_one_50= {Quotient_DP[49:0]}; - assign Qcnt_one_51= {Quotient_DP[50:0]}; - assign Qcnt_one_52= {Quotient_DP[51:0]}; - assign Qcnt_one_53= {Quotient_DP[52:0]}; - assign Qcnt_one_54= {Quotient_DP[53:0]}; - assign Qcnt_one_55= {Quotient_DP[54:0]}; - assign Qcnt_one_56= {Quotient_DP[55:0]}; - assign Qcnt_one_57= {Quotient_DP[56:0]}; - - - assign Qcnt_two_0 = {1'b0, Sqrt_quotinent_S[3]}; //qk for each feedback - assign Qcnt_two_1 = {Quotient_DP[1:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_2 = {Quotient_DP[3:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_3 = {Quotient_DP[5:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_4 = {Quotient_DP[7:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_5 = {Quotient_DP[9:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_6 = {Quotient_DP[11:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_7 = {Quotient_DP[13:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_8 = {Quotient_DP[15:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_9 = {Quotient_DP[17:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_10 = {Quotient_DP[19:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_11 = {Quotient_DP[21:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_12 = {Quotient_DP[23:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_13 = {Quotient_DP[25:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_14 = {Quotient_DP[27:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_15 = {Quotient_DP[29:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_16 = {Quotient_DP[31:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_17 = {Quotient_DP[33:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_18 = {Quotient_DP[35:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_19 = {Quotient_DP[37:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_20 = {Quotient_DP[39:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_21 = {Quotient_DP[41:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_22 = {Quotient_DP[43:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_23 = {Quotient_DP[45:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_24 = {Quotient_DP[47:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_25 = {Quotient_DP[49:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_26 = {Quotient_DP[51:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_27 = {Quotient_DP[53:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_28 = {Quotient_DP[55:0],Sqrt_quotinent_S[3]}; - - - assign Qcnt_three_0 = {1'b0, Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; //qk for each feedback - assign Qcnt_three_1 = {Quotient_DP[2:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_2 = {Quotient_DP[5:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_3 = {Quotient_DP[8:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_4 = {Quotient_DP[11:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_5 = {Quotient_DP[14:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_6 = {Quotient_DP[17:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_7 = {Quotient_DP[20:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_8 = {Quotient_DP[23:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_9 = {Quotient_DP[26:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_10 = {Quotient_DP[29:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_11 = {Quotient_DP[32:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_12 = {Quotient_DP[35:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_13 = {Quotient_DP[38:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_14 = {Quotient_DP[41:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_15 = {Quotient_DP[44:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_16 = {Quotient_DP[47:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_17 = {Quotient_DP[50:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_18 = {Quotient_DP[53:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_19 = {Quotient_DP[56:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - - - assign Qcnt_four_0 = {1'b0, Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_1 = {Quotient_DP[3:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_2 = {Quotient_DP[7:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_3 = {Quotient_DP[11:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_4 = {Quotient_DP[15:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_5 = {Quotient_DP[19:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_6 = {Quotient_DP[23:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_7 = {Quotient_DP[27:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_8 = {Quotient_DP[31:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_9 = {Quotient_DP[35:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_10 = {Quotient_DP[39:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_11 = {Quotient_DP[43:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_12 = {Quotient_DP[47:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_13 = {Quotient_DP[51:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_14 = {Quotient_DP[55:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - - - - - always_comb begin // the intermediate operands for sqrt - - case(Iteration_unit_num_S) - 2'b00: - begin - - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b00, start // - ///////////////////////////////////////////////////////////////////////////// - - - - - case(Crtl_cnt_S) - - 6'b000000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_one_0}; - Sqrt_Q0=Q_sqrt_com_0; - end - 6'b000001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_one_1}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt0={{(C_MANT_FP64+4){1'b0}},Qcnt_one_2}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; - Q_sqrt0={{(C_MANT_FP64+3){1'b0}},Qcnt_one_3}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; - Q_sqrt0={{(C_MANT_FP64+2){1'b0}},Qcnt_one_4}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; - Q_sqrt0={{(C_MANT_FP64+1){1'b0}},Qcnt_one_5}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; - Q_sqrt0={{(C_MANT_FP64){1'b0}},Qcnt_one_6}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000111: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; - Q_sqrt0={{(C_MANT_FP64-1){1'b0}},Qcnt_one_7}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; - Q_sqrt0={{(C_MANT_FP64-2){1'b0}},Qcnt_one_8}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; - Q_sqrt0={{(C_MANT_FP64-3){1'b0}},Qcnt_one_9}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; - Q_sqrt0={{(C_MANT_FP64-4){1'b0}},Qcnt_one_10}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; - Q_sqrt0={{(C_MANT_FP64-5){1'b0}},Qcnt_one_11}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; - Q_sqrt0={{(C_MANT_FP64-6){1'b0}},Qcnt_one_12}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; - Q_sqrt0={{(C_MANT_FP64-7){1'b0}},Qcnt_one_13}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; - Q_sqrt0={{(C_MANT_FP64-8){1'b0}},Qcnt_one_14}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001111: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; - Q_sqrt0={{(C_MANT_FP64-9){1'b0}},Qcnt_one_15}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; - Q_sqrt0={{(C_MANT_FP64-10){1'b0}},Qcnt_one_16}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; - Q_sqrt0={{(C_MANT_FP64-11){1'b0}},Qcnt_one_17}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; - Q_sqrt0={{(C_MANT_FP64-12){1'b0}},Qcnt_one_18}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; - Q_sqrt0={{(C_MANT_FP64-13){1'b0}},Qcnt_one_19}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; - Q_sqrt0={{(C_MANT_FP64-14){1'b0}},Qcnt_one_20}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; - Q_sqrt0={{(C_MANT_FP64-15){1'b0}},Qcnt_one_21}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; - Q_sqrt0={{(C_MANT_FP64-16){1'b0}},Qcnt_one_22}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010111: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; - Q_sqrt0={{(C_MANT_FP64-17){1'b0}},Qcnt_one_23}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; - Q_sqrt0={{(C_MANT_FP64-18){1'b0}},Qcnt_one_24}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; - Q_sqrt0={{(C_MANT_FP64-19){1'b0}},Qcnt_one_25}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; - Q_sqrt0={{(C_MANT_FP64-20){1'b0}},Qcnt_one_26}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-21){1'b0}},Qcnt_one_27}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-22){1'b0}},Qcnt_one_28}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-23){1'b0}},Qcnt_one_29}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-24){1'b0}},Qcnt_one_30}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-25){1'b0}},Qcnt_one_31}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-26){1'b0}},Qcnt_one_32}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-27){1'b0}},Qcnt_one_33}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-28){1'b0}},Qcnt_one_34}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-29){1'b0}},Qcnt_one_35}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-30){1'b0}},Qcnt_one_36}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-31){1'b0}},Qcnt_one_37}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-32){1'b0}},Qcnt_one_38}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-33){1'b0}},Qcnt_one_39}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-34){1'b0}},Qcnt_one_40}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-35){1'b0}},Qcnt_one_41}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-36){1'b0}},Qcnt_one_42}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-37){1'b0}},Qcnt_one_43}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-38){1'b0}},Qcnt_one_44}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-39){1'b0}},Qcnt_one_45}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-40){1'b0}},Qcnt_one_46}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-41){1'b0}},Qcnt_one_47}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-42){1'b0}},Qcnt_one_48}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-43){1'b0}},Qcnt_one_49}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-44){1'b0}},Qcnt_one_50}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-45){1'b0}},Qcnt_one_51}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-46){1'b0}},Qcnt_one_52}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-47){1'b0}},Qcnt_one_53}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-48){1'b0}},Qcnt_one_54}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-49){1'b0}},Qcnt_one_55}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b111000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-50){1'b0}},Qcnt_one_56}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - - default: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0='0; - Sqrt_Q0='0; - end - endcase - end - - - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b00, end // - ///////////////////////////////////////////////////////////////////////////// - - - 2'b01: - begin - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b01, start // - ///////////////////////////////////////////////////////////////////////////// - case(Crtl_cnt_S) - - 6'b000000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_two_0[1]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_two_0[1:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt0={{(C_MANT_FP64+4){1'b0}},Qcnt_two_1[2:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; - Q_sqrt1={{(C_MANT_FP64+3){1'b0}},Qcnt_two_1[2:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; - Q_sqrt0={{(C_MANT_FP64+2){1'b0}},Qcnt_two_2[4:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; - Q_sqrt1={{(C_MANT_FP64+1){1'b0}},Qcnt_two_2[4:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; - Q_sqrt0={{(C_MANT_FP64){1'b0}},Qcnt_two_3[6:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; - Q_sqrt1={{(C_MANT_FP64-1){1'b0}},Qcnt_two_3[6:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; - Q_sqrt0={{(C_MANT_FP64-2){1'b0}},Qcnt_two_4[8:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; - Q_sqrt1={{(C_MANT_FP64-3){1'b0}},Qcnt_two_4[8:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; - Q_sqrt0={{(C_MANT_FP64-4){1'b0}},Qcnt_two_5[10:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; - Q_sqrt1={{(C_MANT_FP64-5){1'b0}},Qcnt_two_5[10:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; - Q_sqrt0={{(C_MANT_FP64-6){1'b0}},Qcnt_two_6[12:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; - Q_sqrt1={{(C_MANT_FP64-7){1'b0}},Qcnt_two_6[12:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000111: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; - Q_sqrt0={{(C_MANT_FP64-8){1'b0}},Qcnt_two_7[14:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; - Q_sqrt1={{(C_MANT_FP64-9){1'b0}},Qcnt_two_7[14:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; - Q_sqrt0={{(C_MANT_FP64-10){1'b0}},Qcnt_two_8[16:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; - Q_sqrt1={{(C_MANT_FP64-11){1'b0}},Qcnt_two_8[16:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; - Q_sqrt0={{(C_MANT_FP64-12){1'b0}},Qcnt_two_9[18:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; - Q_sqrt1={{(C_MANT_FP64-13){1'b0}},Qcnt_two_9[18:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; - Q_sqrt0={{(C_MANT_FP64-14){1'b0}},Qcnt_two_10[20:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; - Q_sqrt1={{(C_MANT_FP64-15){1'b0}},Qcnt_two_10[20:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; - Q_sqrt0={{(C_MANT_FP64-16){1'b0}},Qcnt_two_11[22:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; - Q_sqrt1={{(C_MANT_FP64-17){1'b0}},Qcnt_two_11[22:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; - Q_sqrt0={{(C_MANT_FP64-18){1'b0}},Qcnt_two_12[24:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; - Q_sqrt1={{(C_MANT_FP64-19){1'b0}},Qcnt_two_12[24:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; - Q_sqrt0={{(C_MANT_FP64-20){1'b0}},Qcnt_two_13[26:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-21){1'b0}},Qcnt_two_13[26:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-22){1'b0}},Qcnt_two_14[28:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-23){1'b0}},Qcnt_two_14[28:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-24){1'b0}},Qcnt_two_15[30:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-25){1'b0}},Qcnt_two_15[30:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-26){1'b0}},Qcnt_two_16[32:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-27){1'b0}},Qcnt_two_16[32:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-28){1'b0}},Qcnt_two_17[34:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-29){1'b0}},Qcnt_two_17[34:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-30){1'b0}},Qcnt_two_18[36:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-31){1'b0}},Qcnt_two_18[36:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-32){1'b0}},Qcnt_two_19[38:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-33){1'b0}},Qcnt_two_19[38:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-34){1'b0}},Qcnt_two_20[40:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-35){1'b0}},Qcnt_two_20[40:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-36){1'b0}},Qcnt_two_21[42:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-37){1'b0}},Qcnt_two_21[42:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-38){1'b0}},Qcnt_two_22[44:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-39){1'b0}},Qcnt_two_22[44:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-40){1'b0}},Qcnt_two_23[46:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-41){1'b0}},Qcnt_two_23[46:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b011000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-42){1'b0}},Qcnt_two_24[48:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-43){1'b0}},Qcnt_two_24[48:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b011001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-44){1'b0}},Qcnt_two_25[50:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-45){1'b0}},Qcnt_two_25[50:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b011010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-46){1'b0}},Qcnt_two_26[52:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-47){1'b0}},Qcnt_two_26[52:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b011011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-48){1'b0}},Qcnt_two_27[54:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-49){1'b0}},Qcnt_two_27[54:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b011100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-50){1'b0}},Qcnt_two_28[56:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-51){1'b0}},Qcnt_two_28[56:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - default: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_two_0[1]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_two_0[1:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - endcase - end - - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b01, end // - ///////////////////////////////////////////////////////////////////////////// - - - 2'b10: - begin - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b10, start // - ///////////////////////////////////////////////////////////////////////////// - - case(Crtl_cnt_S) - 6'b000000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_three_0[2]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_three_0[2:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_three_0[2:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; - Q_sqrt0={{(C_MANT_FP64+2){1'b0}},Qcnt_three_1[4:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; - Q_sqrt1={{(C_MANT_FP64+1){1'b0}},Qcnt_three_1[4:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; - Q_sqrt2={{(C_MANT_FP64){1'b0}},Qcnt_three_1[4:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; - Q_sqrt0={{(C_MANT_FP64-1){1'b0}},Qcnt_three_2[7:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; - Q_sqrt1={{(C_MANT_FP64-2){1'b0}},Qcnt_three_2[7:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; - Q_sqrt2={{(C_MANT_FP64-3){1'b0}},Qcnt_three_2[7:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; - Q_sqrt0={{(C_MANT_FP64-4){1'b0}},Qcnt_three_3[10:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; - Q_sqrt1={{(C_MANT_FP64-5){1'b0}},Qcnt_three_3[10:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; - Q_sqrt2={{(C_MANT_FP64-6){1'b0}},Qcnt_three_3[10:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; - Q_sqrt0={{(C_MANT_FP64-7){1'b0}},Qcnt_three_4[13:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; - Q_sqrt1={{(C_MANT_FP64-8){1'b0}},Qcnt_three_4[13:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; - Q_sqrt2={{(C_MANT_FP64-9){1'b0}},Qcnt_three_4[13:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; - Q_sqrt0={{(C_MANT_FP64-10){1'b0}},Qcnt_three_5[16:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; - Q_sqrt1={{(C_MANT_FP64-11){1'b0}},Qcnt_three_5[16:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; - Q_sqrt2={{(C_MANT_FP64-12){1'b0}},Qcnt_three_5[16:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; - Q_sqrt0={{(C_MANT_FP64-13){1'b0}},Qcnt_three_6[19:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; - Q_sqrt1={{(C_MANT_FP64-14){1'b0}},Qcnt_three_6[19:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; - Q_sqrt2={{(C_MANT_FP64-15){1'b0}},Qcnt_three_6[19:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000111: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; - Q_sqrt0={{(C_MANT_FP64-16){1'b0}},Qcnt_three_7[22:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; - Q_sqrt1={{(C_MANT_FP64-17){1'b0}},Qcnt_three_7[22:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; - Q_sqrt2={{(C_MANT_FP64-18){1'b0}},Qcnt_three_7[22:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; - Q_sqrt0={{(C_MANT_FP64-19){1'b0}},Qcnt_three_8[25:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; - Q_sqrt1={{(C_MANT_FP64-20){1'b0}},Qcnt_three_8[25:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; - Q_sqrt2={{(C_MANT_FP64-21){1'b0}},Qcnt_three_8[25:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-22){1'b0}},Qcnt_three_9[28:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-23){1'b0}},Qcnt_three_9[28:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-24){1'b0}},Qcnt_three_9[28:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-25){1'b0}},Qcnt_three_10[31:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-26){1'b0}},Qcnt_three_10[31:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-27){1'b0}},Qcnt_three_10[31:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-28){1'b0}},Qcnt_three_11[34:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-29){1'b0}},Qcnt_three_11[34:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-30){1'b0}},Qcnt_three_11[34:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-31){1'b0}},Qcnt_three_12[37:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-32){1'b0}},Qcnt_three_12[37:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-33){1'b0}},Qcnt_three_12[37:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-34){1'b0}},Qcnt_three_13[40:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-35){1'b0}},Qcnt_three_13[40:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-36){1'b0}},Qcnt_three_13[40:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-37){1'b0}},Qcnt_three_14[43:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-38){1'b0}},Qcnt_three_14[43:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-39){1'b0}},Qcnt_three_14[43:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-40){1'b0}},Qcnt_three_15[46:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-41){1'b0}},Qcnt_three_15[46:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-42){1'b0}},Qcnt_three_15[46:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b010000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-43){1'b0}},Qcnt_three_16[49:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-44){1'b0}},Qcnt_three_16[49:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-45){1'b0}},Qcnt_three_16[49:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b010001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-46){1'b0}},Qcnt_three_17[52:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-47){1'b0}},Qcnt_three_17[52:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-48){1'b0}},Qcnt_three_17[52:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b010010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-49){1'b0}},Qcnt_three_18[55:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-50){1'b0}},Qcnt_three_18[55:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-51){1'b0}},Qcnt_three_18[55:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - default : - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_three_0[2]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_three_0[2:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_three_0[2:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - endcase - - end - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b10, end // - ///////////////////////////////////////////////////////////////////////////// - - - 2'b11: - begin - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b11, start // - ///////////////////////////////////////////////////////////////////////////// - - case(Crtl_cnt_S) - - 6'b000000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_four_0[3]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_four_0[3:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_four_0[3:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; - Q_sqrt3={{(C_MANT_FP64+2){1'b0}},Qcnt_four_0[3:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; - Q_sqrt0={{(C_MANT_FP64+1){1'b0}},Qcnt_four_1[6:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; - Q_sqrt1={{(C_MANT_FP64){1'b0}},Qcnt_four_1[6:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; - Q_sqrt2={{(C_MANT_FP64-1){1'b0}},Qcnt_four_1[6:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; - Q_sqrt3={{(C_MANT_FP64-2){1'b0}},Qcnt_four_1[6:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; - Q_sqrt0={{(C_MANT_FP64-3){1'b0}},Qcnt_four_2[10:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; - Q_sqrt1={{(C_MANT_FP64-4){1'b0}},Qcnt_four_2[10:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; - Q_sqrt2={{(C_MANT_FP64-5){1'b0}},Qcnt_four_2[10:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; - Q_sqrt3={{(C_MANT_FP64-6){1'b0}},Qcnt_four_2[10:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; - Q_sqrt0={{(C_MANT_FP64-7){1'b0}},Qcnt_four_3[14:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; - Q_sqrt1={{(C_MANT_FP64-8){1'b0}},Qcnt_four_3[14:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; - Q_sqrt2={{(C_MANT_FP64-9){1'b0}},Qcnt_four_3[14:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; - Q_sqrt3={{(C_MANT_FP64-10){1'b0}},Qcnt_four_3[14:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; - Q_sqrt0={{(C_MANT_FP64-11){1'b0}},Qcnt_four_4[18:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; - Q_sqrt1={{(C_MANT_FP64-12){1'b0}},Qcnt_four_4[18:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; - Q_sqrt2={{(C_MANT_FP64-13){1'b0}},Qcnt_four_4[18:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; - Q_sqrt3={{(C_MANT_FP64-14){1'b0}},Qcnt_four_4[18:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; - Q_sqrt0={{(C_MANT_FP64-15){1'b0}},Qcnt_four_5[22:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; - Q_sqrt1={{(C_MANT_FP64-16){1'b0}},Qcnt_four_5[22:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; - Q_sqrt2={{(C_MANT_FP64-17){1'b0}},Qcnt_four_5[22:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; - Q_sqrt3={{(C_MANT_FP64-18){1'b0}},Qcnt_four_5[22:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; - Q_sqrt0={{(C_MANT_FP64-19){1'b0}},Qcnt_four_6[26:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; - Q_sqrt1={{(C_MANT_FP64-20){1'b0}},Qcnt_four_6[26:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; - Q_sqrt2={{(C_MANT_FP64-21){1'b0}},Qcnt_four_6[26:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-22){1'b0}},Qcnt_four_6[26:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-23){1'b0}},Qcnt_four_7[30:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-24){1'b0}},Qcnt_four_7[30:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-25){1'b0}},Qcnt_four_7[30:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-26){1'b0}},Qcnt_four_7[30:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-27){1'b0}},Qcnt_four_8[34:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-28){1'b0}},Qcnt_four_8[34:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-29){1'b0}},Qcnt_four_8[34:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-30){1'b0}},Qcnt_four_8[34:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-31){1'b0}},Qcnt_four_9[38:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-32){1'b0}},Qcnt_four_9[38:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-33){1'b0}},Qcnt_four_9[38:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-34){1'b0}},Qcnt_four_9[38:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-35){1'b0}},Qcnt_four_10[42:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-36){1'b0}},Qcnt_four_10[42:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-37){1'b0}},Qcnt_four_10[42:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-38){1'b0}},Qcnt_four_10[42:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-39){1'b0}},Qcnt_four_11[46:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-40){1'b0}},Qcnt_four_11[46:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-41){1'b0}},Qcnt_four_11[46:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-42){1'b0}},Qcnt_four_11[46:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-43){1'b0}},Qcnt_four_12[50:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-44){1'b0}},Qcnt_four_12[50:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-45){1'b0}},Qcnt_four_12[50:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-46){1'b0}},Qcnt_four_12[50:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-47){1'b0}},Qcnt_four_13[54:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-48){1'b0}},Qcnt_four_13[54:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-49){1'b0}},Qcnt_four_13[54:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-50){1'b0}},Qcnt_four_13[54:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - default: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_four_0[3]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_four_0[3:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_four_0[3:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; - Q_sqrt3={{(C_MANT_FP64+2){1'b0}},Qcnt_four_0[3:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - endcase - end - endcase - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b11, end // - ///////////////////////////////////////////////////////////////////////////// - end - - - - assign Sqrt_R0= ((Sqrt_start_dly_S)?'0:{Partial_remainder_DP[C_MANT_FP64+5:0]}); - assign Sqrt_R1= {Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+2:0],Sqrt_DO[0]} ; - assign Sqrt_R2= {Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+2:0],Sqrt_DO[1]}; - assign Sqrt_R3= {Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+2:0],Sqrt_DO[2]}; - assign Sqrt_R4= {Iteration_cell_sum_AMASK_D[3][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[3][C_MANT_FP64+2:0],Sqrt_DO[3]}; - - logic [C_MANT_FP64+5:0] Denominator_se_format_DB; // - - assign Denominator_se_format_DB={Denominator_se_DB[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16ALT],{FP16ALT_SO?FP16ALT_SO:Denominator_se_DB[C_MANT_FP64-C_MANT_FP16ALT-1]}, - Denominator_se_DB[C_MANT_FP64-C_MANT_FP16ALT-2:C_MANT_FP64-C_MANT_FP16],{FP16_SO?FP16_SO:Denominator_se_DB[C_MANT_FP64-C_MANT_FP16-1]}, - Denominator_se_DB[C_MANT_FP64-C_MANT_FP16-2:C_MANT_FP64-C_MANT_FP32],{FP32_SO?FP32_SO:Denominator_se_DB[C_MANT_FP64-C_MANT_FP32-1]}, - Denominator_se_DB[C_MANT_FP64-C_MANT_FP32-2:C_MANT_FP64-C_MANT_FP64],FP64_SO,3'b0} ; - // for iteration cell_U0 - logic [C_MANT_FP64+5:0] First_iteration_cell_div_a_D,First_iteration_cell_div_b_D; - logic Sel_b_for_first_S; - - - assign First_iteration_cell_div_a_D=(Div_start_dly_S)?{Numerator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16ALT],{FP16ALT_SO?FP16ALT_SO:Numerator_se_D[C_MANT_FP64-C_MANT_FP16ALT-1]}, - Numerator_se_D[C_MANT_FP64-C_MANT_FP16ALT-2:C_MANT_FP64-C_MANT_FP16],{FP16_SO?FP16_SO:Numerator_se_D[C_MANT_FP64-C_MANT_FP16-1]}, - Numerator_se_D[C_MANT_FP64-C_MANT_FP16-2:C_MANT_FP64-C_MANT_FP32],{FP32_SO?FP32_SO:Numerator_se_D[C_MANT_FP64-C_MANT_FP32-1]}, - Numerator_se_D[C_MANT_FP64-C_MANT_FP32-2:C_MANT_FP64-C_MANT_FP64],FP64_SO,3'b0} - :{Partial_remainder_DP[C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Quotient_DP[0]:Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16ALT+2]}, - Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Quotient_DP[0]:Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16+2]}, - Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Quotient_DP[0]:Partial_remainder_DP[C_MANT_FP64-C_MANT_FP32+2]}, - Partial_remainder_DP[C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Quotient_DP[0],3'b0}; - assign Sel_b_for_first_S=(Div_start_dly_S)?1:Quotient_DP[0]; - assign First_iteration_cell_div_b_D=Sel_b_for_first_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; - assign Iteration_cell_a_BMASK_D[0]=Sqrt_enable_SO?Sqrt_R0:{First_iteration_cell_div_a_D}; - assign Iteration_cell_b_BMASK_D[0]=Sqrt_enable_SO?Sqrt_Q0:{First_iteration_cell_div_b_D}; - - - - // for iteration cell_U1 - logic [C_MANT_FP64+5:0] Sec_iteration_cell_div_a_D,Sec_iteration_cell_div_b_D; - logic Sel_b_for_sec_S; - generate - if(|Iteration_unit_num_S) - begin - assign Sel_b_for_sec_S=~Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+5]; - assign Sec_iteration_cell_div_a_D={Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Sel_b_for_sec_S:Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16ALT+2]}, - Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Sel_b_for_sec_S:Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16+2]}, - Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Sel_b_for_sec_S:Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP32+2]}, - Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Sel_b_for_sec_S,3'b0}; - assign Sec_iteration_cell_div_b_D=Sel_b_for_sec_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; - assign Iteration_cell_a_BMASK_D[1]=Sqrt_enable_SO?Sqrt_R1:{Sec_iteration_cell_div_a_D}; - assign Iteration_cell_b_BMASK_D[1]=Sqrt_enable_SO?Sqrt_Q1:{Sec_iteration_cell_div_b_D}; - end - endgenerate - - // for iteration cell_U2 - logic [C_MANT_FP64+5:0] Thi_iteration_cell_div_a_D,Thi_iteration_cell_div_b_D; - logic Sel_b_for_thi_S; - generate - if((Iteration_unit_num_S==2'b10) | (Iteration_unit_num_S==2'b11)) - begin - assign Sel_b_for_thi_S=~Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+5]; - assign Thi_iteration_cell_div_a_D={Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Sel_b_for_thi_S:Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16ALT+2]}, - Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Sel_b_for_thi_S:Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16+2]}, - Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Sel_b_for_thi_S:Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP32+2]}, - Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Sel_b_for_thi_S,3'b0}; - assign Thi_iteration_cell_div_b_D=Sel_b_for_thi_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; - assign Iteration_cell_a_BMASK_D[2]=Sqrt_enable_SO?Sqrt_R2:{Thi_iteration_cell_div_a_D}; - assign Iteration_cell_b_BMASK_D[2]=Sqrt_enable_SO?Sqrt_Q2:{Thi_iteration_cell_div_b_D}; - end - endgenerate - - // for iteration cell_U3 - logic [C_MANT_FP64+5:0] Fou_iteration_cell_div_a_D,Fou_iteration_cell_div_b_D; - logic Sel_b_for_fou_S; - - generate - if(Iteration_unit_num_S==2'b11) - begin - assign Sel_b_for_fou_S=~Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+5]; - assign Fou_iteration_cell_div_a_D={Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Sel_b_for_fou_S:Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16ALT+2]}, - Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Sel_b_for_fou_S:Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16+2]}, - Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Sel_b_for_fou_S:Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP32+2]}, - Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Sel_b_for_fou_S,3'b0}; - assign Fou_iteration_cell_div_b_D=Sel_b_for_fou_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; - assign Iteration_cell_a_BMASK_D[3]=Sqrt_enable_SO?Sqrt_R3:{Fou_iteration_cell_div_a_D}; - assign Iteration_cell_b_BMASK_D[3]=Sqrt_enable_SO?Sqrt_Q3:{Fou_iteration_cell_div_b_D}; - end - endgenerate - - ///////////////////////////////////////////////////////////////////////////// - // Masking Contrl // - ///////////////////////////////////////////////////////////////////////////// - - - logic [C_MANT_FP64+1+4:0] Mask_bits_ctl_S; //For extension - - assign Mask_bits_ctl_S =58'h3ff_ffff_ffff_ffff; //It is not needed. The corresponding process is handled the above codes - - ///////////////////////////////////////////////////////////////////////////// - // Iteration Instances with masking control // - ///////////////////////////////////////////////////////////////////////////// - - - logic Div_enable_SI [3:0]; - logic Div_start_dly_SI [3:0]; - logic Sqrt_enable_SI [3:0]; - generate - genvar i,j; - for (i=0; i <= Iteration_unit_num_S ; i++) - begin - for (j = 0; j <= C_MANT_FP64+5; j++) begin - assign Iteration_cell_a_D[i][j] = Mask_bits_ctl_S[j] && Iteration_cell_a_BMASK_D[i][j]; - assign Iteration_cell_b_D[i][j] = Mask_bits_ctl_S[j] && Iteration_cell_b_BMASK_D[i][j]; - assign Iteration_cell_sum_AMASK_D[i][j] = Mask_bits_ctl_S[j] && Iteration_cell_sum_D[i][j]; - end - - assign Div_enable_SI[i] = Div_enable_SO; - assign Div_start_dly_SI[i] = Div_start_dly_S; - assign Sqrt_enable_SI[i] = Sqrt_enable_SO; - iteration_div_sqrt_mvp #(C_MANT_FP64+6) iteration_div_sqrt - ( - .A_DI (Iteration_cell_a_D[i] ), - .B_DI (Iteration_cell_b_D[i] ), - .Div_enable_SI (Div_enable_SI[i] ), - .Div_start_dly_SI (Div_start_dly_SI[i] ), - .Sqrt_enable_SI (Sqrt_enable_SI[i] ), - .D_DI (Sqrt_DI[i] ), - .D_DO (Sqrt_DO[i] ), - .Sum_DO (Iteration_cell_sum_D[i] ), - .Carry_out_DO (Iteration_cell_carry_D[i] ) - ); - - end - - endgenerate - - - - always_comb - begin - case (Iteration_unit_num_S) - 2'b00: - begin - if(Fsm_enable_S) - Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R1:Iteration_cell_sum_AMASK_D[0]; - else - Partial_remainder_DN = Partial_remainder_DP; - end - 2'b01: - begin - if(Fsm_enable_S) - Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R2:Iteration_cell_sum_AMASK_D[1]; - else - Partial_remainder_DN = Partial_remainder_DP; - end - 2'b10: - begin - if(Fsm_enable_S) - Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R3:Iteration_cell_sum_AMASK_D[2]; - else - Partial_remainder_DN = Partial_remainder_DP; - end - 2'b11: - begin - if(Fsm_enable_S) - Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R4:Iteration_cell_sum_AMASK_D[3]; - else - Partial_remainder_DN = Partial_remainder_DP; - end - endcase - end - - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) // partial_remainder - begin - if(~Rst_RBI) - begin - Partial_remainder_DP <= '0; - end - else - begin - Partial_remainder_DP <= Partial_remainder_DN; - end - end - - logic [C_MANT_FP64+4:0] Quotient_DN; - - always_comb // Can choosen the different carry-outs based on different operations - begin - case (Iteration_unit_num_S) - 2'b00: - begin - if(Fsm_enable_S) - Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64+3:0],Sqrt_quotinent_S[3]} :{Quotient_DP[C_MANT_FP64+3:0],Iteration_cell_carry_D[0]}; - else - Quotient_DN= Quotient_DP; - end - 2'b01: - begin - if(Fsm_enable_S) - Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64+2:0],Sqrt_quotinent_S[3:2]} :{Quotient_DP[C_MANT_FP64+2:0],Iteration_cell_carry_D[0],Iteration_cell_carry_D[1]}; - else - Quotient_DN= Quotient_DP; - end - 2'b10: - begin - if(Fsm_enable_S) - Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64+1:0],Sqrt_quotinent_S[3:1]} : {Quotient_DP[C_MANT_FP64+1:0],Iteration_cell_carry_D[0],Iteration_cell_carry_D[1],Iteration_cell_carry_D[2]}; - else - Quotient_DN= Quotient_DP; - end - 2'b11: - begin - if(Fsm_enable_S) - Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64:0],Sqrt_quotinent_S } : {Quotient_DP[C_MANT_FP64:0],Iteration_cell_carry_D[0],Iteration_cell_carry_D[1],Iteration_cell_carry_D[2],Iteration_cell_carry_D[3]}; - else - Quotient_DN= Quotient_DP; - end - endcase - end - - always_ff @(posedge Clk_CI, negedge Rst_RBI) // Quotient - begin - if(~Rst_RBI) - begin - Quotient_DP <= '0; - end - else - Quotient_DP <= Quotient_DN; - end - - - ///////////////////////////////////////////////////////////////////////////// - // Precision Control for outputs // - ///////////////////////////////////////////////////////////////////////////// - - -//////////////////////one iteration unit, start/////////////////////////////////////// - generate - if(Iteration_unit_num_S==2'b00) - begin - always_comb - begin - case (Format_sel_S) - 2'b00: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - 6'h17: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h16: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-1:0],{(C_MANT_FP64-C_MANT_FP32+4+1){1'b0}}}; //Precision_ctl_S+1 - end - 6'h15: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-2:0],{(C_MANT_FP64-C_MANT_FP32+4+2){1'b0}}}; //Precision_ctl_S+1 - end - 6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-3:0],{(C_MANT_FP64-C_MANT_FP32+4+3){1'b0}}}; //Precision_ctl_S+1 - end - 6'h13: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-4:0],{(C_MANT_FP64-C_MANT_FP32+4+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-5:0],{(C_MANT_FP64-C_MANT_FP32+4+5){1'b0}}}; //Precision_ctl_S+1 - end - 6'h11: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-6:0],{(C_MANT_FP64-C_MANT_FP32+4+6){1'b0}}}; //Precision_ctl_S+1 - end - 6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-7:0],{(C_MANT_FP64-C_MANT_FP32+4+7){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-8:0],{(C_MANT_FP64-C_MANT_FP32+4+8){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-9:0],{(C_MANT_FP64-C_MANT_FP32+4+9){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0d: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-10:0],{(C_MANT_FP64-C_MANT_FP32+4+10){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-11:0],{(C_MANT_FP64-C_MANT_FP32+4+11){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0b: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-13:0],{(C_MANT_FP64-C_MANT_FP32+4+13){1'b0}}}; //Precision_ctl_S+1 - end - 6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-14:0],{(C_MANT_FP64-C_MANT_FP32+4+14){1'b0}}}; //Precision_ctl_S+1 - end - 6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-15:0],{(C_MANT_FP64-C_MANT_FP32+4+15){1'b0}}}; //Precision_ctl_S+1 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-16:0],{(C_MANT_FP64-C_MANT_FP32+4+16){1'b0}}}; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - endcase - end - - 2'b01: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 - end - 6'h34: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64:0],{(4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h33: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-1:0],{(4+1){1'b0}}}; //Precision_ctl_S+1 - end - 6'h32: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-2:0],{(4+2){1'b0}}}; //Precision_ctl_S+1 - end - 6'h31: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-3:0],{(4+3){1'b0}}}; //Precision_ctl_S+1 - end - 6'h30: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-4:0],{(4+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(4+5){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-6:0],{(4+6){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2d: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-7:0],{(4+7){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-8:0],{(4+8){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2b: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-9:0],{(4+9){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-10:0],{(4+10){1'b0}}}; //Precision_ctl_S+1 - end - 6'h29: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-11:0],{(4+11){1'b0}}}; //Precision_ctl_S+1 - end - 6'h28: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-12:0],{(4+12){1'b0}}}; //Precision_ctl_S+1 - end - 6'h27: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-13:0],{(4+13){1'b0}}}; //Precision_ctl_S+1 - end - 6'h26: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-14:0],{(4+14){1'b0}}}; //Precision_ctl_S+1 - end - 6'h25: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-15:0],{(4+15){1'b0}}}; //Precision_ctl_S+1 - end - 6'h24: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-16:0],{(4+16){1'b0}}}; //Precision_ctl_S+1 - end - 6'h23: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(4+17){1'b0}}}; //Precision_ctl_S+1 - end - 6'h22: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-18:0],{(4+18){1'b0}}}; //Precision_ctl_S+1 - end - 6'h21: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-19:0],{(4+19){1'b0}}}; //Precision_ctl_S+1 - end - 6'h20: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-20:0],{(4+20){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-21:0],{(4+21){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-22:0],{(4+22){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1d: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-23:0],{(4+23){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-24:0],{(4+24){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1b: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-25:0],{(4+25){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-26:0],{(4+26){1'b0}}}; //Precision_ctl_S+1 - end - 6'h19: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-27:0],{(4+27){1'b0}}}; //Precision_ctl_S+1 - end - 6'h18: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-28:0],{(4+28){1'b0}}}; //Precision_ctl_S+1 - end - 6'h17: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(4+29){1'b0}}}; //Precision_ctl_S+1 - end - 6'h16: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-30:0],{(4+30){1'b0}}}; //Precision_ctl_S+1 - end - 6'h15: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-31:0],{(4+31){1'b0}}}; //Precision_ctl_S+1 - end - 6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-32:0],{(4+32){1'b0}}}; //Precision_ctl_S+1 - end - 6'h13: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-33:0],{(4+33){1'b0}}}; //Precision_ctl_S+1 - end - 6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-34:0],{(4+34){1'b0}}}; //Precision_ctl_S+1 - end - 6'h11: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-35:0],{(4+35){1'b0}}}; //Precision_ctl_S+1 - end - 6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-36:0],{(4+36){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-37:0],{(4+37){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-38:0],{(4+38){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0d: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-39:0],{(4+39){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-40:0],{(4+40){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0b: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(4+41){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-42:0],{(4+42){1'b0}}}; //Precision_ctl_S+1 - end - 6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-43:0],{(4+43){1'b0}}}; //Precision_ctl_S+1 - end - 6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-44:0],{(4+44){1'b0}}}; //Precision_ctl_S+1 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-45:0],{(4+45){1'b0}}}; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 - end - endcase - end - - 2'b10: - begin - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}}}; //+4 - end - 6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16:0],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-1:0],{(C_MANT_FP64-C_MANT_FP16+4+1){1'b0}}}; //Precision_ctl_S+1 - end - 6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-2:0],{(C_MANT_FP64-C_MANT_FP16+4+2){1'b0}}}; //Precision_ctl_S+1 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-3:0],{(C_MANT_FP64-C_MANT_FP16+4+3){1'b0}}}; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}}}; //+4 - end - endcase - end - - 2'b11: - begin - - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}}}; //+4 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT:0],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}}}; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}}}; //+4 - end - endcase - end - endcase - end - end - endgenerate -//////////////////////one iteration unit, end////////////////////////////////////////// - -//////////////////////two iteration units, start/////////////////////////////////////// - generate - if(Iteration_unit_num_S==2'b01) - begin - always_comb - begin - case (Format_sel_S) - 2'b00: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - 6'h17,6'h16: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h15,6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-2:0],{(C_MANT_FP64-C_MANT_FP32+4+2){1'b0}}}; //Precision_ctl_S+1 - end - 6'h13,6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-4:0],{(C_MANT_FP64-C_MANT_FP32+4+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h11,6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-6:0],{(C_MANT_FP64-C_MANT_FP32+4+6){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0f,6'h0e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-8:0],{(C_MANT_FP64-C_MANT_FP32+4+8){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-10:0],{(C_MANT_FP64-C_MANT_FP32+4+10){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0b,6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 - end - 6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-14:0],{(C_MANT_FP64-C_MANT_FP32+4+14){1'b0}}}; //Precision_ctl_S+1 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-16:0],{(C_MANT_FP64-C_MANT_FP32+4+16){1'b0}}}; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - endcase - end - 2'b01: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],1'b0}; //+3 - end - 6'h34: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+1:1],{(4){1'b0}} }; //Precision_ctl_S+1 - end - 6'h33,6'h32: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-1:0],{(4+1){1'b0}} }; //Precision_ctl_S+1 - end - 6'h31,6'h30: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-3:0],{(4+3){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2f,6'h2e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(4+5){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2d,6'h2c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-7:0],{(4+7){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2b,6'h2a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-9:0],{(4+9){1'b0}} }; //Precision_ctl_S+1 - end - 6'h29,6'h28: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-11:0],{(4+11){1'b0}} }; //Precision_ctl_S+1 - end - 6'h27,6'h26: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-13:0],{(4+13){1'b0}} }; //Precision_ctl_S+1 - end - 6'h25,6'h24: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-15:0],{(4+15){1'b0}} }; //Precision_ctl_S+1 - end - 6'h23,6'h22: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(4+17){1'b0}} }; //Precision_ctl_S+1 - end - 6'h21,6'h20: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-19:0],{(4+19){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1f,6'h1e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-21:0],{(4+21){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1d,6'h1c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-23:0],{(4+23){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1b,6'h1a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-25:0],{(4+25){1'b0}} }; //Precision_ctl_S+1 - end - 6'h19,6'h18: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-27:0],{(4+27){1'b0}} }; //Precision_ctl_S+1 - end - 6'h17,6'h16: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(4+29){1'b0}} }; //Precision_ctl_S+1 - end - 6'h15,6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-31:0],{(4+31){1'b0}} }; //Precision_ctl_S+1 - end - 6'h13,6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-33:0],{(4+33){1'b0}} }; //Precision_ctl_S+1 - end - 6'h11,6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-35:0],{(4+35){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0f,6'h0e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-37:0],{(4+37){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-39:0],{(4+39){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0b,6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(4+41){1'b0}} }; //Precision_ctl_S+1 - end - 6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-43:0],{(4+43){1'b0}} }; //Precision_ctl_S+1 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-45:0],{(4+45){1'b0}} }; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],1'b0}; //+3 - end - endcase - end - - 2'b10: - begin - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+3:0],{(C_MANT_FP64-C_MANT_FP16+1){1'b0}} }; //+3 - end - 6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1:1],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}} }; //Precision_ctl_S+1 - end - 6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-1:0],{(C_MANT_FP64-C_MANT_FP16+4+1){1'b0}} }; //Precision_ctl_S+1 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-3:0],{(C_MANT_FP64-C_MANT_FP16+4+3){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+4 - end - endcase - end - - 2'b11: - begin - - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT:0],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - endcase - end - endcase - end - end - endgenerate -//////////////////////two iteration units, end////////////////////////////////////////// - -//////////////////////three iteration units, start/////////////////////////////////////// - generate - if(Iteration_unit_num_S==2'b10) - begin - always_comb - begin - case (Format_sel_S) - 2'b00: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+3:0],{(C_MANT_FP64-C_MANT_FP32+1){1'b0}}}; //+3 - end - 6'h17,6'h16,6'h15: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h14,6'h13,6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-3:0],{(C_MANT_FP64-C_MANT_FP32+4+3){1'b0}}}; //Precision_ctl_S+1 - end - 6'h11,6'h10,6'h0f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-6:0],{(C_MANT_FP64-C_MANT_FP32+4+6){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0e,6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-9:0],{(C_MANT_FP64-C_MANT_FP32+4+9){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0b,6'h0a,6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 - end - 6'h08,6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-15:0],{(C_MANT_FP64-C_MANT_FP32+4+15){1'b0}}}; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+3:0],{(C_MANT_FP64-C_MANT_FP32+1){1'b0}}}; //+3 - end - endcase - end - - 2'b01: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 - end - 6'h34,6'h33: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+1:1],{(4){1'b0}} }; //Precision_ctl_S+1 - end - 6'h32,6'h31,6'h30: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-2:0],{(4+2){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2f,6'h2e,6'h2d: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(4+5){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2c,6'h2b,6'h2a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-8:0],{(4+8){1'b0}} }; //Precision_ctl_S+1 - end - 6'h29,6'h28,6'h27: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-11:0],{(4+11){1'b0}} }; //Precision_ctl_S+1 - end - 6'h26,6'h25,6'h24: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-14:0],{(4+14){1'b0}} }; //Precision_ctl_S+1 - end - 6'h23,6'h22,6'h21: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(4+17){1'b0}} }; //Precision_ctl_S+1 - end - 6'h20,6'h1f,6'h1e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-20:0],{(4+20){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1d,6'h1c,6'h1b: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-23:0],{(4+23){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1a,6'h19,6'h18: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-26:0],{(4+26){1'b0}} }; //Precision_ctl_S+1 - end - 6'h17,6'h16,6'h15: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(4+29){1'b0}} }; //Precision_ctl_S+1 - end - 6'h14,6'h13,6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-32:0],{(4+32){1'b0}} }; //Precision_ctl_S+1 - end - 6'h11,6'h10,6'h0f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-35:0],{(4+35){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0e,6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-38:0],{(4+38){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0b,6'h0a,6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(4+41){1'b0}} }; //Precision_ctl_S+1 - end - 6'h08,6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-44:0],{(4+44){1'b0}} }; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 - end - endcase - end - - 2'b10: - begin - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+4 - end - 6'h0a,6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1:1],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}} }; //Precision_ctl_S+1 - end - 6'h08,6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-2:0],{(C_MANT_FP64-C_MANT_FP16+4+2){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+4 - end - endcase - end - - 2'b11: - begin - - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+1:1],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - endcase - end - endcase - end - end - endgenerate -//////////////////////three iteration units, end////////////////////////////////////////// - -//////////////////////four iteration units, start/////////////////////////////////////// - generate - if(Iteration_unit_num_S==2'b11) - begin - always_comb - begin - case (Format_sel_S) - 2'b00: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - 6'h17,6'h16,6'h15,6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h13,6'h12,6'h11,6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-4:0],{(C_MANT_FP64-C_MANT_FP32+4+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0f,6'h0e,6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-8:0],{(C_MANT_FP64-C_MANT_FP32+4+8){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0b,6'h0a,6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-16:0],{(C_MANT_FP64-C_MANT_FP32+4+16){1'b0}}}; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - endcase - end - - 2'b01: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}}}; //+3 - end - 6'h34: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}} }; //Precision_ctl_S+1 - end - 6'h33,6'h32,6'h31,6'h30: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-1:0],{(5){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2f,6'h2e,6'h2d,6'h2c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(9){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2b,6'h2a,6'h29,6'h28: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-9:0],{(13){1'b0}} }; //Precision_ctl_S+1 - end - 6'h27,6'h26,6'h25,6'h24: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-13:0],{(17){1'b0}} }; //Precision_ctl_S+1 - end - 6'h23,6'h22,6'h21,6'h20: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(21){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1f,6'h1e,6'h1d,6'h1c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-21:0],{(25){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1b,6'h1a,6'h19,6'h18: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-25:0],{(29){1'b0}} }; //Precision_ctl_S+1 - end - 6'h17,6'h16,6'h15,6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(33){1'b0}} }; //Precision_ctl_S+1 - end - 6'h13,6'h12,6'h11,6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-33:0],{(37){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0f,6'h0e,6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-37:0],{(41){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0b,6'h0a,6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(45){1'b0}} }; //Precision_ctl_S+1 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-45:0],{(49){1'b0}} }; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}}}; //+3 - end - endcase - end - - 2'b10: - begin - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+5:0],{(C_MANT_FP64-C_MANT_FP16-1){1'b0}} }; //+5 - end - 6'h0a,6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1:1],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}} }; //Precision_ctl_S+1 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1-4:0],{(C_MANT_FP64-C_MANT_FP16+4+3){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+5:0],{(C_MANT_FP64-C_MANT_FP16-1){1'b0}} }; //+5 - end - endcase - end - - 2'b11: - begin - - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT:0],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - endcase - end - endcase - end - end - endgenerate -//////////////////////four iteration units, end/////////////////////////////////////// - - - - - -// resultant exponent - logic [C_EXP_FP64+1:0] Exp_result_prenorm_DN,Exp_result_prenorm_DP; - - logic [C_EXP_FP64+1:0] Exp_add_a_D; - logic [C_EXP_FP64+1:0] Exp_add_b_D; - logic [C_EXP_FP64+1:0] Exp_add_c_D; - - integer C_BIAS_AONE, C_HALF_BIAS; - always_comb - begin // - case (Format_sel_S) - 2'b00: - begin - C_BIAS_AONE =C_BIAS_AONE_FP32; - C_HALF_BIAS =C_HALF_BIAS_FP32; - end - 2'b01: - begin - C_BIAS_AONE =C_BIAS_AONE_FP64; - C_HALF_BIAS =C_HALF_BIAS_FP64; - end - 2'b10: - begin - C_BIAS_AONE =C_BIAS_AONE_FP16; - C_HALF_BIAS =C_HALF_BIAS_FP16; - end - 2'b11: - begin - C_BIAS_AONE =C_BIAS_AONE_FP16ALT; - C_HALF_BIAS =C_HALF_BIAS_FP16ALT; - end - endcase - end - -//For division, exponent=(Exp_a_D-LZ1)-(Exp_b_D-LZ2)+BIAS -//For square root, exponent=(Exp_a_D-LZ1)/2+(Exp_a_D-LZ1)%2+C_HALF_BIAS -//For exponent, in preprorces module, (Exp_a_D-LZ1) and (Exp_b_D-LZ2) have been processed with the corresponding process for denormal numbers. - - assign Exp_add_a_D = {Sqrt_start_dly_S?{Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64:1]}:{Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64],Exp_num_DI}}; - assign Exp_add_b_D = {Sqrt_start_dly_S?{1'b0,{C_EXP_ZERO_FP64},Exp_num_DI[0]}:{~Exp_den_DI[C_EXP_FP64],~Exp_den_DI[C_EXP_FP64],~Exp_den_DI}}; - assign Exp_add_c_D = {Div_start_dly_S?{{C_BIAS_AONE}}:{{C_HALF_BIAS}}}; - assign Exp_result_prenorm_DN = (Start_dly_S)?{Exp_add_a_D + Exp_add_b_D + Exp_add_c_D}:Exp_result_prenorm_DP; - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Exp_result_prenorm_DP <= '0; - end - else - begin - Exp_result_prenorm_DP<= Exp_result_prenorm_DN; - end - end - - assign Exp_result_prenorm_DO = Exp_result_prenorm_DP; - -endmodule diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv deleted file mode 100644 index b3f41fec6..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv +++ /dev/null @@ -1,83 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// This file contains all div_sqrt_top_mvp parameters -// Authors : Lei Li (lile@iis.ee.ethz.ch) - -package defs_div_sqrt_mvp; - - // op command - localparam C_RM = 3; - localparam C_RM_NEAREST = 3'h0; - localparam C_RM_TRUNC = 3'h1; - localparam C_RM_PLUSINF = 3'h2; - localparam C_RM_MINUSINF = 3'h3; - localparam C_PC = 6; // Precision Control - localparam C_FS = 2; // Format Selection - localparam C_IUNC = 2; // Iteration Unit Number Control - localparam Iteration_unit_num_S = 2'b10; - - // FP64 - localparam C_OP_FP64 = 64; - localparam C_MANT_FP64 = 52; - localparam C_EXP_FP64 = 11; - localparam C_BIAS_FP64 = 1023; - localparam C_BIAS_AONE_FP64 = 11'h400; - localparam C_HALF_BIAS_FP64 = 511; - localparam C_EXP_ZERO_FP64 = 11'h000; - localparam C_EXP_ONE_FP64 = 13'h001; // Bit width is in agreement with in norm - localparam C_EXP_INF_FP64 = 11'h7FF; - localparam C_MANT_ZERO_FP64 = 52'h0; - localparam C_MANT_NAN_FP64 = 52'h8_0000_0000_0000; - localparam C_PZERO_FP64 = 64'h0000_0000_0000_0000; - localparam C_MZERO_FP64 = 64'h8000_0000_0000_0000; - localparam C_QNAN_FP64 = 64'h7FF8_0000_0000_0000; - - // FP32 - localparam C_OP_FP32 = 32; - localparam C_MANT_FP32 = 23; - localparam C_EXP_FP32 = 8; - localparam C_BIAS_FP32 = 127; - localparam C_BIAS_AONE_FP32 = 8'h80; - localparam C_HALF_BIAS_FP32 = 63; - localparam C_EXP_ZERO_FP32 = 8'h00; - localparam C_EXP_INF_FP32 = 8'hFF; - localparam C_MANT_ZERO_FP32 = 23'h0; - localparam C_PZERO_FP32 = 32'h0000_0000; - localparam C_MZERO_FP32 = 32'h8000_0000; - localparam C_QNAN_FP32 = 32'h7FC0_0000; - - // FP16 - localparam C_OP_FP16 = 16; - localparam C_MANT_FP16 = 10; - localparam C_EXP_FP16 = 5; - localparam C_BIAS_FP16 = 15; - localparam C_BIAS_AONE_FP16 = 5'h10; - localparam C_HALF_BIAS_FP16 = 7; - localparam C_EXP_ZERO_FP16 = 5'h00; - localparam C_EXP_INF_FP16 = 5'h1F; - localparam C_MANT_ZERO_FP16 = 10'h0; - localparam C_PZERO_FP16 = 16'h0000; - localparam C_MZERO_FP16 = 16'h8000; - localparam C_QNAN_FP16 = 16'h7E00; - - // FP16alt - localparam C_OP_FP16ALT = 16; - localparam C_MANT_FP16ALT = 7; - localparam C_EXP_FP16ALT = 8; - localparam C_BIAS_FP16ALT = 127; - localparam C_BIAS_AONE_FP16ALT = 8'h80; - localparam C_HALF_BIAS_FP16ALT = 63; - localparam C_EXP_ZERO_FP16ALT = 8'h00; - localparam C_EXP_INF_FP16ALT = 8'hFF; - localparam C_MANT_ZERO_FP16ALT = 7'h0; - localparam C_QNAN_FP16ALT = 16'h7FC0; - -endpackage : defs_div_sqrt_mvp diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv deleted file mode 100644 index 051bcc3ad..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv +++ /dev/null @@ -1,232 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li -- lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 20/04/2018 // -// Design Name: FPU // -// Module Name: div_sqrt_mvp_wrapper.sv // -// Project Name: The shared divisor and square root // -// Language: SystemVerilog // -// // -// Description: The wrapper of div_sqrt_top_mvp // -// // -// // -// // -// // -// // -// // -// // -// // -// // -// // -// // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module div_sqrt_mvp_wrapper -#( - parameter PrePipeline_depth_S = 0, // If you want to add a flip/flop stage before preprocess, set it to 1. - parameter PostPipeline_depth_S = 2 // The output delay stages -) - (//Input - input logic Clk_CI, - input logic Rst_RBI, - input logic Div_start_SI, - input logic Sqrt_start_SI, - - //Input Operands - input logic [C_OP_FP64-1:0] Operand_a_DI, - input logic [C_OP_FP64-1:0] Operand_b_DI, - - // Input Control - input logic [C_RM-1:0] RM_SI, //Rounding Mode - input logic [C_PC-1:0] Precision_ctl_SI, // Precision Control - input logic [C_FS-1:0] Format_sel_SI, // Format Selection, - input logic Kill_SI, - - //Output Result - output logic [C_OP_FP64-1:0] Result_DO, - - //Output-Flags - output logic [4:0] Fflags_SO, - output logic Ready_SO, - output logic Done_SO - ); - - - logic Div_start_S_S,Sqrt_start_S_S; - logic [C_OP_FP64-1:0] Operand_a_S_D; - logic [C_OP_FP64-1:0] Operand_b_S_D; - - // Input Control - logic [C_RM-1:0] RM_S_S; //Rounding Mode - logic [C_PC-1:0] Precision_ctl_S_S; // Precision Control - logic [C_FS-1:0] Format_sel_S_S; // Format Selection, - logic Kill_S_S; - - - logic [C_OP_FP64-1:0] Result_D; - logic Ready_S; - logic Done_S; - logic [4:0] Fflags_S; - - - generate - if(PrePipeline_depth_S==1) - begin - - div_sqrt_top_mvp div_top_U0 //for RTL - - (//Input - .Clk_CI (Clk_CI), - .Rst_RBI (Rst_RBI), - .Div_start_SI (Div_start_S_S), - .Sqrt_start_SI (Sqrt_start_S_S), - //Input Operands - .Operand_a_DI (Operand_a_S_D), - .Operand_b_DI (Operand_b_S_D), - .RM_SI (RM_S_S), //Rounding Mode - .Precision_ctl_SI (Precision_ctl_S_S), - .Format_sel_SI (Format_sel_S_S), - .Kill_SI (Kill_S_S), - .Result_DO (Result_D), - .Fflags_SO (Fflags_S), - .Ready_SO (Ready_S), - .Done_SO (Done_S) - ); - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Div_start_S_S<='0; - Sqrt_start_S_S<=1'b0; - Operand_a_S_D<='0; - Operand_b_S_D<='0; - RM_S_S <=1'b0; - Precision_ctl_S_S<='0; - Format_sel_S_S<='0; - Kill_S_S<='0; - end - else - begin - Div_start_S_S<=Div_start_SI; - Sqrt_start_S_S<=Sqrt_start_SI; - Operand_a_S_D<=Operand_a_DI; - Operand_b_S_D<=Operand_b_DI; - RM_S_S <=RM_SI; - Precision_ctl_S_S<=Precision_ctl_SI; - Format_sel_S_S<=Format_sel_SI; - Kill_S_S<=Kill_SI; - end - end - end - - else - begin - div_sqrt_top_mvp div_top_U0 //for RTL - (//Input - .Clk_CI (Clk_CI), - .Rst_RBI (Rst_RBI), - .Div_start_SI (Div_start_SI), - .Sqrt_start_SI (Sqrt_start_SI), - //Input Operands - .Operand_a_DI (Operand_a_DI), - .Operand_b_DI (Operand_b_DI), - .RM_SI (RM_SI), //Rounding Mode - .Precision_ctl_SI (Precision_ctl_SI), - .Format_sel_SI (Format_sel_SI), - .Kill_SI (Kill_SI), - .Result_DO (Result_D), - .Fflags_SO (Fflags_S), - .Ready_SO (Ready_S), - .Done_SO (Done_S) - ); - end - endgenerate - - ///////////////////////////////////////////////////////////////////////////// - // First Stage of Outputs - ///////////////////////////////////////////////////////////////////////////// - logic [C_OP_FP64-1:0] Result_dly_S_D; - logic Ready_dly_S_S; - logic Done_dly_S_S; - logic [4:0] Fflags_dly_S_S; - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Result_dly_S_D<='0; - Ready_dly_S_S<=1'b0; - Done_dly_S_S<=1'b0; - Fflags_dly_S_S<=1'b0; - end - else - begin - Result_dly_S_D<=Result_D; - Ready_dly_S_S<=Ready_S; - Done_dly_S_S<=Done_S; - Fflags_dly_S_S<=Fflags_S; - end - end - - ///////////////////////////////////////////////////////////////////////////// - // Second Stage of Outputs - ///////////////////////////////////////////////////////////////////////////// - - logic [C_OP_FP64-1:0] Result_dly_D_D; - logic Ready_dly_D_S; - logic Done_dly_D_S; - logic [4:0] Fflags_dly_D_S; - generate - if(PostPipeline_depth_S==2) - begin - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Result_dly_D_D<='0; - Ready_dly_D_S<=1'b0; - Done_dly_D_S<=1'b0; - Fflags_dly_D_S<=1'b0; - end - else - begin - Result_dly_D_D<=Result_dly_S_D; - Ready_dly_D_S<=Ready_dly_S_S; - Done_dly_D_S<=Done_dly_S_S; - Fflags_dly_D_S<=Fflags_dly_S_S; - end - end - assign Result_DO = Result_dly_D_D; - assign Ready_SO = Ready_dly_D_S; - assign Done_SO = Done_dly_D_S; - assign Fflags_SO=Fflags_dly_D_S; - end - - else - begin - assign Result_DO = Result_dly_S_D; - assign Ready_SO = Ready_dly_S_S; - assign Done_SO = Done_dly_S_S; - assign Fflags_SO = Fflags_dly_S_S; - end - - endgenerate - -endmodule // diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv deleted file mode 100644 index 3af6081b7..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv +++ /dev/null @@ -1,180 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li -- lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 03/03/2018 // -// Design Name: div_sqrt_top_mvp // -// Module Name: div_sqrt_top_mvp.sv // -// Project Name: The shared divisor and square root // -// Language: SystemVerilog // -// // -// Description: The top of div and sqrt // -// // -// // -// Revision Date: 12/04/2018 // -// Lei Li // -// To address some requirements by Stefan and add low power // -// control for special cases // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module div_sqrt_top_mvp - - (//Input - input logic Clk_CI, - input logic Rst_RBI, - input logic Div_start_SI, - input logic Sqrt_start_SI, - - //Input Operands - input logic [C_OP_FP64-1:0] Operand_a_DI, - input logic [C_OP_FP64-1:0] Operand_b_DI, - - // Input Control - input logic [C_RM-1:0] RM_SI, //Rounding Mode - input logic [C_PC-1:0] Precision_ctl_SI, // Precision Control - input logic [C_FS-1:0] Format_sel_SI, // Format Selection, - input logic Kill_SI, - - //Output Result - output logic [C_OP_FP64-1:0] Result_DO, - - //Output-Flags - output logic [4:0] Fflags_SO, - output logic Ready_SO, - output logic Done_SO - ); - - - - - - //Operand components - logic [C_EXP_FP64:0] Exp_a_D; - logic [C_EXP_FP64:0] Exp_b_D; - logic [C_MANT_FP64:0] Mant_a_D; - logic [C_MANT_FP64:0] Mant_b_D; - - logic [C_EXP_FP64+1:0] Exp_z_D; - logic [C_MANT_FP64+4:0] Mant_z_D; - logic Sign_z_D; - logic Start_S; - logic [C_RM-1:0] RM_dly_S; - logic Div_enable_S; - logic Sqrt_enable_S; - logic Inf_a_S; - logic Inf_b_S; - logic Zero_a_S; - logic Zero_b_S; - logic NaN_a_S; - logic NaN_b_S; - logic SNaN_S; - logic Special_case_SB,Special_case_dly_SB; - - logic Full_precision_S; - logic FP32_S; - logic FP64_S; - logic FP16_S; - logic FP16ALT_S; - - - preprocess_mvp preprocess_U0 - ( - .Clk_CI (Clk_CI ), - .Rst_RBI (Rst_RBI ), - .Div_start_SI (Div_start_SI ), - .Sqrt_start_SI (Sqrt_start_SI ), - .Ready_SI (Ready_SO ), - .Operand_a_DI (Operand_a_DI ), - .Operand_b_DI (Operand_b_DI ), - .RM_SI (RM_SI ), - .Format_sel_SI (Format_sel_SI ), - .Start_SO (Start_S ), - .Exp_a_DO_norm (Exp_a_D ), - .Exp_b_DO_norm (Exp_b_D ), - .Mant_a_DO_norm (Mant_a_D ), - .Mant_b_DO_norm (Mant_b_D ), - .RM_dly_SO (RM_dly_S ), - .Sign_z_DO (Sign_z_D ), - .Inf_a_SO (Inf_a_S ), - .Inf_b_SO (Inf_b_S ), - .Zero_a_SO (Zero_a_S ), - .Zero_b_SO (Zero_b_S ), - .NaN_a_SO (NaN_a_S ), - .NaN_b_SO (NaN_b_S ), - .SNaN_SO (SNaN_S ), - .Special_case_SBO (Special_case_SB ), - .Special_case_dly_SBO (Special_case_dly_SB) - ); - - nrbd_nrsc_mvp nrbd_nrsc_U0 - ( - .Clk_CI (Clk_CI ), - .Rst_RBI (Rst_RBI ), - .Div_start_SI (Div_start_SI ) , - .Sqrt_start_SI (Sqrt_start_SI ), - .Start_SI (Start_S ), - .Kill_SI (Kill_SI ), - .Special_case_SBI (Special_case_SB ), - .Special_case_dly_SBI (Special_case_dly_SB), - .Div_enable_SO (Div_enable_S ), - .Sqrt_enable_SO (Sqrt_enable_S ), - .Precision_ctl_SI (Precision_ctl_SI ), - .Format_sel_SI (Format_sel_SI ), - .Exp_a_DI (Exp_a_D ), - .Exp_b_DI (Exp_b_D ), - .Mant_a_DI (Mant_a_D ), - .Mant_b_DI (Mant_b_D ), - .Full_precision_SO (Full_precision_S ), - .FP32_SO (FP32_S ), - .FP64_SO (FP64_S ), - .FP16_SO (FP16_S ), - .FP16ALT_SO (FP16ALT_S ), - .Ready_SO (Ready_SO ), - .Done_SO (Done_SO ), - .Exp_z_DO (Exp_z_D ), - .Mant_z_DO (Mant_z_D ) - ); - - - norm_div_sqrt_mvp fpu_norm_U0 - ( - .Mant_in_DI (Mant_z_D ), - .Exp_in_DI (Exp_z_D ), - .Sign_in_DI (Sign_z_D ), - .Div_enable_SI (Div_enable_S ), - .Sqrt_enable_SI (Sqrt_enable_S ), - .Inf_a_SI (Inf_a_S ), - .Inf_b_SI (Inf_b_S ), - .Zero_a_SI (Zero_a_S ), - .Zero_b_SI (Zero_b_S ), - .NaN_a_SI (NaN_a_S ), - .NaN_b_SI (NaN_b_S ), - .SNaN_SI (SNaN_S ), - .RM_SI (RM_dly_S ), - .Full_precision_SI (Full_precision_S ), - .FP32_SI (FP32_S ), - .FP64_SI (FP64_S ), - .FP16_SI (FP16_S ), - .FP16ALT_SI (FP16ALT_S ), - .Result_DO (Result_DO ), - .Fflags_SO (Fflags_SO ) //{NV,DZ,OF,UF,NX} - ); - -endmodule diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv deleted file mode 100644 index 0c645e6eb..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv +++ /dev/null @@ -1,61 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 12/01/2017 // -// Design Name: FPU // -// Module Name: iteration_div_sqrt_mvp // -// Project Name: Private FPU // -// Language: SystemVerilog // -// // -// Description: iteration unit for div and sqrt // -// // -// // -// Revision: 03/14/2018 // -// For div_sqrt_mvp // -//////////////////////////////////////////////////////////////////////////////// - -module iteration_div_sqrt_mvp -#( - parameter WIDTH=25 -) - (//Input - - input logic [WIDTH-1:0] A_DI, - input logic [WIDTH-1:0] B_DI, - input logic Div_enable_SI, - input logic Div_start_dly_SI, - input logic Sqrt_enable_SI, - input logic [1:0] D_DI, - - output logic [1:0] D_DO, - output logic [WIDTH-1:0] Sum_DO, - output logic Carry_out_DO - ); - - logic D_carry_D; - logic Sqrt_cin_D; - logic Cin_D; - - assign D_DO[0]=~D_DI[0]; - assign D_DO[1]=~(D_DI[1] ^ D_DI[0]); - assign D_carry_D=D_DI[1] | D_DI[0]; - assign Sqrt_cin_D=Sqrt_enable_SI&&D_carry_D; - assign Cin_D=Div_enable_SI?1'b0:Sqrt_cin_D; - assign {Carry_out_DO,Sum_DO}=A_DI+B_DI+Cin_D; - -endmodule diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv deleted file mode 100644 index 590abe969..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv +++ /dev/null @@ -1,470 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 09/03/2018 // -// Design Name: FPU // -// Module Name: norm_div_sqrt_mvp.sv // -// Project Name: // -// Language: SystemVerilog // -// // -// Description: Floating point Normalizer/Rounding unit // -// Since this module is design as a combinatinal logic, it can// -// be added arbinary register stages for different frequency // -// in the wrapper module. // -// // -// // -// // -// Revision Date: 12/04/2018 // -// Lei Li // -// To address some requirements by Stefan // -// // -// // -// // -// // -// // -// // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module norm_div_sqrt_mvp - (//Inputs - input logic [C_MANT_FP64+4:0] Mant_in_DI, // Include the needed 4-bit for rounding and hidden bit - input logic signed [C_EXP_FP64+1:0] Exp_in_DI, - input logic Sign_in_DI, - input logic Div_enable_SI, - input logic Sqrt_enable_SI, - input logic Inf_a_SI, - input logic Inf_b_SI, - input logic Zero_a_SI, - input logic Zero_b_SI, - input logic NaN_a_SI, - input logic NaN_b_SI, - input logic SNaN_SI, - input logic [C_RM-1:0] RM_SI, - input logic Full_precision_SI, - input logic FP32_SI, - input logic FP64_SI, - input logic FP16_SI, - input logic FP16ALT_SI, - //Outputs - output logic [C_EXP_FP64+C_MANT_FP64:0] Result_DO, - output logic [4:0] Fflags_SO //{NV,DZ,OF,UF,NX} - ); - - - logic Sign_res_D; - - logic NV_OP_S; - logic Exp_OF_S; - logic Exp_UF_S; - logic Div_Zero_S; - logic In_Exact_S; - - ///////////////////////////////////////////////////////////////////////////// - // Normalization // - ///////////////////////////////////////////////////////////////////////////// - logic [C_MANT_FP64:0] Mant_res_norm_D; - logic [C_EXP_FP64-1:0] Exp_res_norm_D; - - ///////////////////////////////////////////////////////////////////////////// - // Right shift operations for negtive exponents // - ///////////////////////////////////////////////////////////////////////////// - - logic [C_EXP_FP64+1:0] Exp_Max_RS_FP64_D; - logic [C_EXP_FP32+1:0] Exp_Max_RS_FP32_D; - logic [C_EXP_FP16+1:0] Exp_Max_RS_FP16_D; - logic [C_EXP_FP16ALT+1:0] Exp_Max_RS_FP16ALT_D; - // - assign Exp_Max_RS_FP64_D=Exp_in_DI[C_EXP_FP64:0]+C_MANT_FP64+1; // to check exponent after (C_MANT_FP64+1)-bit >> when Exp_in_DI is negative - assign Exp_Max_RS_FP32_D=Exp_in_DI[C_EXP_FP32:0]+C_MANT_FP32+1; // to check exponent after (C_MANT_FP32+1)-bit >> when Exp_in_DI is negative - assign Exp_Max_RS_FP16_D=Exp_in_DI[C_EXP_FP16:0]+C_MANT_FP16+1; // to check exponent after (C_MANT_FP16+1)-bit >> when Exp_in_DI is negative - assign Exp_Max_RS_FP16ALT_D=Exp_in_DI[C_EXP_FP16ALT:0]+C_MANT_FP16ALT+1; // to check exponent after (C_MANT_FP16ALT+1)-bit >> when Exp_in_DI is negative - logic [C_EXP_FP64+1:0] Num_RS_D; - assign Num_RS_D=~Exp_in_DI+1+1; // How many right shifts(RS) are needed to generate a denormal number? >> is need only when Exp_in_DI is negative - logic [C_MANT_FP64:0] Mant_RS_D; - logic [C_MANT_FP64+4:0] Mant_forsticky_D; - assign {Mant_RS_D,Mant_forsticky_D} ={Mant_in_DI,{(C_MANT_FP64+1){1'b0}} } >>(Num_RS_D); // -// - logic [C_EXP_FP64+1:0] Exp_subOne_D; - assign Exp_subOne_D = Exp_in_DI -1; - - //normalization - logic [1:0] Mant_lower_D; - logic Mant_sticky_bit_D; - logic [C_MANT_FP64+4:0] Mant_forround_D; - - always_comb - begin - - if(NaN_a_SI) // if a is NaN, return NaN - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = SNaN_SI; - end - - else if(NaN_b_SI) //if b is NaN, return NaN - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = SNaN_SI; - end - - else if(Inf_a_SI) - begin - if(Div_enable_SI&&Inf_b_SI) //Inf/Inf, retrurn NaN - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = 1'b1; - end - else if (Sqrt_enable_SI && Sign_in_DI) begin // catch sqrt(-inf) - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = 1'b1; - end else begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b1; - Exp_UF_S=1'b0; - Mant_res_norm_D= '0; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - end - - else if(Div_enable_SI&&Inf_b_SI) - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b1; - Exp_UF_S=1'b0; - Mant_res_norm_D= '0; - Exp_res_norm_D='0; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else if(Zero_a_SI) - begin - if(Div_enable_SI&&Zero_b_SI) - begin - Div_Zero_S=1'b1; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = 1'b1; - end - else - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D='0; - Exp_res_norm_D='0; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - end - - else if(Div_enable_SI&&(Zero_b_SI)) //div Zero - begin - Div_Zero_S=1'b1; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D='0; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else if(Sign_in_DI&&Sqrt_enable_SI) //sqrt(-a) - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = 1'b1; - end - - else if((Exp_in_DI[C_EXP_FP64:0]=='0)) - begin - if(Mant_in_DI!='0) //Exp=0, Mant!=0, it is denormal - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b1; - Mant_res_norm_D={1'b0,Mant_in_DI[C_MANT_FP64+4:5]}; - Exp_res_norm_D='0; - Mant_forround_D={Mant_in_DI[4:0],{(C_MANT_FP64){1'b0}} }; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - else // Zero - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D='0; - Exp_res_norm_D='0; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - end - - else if((Exp_in_DI[C_EXP_FP64:0]==C_EXP_ONE_FP64)&&(~Mant_in_DI[C_MANT_FP64+4])) //denormal - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b1; - Mant_res_norm_D=Mant_in_DI[C_MANT_FP64+4:4]; - Exp_res_norm_D='0; - Mant_forround_D={Mant_in_DI[3:0],{(C_MANT_FP64+1){1'b0}}}; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else if(Exp_in_DI[C_EXP_FP64+1]) //minus //consider format - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b1; - Mant_res_norm_D={Mant_RS_D[C_MANT_FP64:0]}; - Exp_res_norm_D='0; - Mant_forround_D={Mant_forsticky_D[C_MANT_FP64+4:0]}; //?? - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else if( (Exp_in_DI[C_EXP_FP32]&&FP32_SI) | (Exp_in_DI[C_EXP_FP64]&&FP64_SI) | (Exp_in_DI[C_EXP_FP16]&&FP16_SI) | (Exp_in_DI[C_EXP_FP16ALT]&&FP16ALT_SI) ) //OF - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b1; - Exp_UF_S=1'b0; - Mant_res_norm_D='0; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else if( ((Exp_in_DI[C_EXP_FP32-1:0]=='1)&&FP32_SI) | ((Exp_in_DI[C_EXP_FP64-1:0]=='1)&&FP64_SI) | ((Exp_in_DI[C_EXP_FP16-1:0]=='1)&&FP16_SI) | ((Exp_in_DI[C_EXP_FP16ALT-1:0]=='1)&&FP16ALT_SI) )//255 - begin - if(~Mant_in_DI[C_MANT_FP64+4]) // MSB=0 - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D=Mant_in_DI[C_MANT_FP64+3:3]; - Exp_res_norm_D=Exp_subOne_D; - Mant_forround_D={Mant_in_DI[2:0],{(C_MANT_FP64+2){1'b0}}}; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - else if(Mant_in_DI!='0) //NaN - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b1; - Exp_UF_S=1'b0; - Mant_res_norm_D= '0; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - else //infinity - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b1; - Exp_UF_S=1'b0; - Mant_res_norm_D= '0; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - end - - else if(Mant_in_DI[C_MANT_FP64+4]) //normal numbers with 1.XXX - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D= Mant_in_DI[C_MANT_FP64+4:4]; - Exp_res_norm_D=Exp_in_DI[C_EXP_FP64-1:0]; - Mant_forround_D={Mant_in_DI[3:0],{(C_MANT_FP64+1){1'b0}}}; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else //normal numbers with 0.1XX - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D=Mant_in_DI[C_MANT_FP64+3:3]; - Exp_res_norm_D=Exp_subOne_D; - Mant_forround_D={Mant_in_DI[2:0],{(C_MANT_FP64+2){1'b0}}}; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - end - - ///////////////////////////////////////////////////////////////////////////// - // Rounding enable only for full precision (Full_precision_SI==1'b1) // - ///////////////////////////////////////////////////////////////////////////// - - logic [C_MANT_FP64:0] Mant_upper_D; - logic [C_MANT_FP64+1:0] Mant_upperRounded_D; - logic Mant_roundUp_S; - logic Mant_rounded_S; - - always_comb //determine which bits for Mant_lower_D and Mant_sticky_bit_D - begin - if(FP32_SI) - begin - Mant_upper_D = {Mant_res_norm_D[C_MANT_FP64:C_MANT_FP64-C_MANT_FP32], {(C_MANT_FP64-C_MANT_FP32){1'b0}} }; - Mant_lower_D = Mant_res_norm_D[C_MANT_FP64-C_MANT_FP32-1:C_MANT_FP64-C_MANT_FP32-2]; - Mant_sticky_bit_D = | Mant_res_norm_D[C_MANT_FP64-C_MANT_FP32-3:0]; - end - else if(FP64_SI) - begin - Mant_upper_D = Mant_res_norm_D[C_MANT_FP64:0]; - Mant_lower_D = Mant_forround_D[C_MANT_FP64+4:C_MANT_FP64+3]; - Mant_sticky_bit_D = | Mant_forround_D[C_MANT_FP64+3:0]; - end - else if(FP16_SI) - begin - Mant_upper_D = {Mant_res_norm_D[C_MANT_FP64:C_MANT_FP64-C_MANT_FP16], {(C_MANT_FP64-C_MANT_FP16){1'b0}} }; - Mant_lower_D = Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16-1:C_MANT_FP64-C_MANT_FP16-2]; - Mant_sticky_bit_D = | Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16-3:30]; - end - else //FP16ALT - begin - Mant_upper_D = {Mant_res_norm_D[C_MANT_FP64:C_MANT_FP64-C_MANT_FP16ALT], {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; - Mant_lower_D = Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16ALT-1:C_MANT_FP64-C_MANT_FP16ALT-2]; - Mant_sticky_bit_D = | Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16ALT-3:30]; - end - end - - assign Mant_rounded_S = (|(Mant_lower_D))| Mant_sticky_bit_D; - - - - - always_comb //determine whether to round up or not - begin - Mant_roundUp_S = 1'b0; - case (RM_SI) - C_RM_NEAREST : - Mant_roundUp_S = Mant_lower_D[1] && ((Mant_lower_D[0] | Mant_sticky_bit_D )| ( (FP32_SI&&Mant_upper_D[C_MANT_FP64-C_MANT_FP32]) | (FP64_SI&&Mant_upper_D[0]) | (FP16_SI&&Mant_upper_D[C_MANT_FP64-C_MANT_FP16]) | (FP16ALT_SI&&Mant_upper_D[C_MANT_FP64-C_MANT_FP16ALT]) ) ); - C_RM_TRUNC : - Mant_roundUp_S = 0; - C_RM_PLUSINF : - Mant_roundUp_S = Mant_rounded_S & ~Sign_in_DI; - C_RM_MINUSINF: - Mant_roundUp_S = Mant_rounded_S & Sign_in_DI; - default : - Mant_roundUp_S = 0; - endcase // case (RM_DI) - end // always_comb begin - - logic Mant_renorm_S; - logic [C_MANT_FP64:0] Mant_roundUp_Vector_S; // for all the formats - - assign Mant_roundUp_Vector_S={7'h0,(FP16ALT_SI&&Mant_roundUp_S),2'h0,(FP16_SI&&Mant_roundUp_S),12'h0,(FP32_SI&&Mant_roundUp_S),28'h0,(FP64_SI&&Mant_roundUp_S)}; - - - assign Mant_upperRounded_D = Mant_upper_D + Mant_roundUp_Vector_S; - assign Mant_renorm_S = Mant_upperRounded_D[C_MANT_FP64+1]; - - ///////////////////////////////////////////////////////////////////////////// - // Renormalization for Rounding // - ///////////////////////////////////////////////////////////////////////////// - logic [C_MANT_FP64-1:0] Mant_res_round_D; - logic [C_EXP_FP64-1:0] Exp_res_round_D; - - - assign Mant_res_round_D = (Mant_renorm_S)?Mant_upperRounded_D[C_MANT_FP64:1]:Mant_upperRounded_D[C_MANT_FP64-1:0]; // including the process of the hidden bit - assign Exp_res_round_D = Exp_res_norm_D+Mant_renorm_S; - - ///////////////////////////////////////////////////////////////////////////// - // Output Assignments // - ///////////////////////////////////////////////////////////////////////////// - logic [C_MANT_FP64-1:0] Mant_before_format_ctl_D; - logic [C_EXP_FP64-1:0] Exp_before_format_ctl_D; - assign Mant_before_format_ctl_D = Full_precision_SI ? Mant_res_round_D : Mant_res_norm_D; - assign Exp_before_format_ctl_D = Full_precision_SI ? Exp_res_round_D : Exp_res_norm_D; - - always_comb //NaN Boxing - begin // - if(FP32_SI) - begin - Result_DO ={32'hffff_ffff,Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP32-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:C_MANT_FP64-C_MANT_FP32]}; - end - else if(FP64_SI) - begin - Result_DO ={Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP64-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:0]}; - end - else if(FP16_SI) - begin - Result_DO ={48'hffff_ffff_ffff,Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP16-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:C_MANT_FP64-C_MANT_FP16]}; - end - else - begin - Result_DO ={48'hffff_ffff_ffff,Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP16ALT-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:C_MANT_FP64-C_MANT_FP16ALT]}; - end - end - -assign In_Exact_S = (~Full_precision_SI) | Mant_rounded_S; -assign Fflags_SO = {NV_OP_S,Div_Zero_S,Exp_OF_S,Exp_UF_S,In_Exact_S}; //{NV,DZ,OF,UF,NX} - -endmodule // norm_div_sqrt_mvp diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv deleted file mode 100644 index 62bd147f6..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv +++ /dev/null @@ -1,104 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 10/04/2018 // -// Design Name: FPU // -// Module Name: nrbd_nrsc_mvp.sv // -// Project Name: Private FPU // -// Language: SystemVerilog // -// // -// Description: non restroring binary divisior/ square root // -// // -// Revision Date: 12/04/2018 // -// Lei Li // -// To address some requirements by Stefan and add low power // -// control for special cases // -// // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module nrbd_nrsc_mvp - - (//Input - input logic Clk_CI, - input logic Rst_RBI, - input logic Div_start_SI, - input logic Sqrt_start_SI, - input logic Start_SI, - input logic Kill_SI, - input logic Special_case_SBI, - input logic Special_case_dly_SBI, - input logic [C_PC-1:0] Precision_ctl_SI, - input logic [1:0] Format_sel_SI, - input logic [C_MANT_FP64:0] Mant_a_DI, - input logic [C_MANT_FP64:0] Mant_b_DI, - input logic [C_EXP_FP64:0] Exp_a_DI, - input logic [C_EXP_FP64:0] Exp_b_DI, - //output - output logic Div_enable_SO, - output logic Sqrt_enable_SO, - - output logic Full_precision_SO, - output logic FP32_SO, - output logic FP64_SO, - output logic FP16_SO, - output logic FP16ALT_SO, - output logic Ready_SO, - output logic Done_SO, - output logic [C_MANT_FP64+4:0] Mant_z_DO, - output logic [C_EXP_FP64+1:0] Exp_z_DO - ); - - - logic Div_start_dly_S,Sqrt_start_dly_S; - - -control_mvp control_U0 -( .Clk_CI (Clk_CI ), - .Rst_RBI (Rst_RBI ), - .Div_start_SI (Div_start_SI ), - .Sqrt_start_SI (Sqrt_start_SI ), - .Start_SI (Start_SI ), - .Kill_SI (Kill_SI ), - .Special_case_SBI (Special_case_SBI ), - .Special_case_dly_SBI (Special_case_dly_SBI ), - .Precision_ctl_SI (Precision_ctl_SI ), - .Format_sel_SI (Format_sel_SI ), - .Numerator_DI (Mant_a_DI ), - .Exp_num_DI (Exp_a_DI ), - .Denominator_DI (Mant_b_DI ), - .Exp_den_DI (Exp_b_DI ), - .Div_start_dly_SO (Div_start_dly_S ), - .Sqrt_start_dly_SO (Sqrt_start_dly_S ), - .Div_enable_SO (Div_enable_SO ), - .Sqrt_enable_SO (Sqrt_enable_SO ), - .Full_precision_SO (Full_precision_SO ), - .FP32_SO (FP32_SO ), - .FP64_SO (FP64_SO ), - .FP16_SO (FP16_SO ), - .FP16ALT_SO (FP16ALT_SO ), - .Ready_SO (Ready_SO ), - .Done_SO (Done_SO ), - .Mant_result_prenorm_DO (Mant_z_DO ), - .Exp_result_prenorm_DO (Exp_z_DO ) -); - - - -endmodule diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv deleted file mode 100644 index 9e0d25f38..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv +++ /dev/null @@ -1,425 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li //lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 01/03/2018 // -// Design Name: FPU // -// Module Name: preprocess_mvp.sv // -// Project Name: Private FPU // -// Language: SystemVerilog // -// // -// Description: decode and data preparation // -// // -// Revision Date: 12/04/2018 // -// Lei Li // -// To address some requirements by Stefan and add low power // -// control for special cases // -// // -// // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module preprocess_mvp - ( - input logic Clk_CI, - input logic Rst_RBI, - input logic Div_start_SI, - input logic Sqrt_start_SI, - input logic Ready_SI, - //Input Operands - input logic [C_OP_FP64-1:0] Operand_a_DI, - input logic [C_OP_FP64-1:0] Operand_b_DI, - input logic [C_RM-1:0] RM_SI, //Rounding Mode - input logic [C_FS-1:0] Format_sel_SI, // Format Selection - - // to control - output logic Start_SO, - output logic [C_EXP_FP64:0] Exp_a_DO_norm, - output logic [C_EXP_FP64:0] Exp_b_DO_norm, - output logic [C_MANT_FP64:0] Mant_a_DO_norm, - output logic [C_MANT_FP64:0] Mant_b_DO_norm, - - output logic [C_RM-1:0] RM_dly_SO, - - output logic Sign_z_DO, - output logic Inf_a_SO, - output logic Inf_b_SO, - output logic Zero_a_SO, - output logic Zero_b_SO, - output logic NaN_a_SO, - output logic NaN_b_SO, - output logic SNaN_SO, - output logic Special_case_SBO, - output logic Special_case_dly_SBO - ); - - //Hidden Bits - logic Hb_a_D; - logic Hb_b_D; - - logic [C_EXP_FP64-1:0] Exp_a_D; - logic [C_EXP_FP64-1:0] Exp_b_D; - logic [C_MANT_FP64-1:0] Mant_a_NonH_D; - logic [C_MANT_FP64-1:0] Mant_b_NonH_D; - logic [C_MANT_FP64:0] Mant_a_D; - logic [C_MANT_FP64:0] Mant_b_D; - - ///////////////////////////////////////////////////////////////////////////// - // Disassemble operands - ///////////////////////////////////////////////////////////////////////////// - logic Sign_a_D,Sign_b_D; - logic Start_S; - - always_comb - begin - case(Format_sel_SI) - 2'b00: - begin - Sign_a_D = Operand_a_DI[C_OP_FP32-1]; - Sign_b_D = Operand_b_DI[C_OP_FP32-1]; - Exp_a_D = {3'h0, Operand_a_DI[C_OP_FP32-2:C_MANT_FP32]}; - Exp_b_D = {3'h0, Operand_b_DI[C_OP_FP32-2:C_MANT_FP32]}; - Mant_a_NonH_D = {Operand_a_DI[C_MANT_FP32-1:0],29'h0}; - Mant_b_NonH_D = {Operand_b_DI[C_MANT_FP32-1:0],29'h0}; - end - 2'b01: - begin - Sign_a_D = Operand_a_DI[C_OP_FP64-1]; - Sign_b_D = Operand_b_DI[C_OP_FP64-1]; - Exp_a_D = Operand_a_DI[C_OP_FP64-2:C_MANT_FP64]; - Exp_b_D = Operand_b_DI[C_OP_FP64-2:C_MANT_FP64]; - Mant_a_NonH_D = Operand_a_DI[C_MANT_FP64-1:0]; - Mant_b_NonH_D = Operand_b_DI[C_MANT_FP64-1:0]; - end - 2'b10: - begin - Sign_a_D = Operand_a_DI[C_OP_FP16-1]; - Sign_b_D = Operand_b_DI[C_OP_FP16-1]; - Exp_a_D = {6'h00, Operand_a_DI[C_OP_FP16-2:C_MANT_FP16]}; - Exp_b_D = {6'h00, Operand_b_DI[C_OP_FP16-2:C_MANT_FP16]}; - Mant_a_NonH_D = {Operand_a_DI[C_MANT_FP16-1:0],42'h0}; - Mant_b_NonH_D = {Operand_b_DI[C_MANT_FP16-1:0],42'h0}; - end - 2'b11: - begin - Sign_a_D = Operand_a_DI[C_OP_FP16ALT-1]; - Sign_b_D = Operand_b_DI[C_OP_FP16ALT-1]; - Exp_a_D = {3'h0, Operand_a_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT]}; - Exp_b_D = {3'h0, Operand_b_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT]}; - Mant_a_NonH_D = {Operand_a_DI[C_MANT_FP16ALT-1:0],45'h0}; - Mant_b_NonH_D = {Operand_b_DI[C_MANT_FP16ALT-1:0],45'h0}; - end - endcase - end - - - assign Mant_a_D = {Hb_a_D,Mant_a_NonH_D}; - assign Mant_b_D = {Hb_b_D,Mant_b_NonH_D}; - - assign Hb_a_D = | Exp_a_D; // hidden bit - assign Hb_b_D = | Exp_b_D; // hidden bit - - assign Start_S= Div_start_SI | Sqrt_start_SI; - - - - ///////////////////////////////////////////////////////////////////////////// - // preliminary checks for infinite/zero/NaN operands // - ///////////////////////////////////////////////////////////////////////////// - - logic Mant_a_prenorm_zero_S; - logic Mant_b_prenorm_zero_S; - - logic Exp_a_prenorm_zero_S; - logic Exp_b_prenorm_zero_S; - assign Exp_a_prenorm_zero_S = ~Hb_a_D; - assign Exp_b_prenorm_zero_S = ~Hb_b_D; - - logic Exp_a_prenorm_Inf_NaN_S; - logic Exp_b_prenorm_Inf_NaN_S; - - logic Mant_a_prenorm_QNaN_S; - logic Mant_a_prenorm_SNaN_S; - logic Mant_b_prenorm_QNaN_S; - logic Mant_b_prenorm_SNaN_S; - - assign Mant_a_prenorm_QNaN_S=Mant_a_NonH_D[C_MANT_FP64-1]&&(~(|Mant_a_NonH_D[C_MANT_FP64-2:0])); - assign Mant_a_prenorm_SNaN_S=(~Mant_a_NonH_D[C_MANT_FP64-1])&&((|Mant_a_NonH_D[C_MANT_FP64-2:0])); - assign Mant_b_prenorm_QNaN_S=Mant_b_NonH_D[C_MANT_FP64-1]&&(~(|Mant_b_NonH_D[C_MANT_FP64-2:0])); - assign Mant_b_prenorm_SNaN_S=(~Mant_b_NonH_D[C_MANT_FP64-1])&&((|Mant_b_NonH_D[C_MANT_FP64-2:0])); - - always_comb - begin - case(Format_sel_SI) - 2'b00: - begin - Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP32-1:0] == C_MANT_ZERO_FP32); - Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP32-1:0] == C_MANT_ZERO_FP32); - Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP32-2:C_MANT_FP32] == C_EXP_INF_FP32); - Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP32-2:C_MANT_FP32] == C_EXP_INF_FP32); - end - 2'b01: - begin - Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP64-1:0] == C_MANT_ZERO_FP64); - Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP64-1:0] == C_MANT_ZERO_FP64); - Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP64-2:C_MANT_FP64] == C_EXP_INF_FP64); - Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP64-2:C_MANT_FP64] == C_EXP_INF_FP64); - end - 2'b10: - begin - Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP16-1:0] == C_MANT_ZERO_FP16); - Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP16-1:0] == C_MANT_ZERO_FP16); - Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP16-2:C_MANT_FP16] == C_EXP_INF_FP16); - Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP16-2:C_MANT_FP16] == C_EXP_INF_FP16); - end - 2'b11: - begin - Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP16ALT-1:0] == C_MANT_ZERO_FP16ALT); - Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP16ALT-1:0] == C_MANT_ZERO_FP16ALT); - Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT] == C_EXP_INF_FP16ALT); - Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT] == C_EXP_INF_FP16ALT); - end - endcase - end - - - - - logic Zero_a_SN,Zero_a_SP; - logic Zero_b_SN,Zero_b_SP; - logic Inf_a_SN,Inf_a_SP; - logic Inf_b_SN,Inf_b_SP; - logic NaN_a_SN,NaN_a_SP; - logic NaN_b_SN,NaN_b_SP; - logic SNaN_SN,SNaN_SP; - - assign Zero_a_SN = (Start_S&&Ready_SI)?(Exp_a_prenorm_zero_S&&Mant_a_prenorm_zero_S):Zero_a_SP; - assign Zero_b_SN = (Start_S&&Ready_SI)?(Exp_b_prenorm_zero_S&&Mant_b_prenorm_zero_S):Zero_b_SP; - assign Inf_a_SN = (Start_S&&Ready_SI)?(Exp_a_prenorm_Inf_NaN_S&&Mant_a_prenorm_zero_S):Inf_a_SP; - assign Inf_b_SN = (Start_S&&Ready_SI)?(Exp_b_prenorm_Inf_NaN_S&&Mant_b_prenorm_zero_S):Inf_b_SP; - assign NaN_a_SN = (Start_S&&Ready_SI)?(Exp_a_prenorm_Inf_NaN_S&&(~Mant_a_prenorm_zero_S)):NaN_a_SP; - assign NaN_b_SN = (Start_S&&Ready_SI)?(Exp_b_prenorm_Inf_NaN_S&&(~Mant_b_prenorm_zero_S)):NaN_b_SP; - assign SNaN_SN = (Start_S&&Ready_SI) ? ((Mant_a_prenorm_SNaN_S&&NaN_a_SN) | (Mant_b_prenorm_SNaN_S&&NaN_b_SN)) : SNaN_SP; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Zero_a_SP <='0; - Zero_b_SP <='0; - Inf_a_SP <='0; - Inf_b_SP <='0; - NaN_a_SP <='0; - NaN_b_SP <='0; - SNaN_SP <= '0; - end - else - begin - Inf_a_SP <=Inf_a_SN; - Inf_b_SP <=Inf_b_SN; - Zero_a_SP <=Zero_a_SN; - Zero_b_SP <=Zero_b_SN; - NaN_a_SP <=NaN_a_SN; - NaN_b_SP <=NaN_b_SN; - SNaN_SP <= SNaN_SN; - end - end - - ///////////////////////////////////////////////////////////////////////////// - // Low power control - ///////////////////////////////////////////////////////////////////////////// - - assign Special_case_SBO=(~{(Div_start_SI)?(Zero_a_SN | Zero_b_SN | Inf_a_SN | Inf_b_SN | NaN_a_SN | NaN_b_SN): (Zero_a_SN | Inf_a_SN | NaN_a_SN | Sign_a_D) })&&(Start_S&&Ready_SI); - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Special_case_dly_SBO <= '0; - end - else if((Start_S&&Ready_SI)) - begin - Special_case_dly_SBO <= Special_case_SBO; - end - else if(Special_case_dly_SBO) - begin - Special_case_dly_SBO <= 1'b1; - end - else - begin - Special_case_dly_SBO <= '0; - end - end - - ///////////////////////////////////////////////////////////////////////////// - // Delay sign for normalization and round // - ///////////////////////////////////////////////////////////////////////////// - - logic Sign_z_DN; - logic Sign_z_DP; - - always_comb - begin - if(Div_start_SI&&Ready_SI) - Sign_z_DN = Sign_a_D ^ Sign_b_D; - else if(Sqrt_start_SI&&Ready_SI) - Sign_z_DN = Sign_a_D; - else - Sign_z_DN = Sign_z_DP; - end - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Sign_z_DP <= '0; - end - else - begin - Sign_z_DP <= Sign_z_DN; - end - end - - logic [C_RM-1:0] RM_DN; - logic [C_RM-1:0] RM_DP; - - always_comb - begin - if(Start_S&&Ready_SI) - RM_DN = RM_SI; - else - RM_DN = RM_DP; - end - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - RM_DP <= '0; - end - else - begin - RM_DP <= RM_DN; - end - end - assign RM_dly_SO = RM_DP; - - logic [5:0] Mant_leadingOne_a, Mant_leadingOne_b; - logic Mant_zero_S_a,Mant_zero_S_b; - - lzc #( - .WIDTH ( C_MANT_FP64+1 ), - .MODE ( 1 ) - ) LOD_Ua ( - .in_i ( Mant_a_D ), - .cnt_o ( Mant_leadingOne_a ), - .empty_o ( Mant_zero_S_a ) - ); - - logic [C_MANT_FP64:0] Mant_a_norm_DN,Mant_a_norm_DP; - - assign Mant_a_norm_DN = ((Start_S&&Ready_SI))?(Mant_a_D<<(Mant_leadingOne_a)):Mant_a_norm_DP; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Mant_a_norm_DP <= '0; - end - else - begin - Mant_a_norm_DP<=Mant_a_norm_DN; - end - end - - logic [C_EXP_FP64:0] Exp_a_norm_DN,Exp_a_norm_DP; - assign Exp_a_norm_DN = ((Start_S&&Ready_SI))?(Exp_a_D-Mant_leadingOne_a+(|Mant_leadingOne_a)):Exp_a_norm_DP; //Covering the process of denormal numbers - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Exp_a_norm_DP <= '0; - end - else - begin - Exp_a_norm_DP<=Exp_a_norm_DN; - end - end - - lzc #( - .WIDTH ( C_MANT_FP64+1 ), - .MODE ( 1 ) - ) LOD_Ub ( - .in_i ( Mant_b_D ), - .cnt_o ( Mant_leadingOne_b ), - .empty_o ( Mant_zero_S_b ) - ); - - - logic [C_MANT_FP64:0] Mant_b_norm_DN,Mant_b_norm_DP; - - assign Mant_b_norm_DN = ((Start_S&&Ready_SI))?(Mant_b_D<<(Mant_leadingOne_b)):Mant_b_norm_DP; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Mant_b_norm_DP <= '0; - end - else - begin - Mant_b_norm_DP<=Mant_b_norm_DN; - end - end - - logic [C_EXP_FP64:0] Exp_b_norm_DN,Exp_b_norm_DP; - assign Exp_b_norm_DN = ((Start_S&&Ready_SI))?(Exp_b_D-Mant_leadingOne_b+(|Mant_leadingOne_b)):Exp_b_norm_DP; //Covering the process of denormal numbers - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Exp_b_norm_DP <= '0; - end - else - begin - Exp_b_norm_DP<=Exp_b_norm_DN; - end - end - - ///////////////////////////////////////////////////////////////////////////// - // Output assignments // - ///////////////////////////////////////////////////////////////////////////// - - assign Start_SO=Start_S; - assign Exp_a_DO_norm=Exp_a_norm_DP; - assign Exp_b_DO_norm=Exp_b_norm_DP; - assign Mant_a_DO_norm=Mant_a_norm_DP; - assign Mant_b_DO_norm=Mant_b_norm_DP; - assign Sign_z_DO=Sign_z_DP; - assign Inf_a_SO=Inf_a_SP; - assign Inf_b_SO=Inf_b_SP; - assign Zero_a_SO=Zero_a_SP; - assign Zero_b_SO=Zero_b_SP; - assign NaN_a_SO=NaN_a_SP; - assign NaN_b_SO=NaN_b_SP; - assign SNaN_SO=SNaN_SP; - -endmodule