diff --git a/lib/cv_dv_utils/python/sim_cmd/README.md b/lib/cv_dv_utils/python/sim_cmd/README.md new file mode 100644 index 0000000000..c26bcd4853 --- /dev/null +++ b/lib/cv_dv_utils/python/sim_cmd/README.md @@ -0,0 +1,17 @@ + + +# SIM CMD +## Introduction +These are python scripts, they allow to compile and run a test. + +# Usage +To compile a code in system verilog +python3 compile.py --yaml simulator_vcs.yaml --outdir out + +To run a test +python3 run_test.py --yaml simulator_vcs.yaml --test_name bursty_test_c + +The templates of yaml files are provided with the script, which can be used to compile and run the test diff --git a/lib/cv_dv_utils/python/sim_cmd/compile.py b/lib/cv_dv_utils/python/sim_cmd/compile.py new file mode 100644 index 0000000000..ea3795d1b2 --- /dev/null +++ b/lib/cv_dv_utils/python/sim_cmd/compile.py @@ -0,0 +1,136 @@ +## ---------------------------------------------------------------------------- +##Copyright 2023 CEA* +##*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +## +##Licensed under the Apache License, Version 2.0 (the "License"); +##you may not use this file except in compliance with the License. +##You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +##Unless required by applicable law or agreed to in writing, software +##distributed under the License is distributed on an "AS IS" BASIS, +##WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +##See the License for the specific language governing permissions and +##limitations under the License. +##[END OF HEADER] +## ---------------------------------------------------------------------------- + + +import argparse +import os +import yaml + +#import compile_cmd as cmp + +parser = argparse.ArgumentParser(description='compile options') +parser.add_argument('--yaml' ,dest='yaml_file', type=str, help='Top YAML with compile and simulation options') +parser.add_argument('--outdir' ,dest='outdir', type=str, help='Logs are directed to outdir: default output') +args = parser.parse_args() + + +def get_cmd(yaml_file, outdir, opt, vopt_option, work): + with open(yaml_file, 'r') as yaml_top: + sim_yaml = yaml.safe_load(yaml_top) + + + for entry in sim_yaml: + if entry['tool'] == "questa": + cmd = "vlog -sv" + vopt_cmd = "vopt" + tool = "questa" + elif entry['tool'] == "vcs": + cmd = "vcs -sverilog" + vopt_cmd = "" + tool = "vcs" + if 'compile' in entry: + comp = entry['compile'] + else: + comp = "" + ######################## + ## get compile options ## + ######################## + if 'work_lib' in comp: + work_lib = comp['work_lib'] + elif work != '': + work_lib = work + else: + work_lib = "work" + ######################## + ## get SV log options ## + ######################## + if 'svlog_option' in comp: + opt += " " + opt += comp["svlog_option"] + else: + opt += " " + ######################## + ## get SV log sources ## + ## *.sv ## + ######################## + if 'svlog_source' in comp: + src_list = comp["svlog_source"] + srcs = src_list.split() + else: + src_list = "" + ######################## + ## get file list ## + ######################## + if 'svlog_flist' in comp: + file_list = comp["svlog_flist"] + files = file_list.split() + else: + file_list = "" + files = "" + ######################## + ## get vopt options ## + ######################## + if 'top_entity' in entry: + top_entity = comp['top_entity'] + else: + top_entity = "top" + if 'vopt_option' in comp: + vopt_option += " " + vopt_option += comp['vopt_option'] + else: + vopt_option += " " + ######################## + ## run other YAML #### + ######################## + if 'yaml_lists' in comp: + yaml_list = comp["yaml_lists"] + yamls = yaml_list.split() + for y in yamls: + get_cmd(y, outdir, opt, vopt_option, work_lib) + + + file_cmd = "" + for f in files: + file_cmd += " -f " + f + + if tool == "questa": + compile_cmd = "{} {} {} {} -work {} -l {}/{}.log".format(cmd, opt, file_cmd, src_list, work_lib, outdir, yaml_file) + vopt_cmd = "{} {} -work {} {} -o opt".format(vopt_cmd, vopt_option, work_lib, top_entity) + elif tool == "vcs": + compile_cmd = "{} {} {} {} -l {}/{}.log".format(cmd, opt, file_cmd, src_list, outdir, yaml_file) + vopt_cmd = "" + + print(compile_cmd) + os.system(compile_cmd) + return vopt_cmd +## get_cmd + +if args.outdir==None: + outdir = "output" +else: + outdir = args.outdir + + +if args.yaml_file == None: + print("Please provide a Top YAML file") +else: + if os.path.isdir("{}".format(outdir)) == False: + os.system("mkdir {}".format(outdir)) + vopt_cmd = get_cmd(args.yaml_file, outdir, '', '', '') + if vopt_cmd != "": + os.system(vopt_cmd) diff --git a/lib/cv_dv_utils/python/sim_cmd/module1_template.yaml b/lib/cv_dv_utils/python/sim_cmd/module1_template.yaml new file mode 100644 index 0000000000..1e4fbc6b01 --- /dev/null +++ b/lib/cv_dv_utils/python/sim_cmd/module1_template.yaml @@ -0,0 +1,26 @@ +## ---------------------------------------------------------------------------- +##Copyright 2023 CEA* +##*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +## +##Licensed under the Apache License, Version 2.0 (the "License"); +##you may not use this file except in compliance with the License. +##You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +##Unless required by applicable law or agreed to in writing, software +##distributed under the License is distributed on an "AS IS" BASIS, +##WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +##See the License for the specific language governing permissions and +##limitations under the License. +##[END OF HEADER] +## ---------------------------------------------------------------------------- + + + + +- tool: questa + compile: + work_lib : "module1 lib name" + svlog_option: "local svlog options" + svlog_flist : "file lists (ex module1_pkg.Flist)" diff --git a/lib/cv_dv_utils/python/sim_cmd/module2_template.yaml b/lib/cv_dv_utils/python/sim_cmd/module2_template.yaml new file mode 100644 index 0000000000..e20f3a52d3 --- /dev/null +++ b/lib/cv_dv_utils/python/sim_cmd/module2_template.yaml @@ -0,0 +1,24 @@ +## ---------------------------------------------------------------------------- +##Copyright 2023 CEA* +##*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +## +##Licensed under the Apache License, Version 2.0 (the "License"); +##you may not use this file except in compliance with the License. +##You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +##Unless required by applicable law or agreed to in writing, software +##distributed under the License is distributed on an "AS IS" BASIS, +##WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +##See the License for the specific language governing permissions and +##limitations under the License. +##[END OF HEADER] +## ---------------------------------------------------------------------------- + + +- tool: questa + compile: + work_lib : "module1 lib name" + svlog_option: "local svlog options" + svlog_flist : "file lists (ex module2_pkg.Flist)" diff --git a/lib/cv_dv_utils/python/sim_cmd/run_test.py b/lib/cv_dv_utils/python/sim_cmd/run_test.py new file mode 100644 index 0000000000..6c3ddebf02 --- /dev/null +++ b/lib/cv_dv_utils/python/sim_cmd/run_test.py @@ -0,0 +1,133 @@ +## ---------------------------------------------------------------------------- +##Copyright 2023 CEA* +##*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +## +##Licensed under the Apache License, Version 2.0 (the "License"); +##you may not use this file except in compliance with the License. +##You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +##Unless required by applicable law or agreed to in writing, software +##distributed under the License is distributed on an "AS IS" BASIS, +##WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +##See the License for the specific language governing permissions and +##limitations under the License. +##[END OF HEADER] +## ---------------------------------------------------------------------------- + + + +import argparse +import os +import yaml + +parser = argparse.ArgumentParser(description='compile and simulation options') +parser.add_argument('--yaml' ,dest='yaml_file', type=str, help='Top YAML with compile and simulation options') +parser.add_argument('--test_name',dest='test_name', type=str, help='Name of the test, default: test_hpdcache_multiple_random_requests') +parser.add_argument('--seed' , dest='seed', type=int, help='random seed ex: 3452363, default 1') +parser.add_argument('--debug' , dest='debug', type=str, help='UVM_LOW/MEDIUM/HIGH/FULL/DEBUG, default LOW') +parser.add_argument('--batch' , dest='batch', type=int, help='1: batch mode, 0:gui default, 1') +parser.add_argument('--stdout' , dest='stdout', type=int, help='1: stdout 0: nostdout') +parser.add_argument('--outdir' , dest='outdir', type=str, help='output dirctory de fault "output"') +## +args = parser.parse_args() + +def run_test(cmd, test_name, seed, debug, batch, stdout, outdir, work_lib, opt, tool): + ## get arguments + if outdir == None: + outdir = "output" + + + if seed == None: + seed = 1 + + if debug == None: + debug = "UVM_LOW" + + if batch == None: + batch = 1 + + if batch == 1: + if tool == "questa": + batchstr = "-c" + else: + batchstr = "" + else: + if tool == "vcs": + batchstr = "-gui" + else: + batchstr = "" + + if stdout == None: + stdout = 1 + + if stdout == 0: + stdoutstr = ">" + else: + stdoutstr = "-l" + + if os.path.isdir("{}".format(outdir)) == False: + os.system("mkdir {}".format(outdir)) + + if test_name == None: + print("ERROR: Please provide a valid test name") + else: + if tool == "questa": + run_cmd = "{} {} -sv_seed {} +UVM_VERBOSITY={} -wlf {}/{}_{}.wlf +UVM_TESTNAME={} {} -lib {} opt {} {}/{}_{}.log".format(cmd, batchstr, seed, debug, outdir, test_name, seed, test_name, opt, work_lib, stdoutstr, outdir, test_name, seed ) + elif tool == "vcs": + run_cmd = "{} {} +ntb_random_seed={} +UVM_VERBOSITY={} -grw {}/{}_{}.wlf +UVM_TESTNAME={} {} {}/{}_{}.log".format(cmd, batchstr, seed, debug, outdir, test_name, seed, test_name, stdoutstr, outdir, test_name, seed ) + + print(run_cmd) + os.system("{}".format(run_cmd)) + +def get_cmd(yaml_file, opt): + with open(yaml_file, 'r') as yaml_top: + sim_yaml = yaml.safe_load(yaml_top) + + + for entry in sim_yaml: + if entry['tool'] == "questa": + cmd = "vsim" + tool = "questa" + if 'sim' in entry: + sim = entry['sim'] + else: + sim = "" + elif entry['tool'] == "vcs": + cmd = "./simv" + tool = "vcs" + if 'sim' in entry: + sim = entry['sim'] + else: + sim = "" + ######################## + ## get compile options ## + ######################## + if tool == "questa": + if 'work_lib' in sim: + work_lib = sim['work_lib'] + elif work != '': + work_lib = work + else: + work_lib = "work" + else: + work_lib = "" + ######################## + ## get SV log options ## + ######################## + if 'sim_option' in sim: + opt += " " + opt += sim["sim_option"] + else: + opt += " " + return cmd, work_lib, opt, tool + +if args.yaml_file == None: + print("Please provide a Top YAML file") +else: + cmd, work_lib, opt, tool = get_cmd(args.yaml_file, '') + run_test(cmd, args.test_name, args.seed, args.debug, args.batch, args.stdout, args.outdir, work_lib, opt, tool ) + + + diff --git a/lib/cv_dv_utils/python/sim_cmd/top_questa_template.yaml b/lib/cv_dv_utils/python/sim_cmd/top_questa_template.yaml new file mode 100644 index 0000000000..9997724583 --- /dev/null +++ b/lib/cv_dv_utils/python/sim_cmd/top_questa_template.yaml @@ -0,0 +1,30 @@ +## ---------------------------------------------------------------------------- +##Copyright 2023 CEA* +##*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +## +##Licensed under the Apache License, Version 2.0 (the "License"); +##you may not use this file except in compliance with the License. +##You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +##Unless required by applicable law or agreed to in writing, software +##distributed under the License is distributed on an "AS IS" BASIS, +##WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +##See the License for the specific language governing permissions and +##limitations under the License. +##[END OF HEADER] +## ---------------------------------------------------------------------------- + + +- tool: questa + compile: + work_lib : "" + svlog_option: "" + svlog_source: "list of sv sources (ex module.sv top.sv)" + yaml_lists : "list of yaml of other modules (ex module1_template.yaml, module2_template.yaml" + vopt_option : "" + top_entity : "" + sim: + work_lib : "" + sim_option : "sim options" diff --git a/lib/cv_dv_utils/python/sim_cmd/top_vcs_template.yaml b/lib/cv_dv_utils/python/sim_cmd/top_vcs_template.yaml new file mode 100644 index 0000000000..f3e052102b --- /dev/null +++ b/lib/cv_dv_utils/python/sim_cmd/top_vcs_template.yaml @@ -0,0 +1,26 @@ +## ---------------------------------------------------------------------------- +##Copyright 2023 CEA* +##*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +## +##Licensed under the Apache License, Version 2.0 (the "License"); +##you may not use this file except in compliance with the License. +##You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +##Unless required by applicable law or agreed to in writing, software +##distributed under the License is distributed on an "AS IS" BASIS, +##WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +##See the License for the specific language governing permissions and +##limitations under the License. +##[END OF HEADER] +## ---------------------------------------------------------------------------- + +- tool: vcs + compile: + svlog_option: "" + svlog_option: "" + svlog_flist : "file list (example $MODULE/module_pkg.Flit)" + top_entity : "" + sim: + sim_option : "sim option" diff --git a/lib/uvm_agents/uvma_axi5/example/README.md b/lib/uvm_agents/uvma_axi5/example/README.md new file mode 100644 index 0000000000..2f38d0ed42 --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/README.md @@ -0,0 +1,18 @@ + + +# AXI master to slave example +## Introduction +In this example, an AXI master agent is connected to an AXI slave agent. This example allows a fast verification of changes made in the AXI agent. + +# Configuration +Please set memory response model response to random 0 + +# Usage +To compile and run using VCS: +python3 $CORE_V_VERIF/lib/cv_dv_utils/python/sim_cmd/compile.py --yaml simulator_vcs.yaml --outdir out +python3 $CORE_V_VERIF/lib/cv_dv_utils/python/sim_cmd/run_test.py --yaml simulator_vcs.yaml --test_name bursty_test_c + +To compile and run using questa +python3 $CORE_V_VERIF/lib/cv_dv_utils/python/sim_cmd/compile.py --yaml simulator_questa.yaml --outdir out +python3 $CORE_V_VERIF/lib/cv_dv_utils/python/sim_cmd/run_test.py --yaml simulator_questa.yaml --test_name bursty_test_c + diff --git a/lib/uvm_agents/uvma_axi5/example/simu/cv_dv_utils.yaml b/lib/uvm_agents/uvma_axi5/example/simu/cv_dv_utils.yaml new file mode 100644 index 0000000000..9a7faac2ff --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/simu/cv_dv_utils.yaml @@ -0,0 +1,26 @@ +## ---------------------------------------------------------------------------- +##Copyright 2023 CEA* +##*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +## +##Licensed under the Apache License, Version 2.0 (the "License"); +##you may not use this file except in compliance with the License. +##You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +##Unless required by applicable law or agreed to in writing, software +##distributed under the License is distributed on an "AS IS" BASIS, +##WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +##See the License for the specific language governing permissions and +##limitations under the License. +##[END OF HEADER] +## ---------------------------------------------------------------------------- + + + + +- tool: questa + compile: + work_lib : "cv_uvm_dv_utils_lib" + svlog_option: "-note 13314" + svlog_flist : "$CORE_V_VERIF/lib/cv_dv_utils/uvm/Files.f" diff --git a/lib/uvm_agents/uvma_axi5/example/simu/run.do b/lib/uvm_agents/uvma_axi5/example/simu/run.do new file mode 100644 index 0000000000..006b8e8766 --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/simu/run.do @@ -0,0 +1,2 @@ +log -r /top/** +run -all diff --git a/lib/uvm_agents/uvma_axi5/example/simu/run_test.do b/lib/uvm_agents/uvma_axi5/example/simu/run_test.do new file mode 100644 index 0000000000..c416cb6fd1 --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/simu/run_test.do @@ -0,0 +1,2 @@ +coverage save -onexit ucdb/cov_test_ucdb +run -all diff --git a/lib/uvm_agents/uvma_axi5/example/simu/simulator_questa.yaml b/lib/uvm_agents/uvma_axi5/example/simu/simulator_questa.yaml new file mode 100644 index 0000000000..bdce56f14b --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/simu/simulator_questa.yaml @@ -0,0 +1,32 @@ +## ---------------------------------------------------------------------------- +##Copyright 2023 CEA* +##*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +## +##Licensed under the Apache License, Version 2.0 (the "License"); +##you may not use this file except in compliance with the License. +##You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +##Unless required by applicable law or agreed to in writing, software +##distributed under the License is distributed on an "AS IS" BASIS, +##WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +##See the License for the specific language governing permissions and +##limitations under the License. +##[END OF HEADER] +## ---------------------------------------------------------------------------- + + + +- tool: questa + compile: + work_lib : "work_top" + svlog_option: "-64 -L cv_uvm_dv_utils_lib -L tb_lib -L /home/cao/mgc/questasim/2023.3/uvm-1.2/ +incdir+/home/cao/mgc/questasim/2023.3/verilog_src/uvm-1.2/src" + svlog_source: "$PROJECT_DIR/sv/dut_env_pkg.sv + $PROJECT_DIR/test/test_pkg.sv $PROJECT_DIR/top/top.sv" + yaml_lists : "cv_dv_utils.yaml uvma_axi5.yaml" + vopt_option : "-assertdebug -L cv_uvm_dv_utils_lib -L tb_lib +acc -note 12003 -suppress 2583 -note 13314" + top_entity : "top" + sim: + work_lib : "work_top" + sim_option : "-L cv_uvm_dv_utils_lib -L tb_lib -note 8233 -note 12003 -c -classdebug -solvefailseverity=4 -solvefaildebug=2 -solvefailtestcase=constraint_failure.txt -l -assertdebug -msgmode both" diff --git a/lib/uvm_agents/uvma_axi5/example/simu/simulator_vcs.yaml b/lib/uvm_agents/uvma_axi5/example/simu/simulator_vcs.yaml new file mode 100644 index 0000000000..e246fb707c --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/simu/simulator_vcs.yaml @@ -0,0 +1,31 @@ +## ---------------------------------------------------------------------------- +##Copyright 2023 CEA* +##*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +## +##Licensed under the Apache License, Version 2.0 (the "License"); +##you may not use this file except in compliance with the License. +##You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +##Unless required by applicable law or agreed to in writing, software +##distributed under the License is distributed on an "AS IS" BASIS, +##WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +##See the License for the specific language governing permissions and +##limitations under the License. +##[END OF HEADER] +## ---------------------------------------------------------------------------- + +- tool: vcs + compile: + svlog_option: "-timescale=1ns/100ps -full64 -ntb_opts uvm-1.2 +incdir+$PROJECT_DIR/sv +incdir+$PROJECT_DIR/test +incdir+$PROJECT_DIR/rtl +incdir+$PROJECT_DIR/top +incdir+$PROJECT_DIR/test" + svlog_source: "$DV_UVMA_AXI_PATH/src/uvma_axi_intf.sv $PROJECT_DIR/sv/dut_env_pkg.sv + $PROJECT_DIR/test/test_pkg.sv $PROJECT_DIR/top/top.sv" + svlog_flist : "$CORE_V_VERIF/lib/cv_dv_utils/uvm/Files.f + $CORE_V_VERIF/lib/uvm_libs/uvml_mem/uvml_mem_pkg.flist + $CORE_V_VERIF/lib/uvm_libs/uvml_trn/uvml_trn_pkg.flist + $CORE_V_VERIF/lib/uvm_libs/uvml_logs/uvml_logs_pkg.flist + $CORE_V_VERIF/lib/uvm_agents/uvma_axi5/src/uvma_axi_pkg.flist" + top_entity : "top" + sim: + sim_option : "-full64 +ntb_random_seed_automatic +ntb_stop_on_constraint_solver_error=0" diff --git a/lib/uvm_agents/uvma_axi5/example/simu/uvma_axi5.yaml b/lib/uvm_agents/uvma_axi5/example/simu/uvma_axi5.yaml new file mode 100644 index 0000000000..aac1989597 --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/simu/uvma_axi5.yaml @@ -0,0 +1,31 @@ +## ---------------------------------------------------------------------------- +##Copyright 2023 CEA* +##*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +## +##Licensed under the Apache License, Version 2.0 (the "License"); +##you may not use this file except in compliance with the License. +##You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +##Unless required by applicable law or agreed to in writing, software +##distributed under the License is distributed on an "AS IS" BASIS, +##WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +##See the License for the specific language governing permissions and +##limitations under the License. +##[END OF HEADER] +## ---------------------------------------------------------------------------- + + + + + +- tool: questa + compile: + work_lib : "tb_lib" + svlog_option: "-suppress 2583" + svlog_source: "$DV_UVMA_AXI_PATH/src/uvma_axi_intf.sv" + svlog_flist : "$CORE_V_VERIF/lib/uvm_libs/uvml_mem/uvml_mem_pkg.flist + $CORE_V_VERIF/lib/uvm_libs/uvml_trn/uvml_trn_pkg.flist + $CORE_V_VERIF/lib/uvm_libs/uvml_logs/uvml_logs_pkg.flist + $CORE_V_VERIF/lib/uvm_agents/uvma_axi5/src/uvma_axi_pkg.flist" diff --git a/lib/uvm_agents/uvma_axi5/example/simu/wave.do b/lib/uvm_agents/uvma_axi5/example/simu/wave.do new file mode 100644 index 0000000000..0f6bcda296 --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/simu/wave.do @@ -0,0 +1,29 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /top/ivif/clk +add wave -noupdate /top/ivif/rst_n +add wave -noupdate /top/ivif/cf +add wave -noupdate /top/ivif/data_in0 +add wave -noupdate /top/ivif/data_in1 +add wave -noupdate /top/ovif/data_out0 +add wave -noupdate /top/ovif/data_out1 +add wave -noupdate /top/ivif/enable +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {15225 ns} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 335 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ns} {10000 ns} +run -all diff --git a/lib/uvm_agents/uvma_axi5/example/sv/bp_virtual_sequence.svh b/lib/uvm_agents/uvma_axi5/example/sv/bp_virtual_sequence.svh new file mode 100644 index 0000000000..35a5c9651a --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/sv/bp_virtual_sequence.svh @@ -0,0 +1,70 @@ +// ---------------------------------------------------------------------------- +//Copyright 2023 CEA* +//*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +// +//Licensed under the Apache License, Version 2.0 (the "License"); +//you may not use this file except in compliance with the License. +//You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +//Unless required by applicable law or agreed to in writing, software +//distributed under the License is distributed on an "AS IS" BASIS, +//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +//See the License for the specific language governing permissions and +//limitations under the License. +//[END OF HEADER] +// ---------------------------------------------------------------------------- +// Description : Virtual sequence: To run back pressure sequences +// +// ---------------------------------------------------------------------------- + +class bp_vseq_base extends uvm_sequence #(uvm_sequence_item); + `uvm_object_utils(bp_vseq_base) + + // Type of the back pressure to be applied + bp_type_t which_bp; + /// Target Agent Sequencers + bp_sequencer bp_sqr; + + /// Constructor + function new (string name = "bp_vseq_base"); + super.new(name); + endfunction: new + +endclass: bp_vseq_base + +///// Virtual Sequence Class +class bp_virtual_sequence extends bp_vseq_base; + `uvm_object_utils(bp_virtual_sequence) + + /// Constructor + function new (string name = "bp_virtual_sequence"); + super.new(name); + endfunction: new + + /// Sequence Body Task + task body(); + + // Following three sequences are defined in bp_seq agent + occassional_bp_sequence o_bp_sequence; + + heavy_bp_sequence h_bp_sequence; + + // occasional backpressure + o_bp_sequence = occassional_bp_sequence::type_id::create("o_bp_seq"); + + // heavy backpressure + h_bp_sequence = heavy_bp_sequence::type_id::create("h_bp_seq"); + + case (which_bp) + OCCASSIONAL_BP: begin + o_bp_sequence.start(bp_sqr); + end + HEAVY_BP: begin + h_bp_sequence.start(bp_sqr); + end + default: `uvm_fatal("VSEQ FATAL", $sformatf("Back pressure %s doesnt exists", which_bp )) + endcase + endtask: body // body +endclass: bp_virtual_sequence diff --git a/lib/uvm_agents/uvma_axi5/example/sv/dut_cfg_c.svh b/lib/uvm_agents/uvma_axi5/example/sv/dut_cfg_c.svh new file mode 100644 index 0000000000..e72f409c7b --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/sv/dut_cfg_c.svh @@ -0,0 +1,55 @@ +// ---------------------------------------------------------------------------- +//Copyright 2023 CEA* +//*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +// +//Licensed under the Apache License, Version 2.0 (the "License"); +//you may not use this file except in compliance with the License. +//You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +//Unless required by applicable law or agreed to in writing, software +//distributed under the License is distributed on an "AS IS" BASIS, +//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +//See the License for the specific language governing permissions and +//limitations under the License. +//[END OF HEADER] +// ---------------------------------------------------------------------------- +// Description : This class (uvm_object) holds an abstract representation of +// the configuration of one Slice in the RWI. +// +// +// +// ---------------------------------------------------------------------------- + +class dut_cfg_c extends uvm_object; + + rand bp_type_t aw_bp ; + rand bp_type_t w_bp ; + rand bp_type_t b_bp ; + rand bp_type_t ar_bp ; + rand bp_type_t r_bp ; + + `uvm_object_utils_begin( dut_cfg_c ) + `uvm_field_enum( bp_type_t, aw_bp , UVM_DEFAULT ) + `uvm_field_enum( bp_type_t, w_bp , UVM_DEFAULT ) + `uvm_field_enum( bp_type_t, b_bp , UVM_DEFAULT ) + `uvm_field_enum( bp_type_t, ar_bp , UVM_DEFAULT ) + `uvm_field_enum( bp_type_t, r_bp , UVM_DEFAULT ) + `uvm_object_utils_end + + // ------------------------------------------------------------------------ + // Constructor + // ------------------------------------------------------------------------ + function new( string name = "dut_cfg_c" ); + super.new(name); + endfunction: new + + constraint aw_bp_data_c { aw_bp dist { OCCASSIONAL_BP := 90, HEAVY_BP := 10};}; + constraint w_bp_data_c { w_bp dist { OCCASSIONAL_BP := 90, HEAVY_BP := 10};}; + constraint b_bp_data_c { b_bp dist { OCCASSIONAL_BP := 90, HEAVY_BP := 10};}; + constraint ar_bp_data_c { ar_bp dist { OCCASSIONAL_BP := 90, HEAVY_BP := 10};}; + constraint r_bp_data_c { r_bp dist { OCCASSIONAL_BP := 90, HEAVY_BP := 10};}; + +endclass : dut_cfg_c + diff --git a/lib/uvm_agents/uvma_axi5/example/sv/dut_env.sv b/lib/uvm_agents/uvma_axi5/example/sv/dut_env.sv new file mode 100644 index 0000000000..b46924743c --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/sv/dut_env.sv @@ -0,0 +1,146 @@ +// ---------------------------------------------------------------------------- +//Copyright 2023 CEA* +//*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +// +//Licensed under the Apache License, Version 2.0 (the "License"); +//you may not use this file except in compliance with the License. +//You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +//Unless required by applicable law or agreed to in writing, software +//distributed under the License is distributed on an "AS IS" BASIS, +//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +//See the License for the specific language governing permissions and +//limitations under the License. +//[END OF HEADER] +// ---------------------------------------------------------------------------- + + +class dut_env extends uvm_env; + + watchdog_c m_wd; + + clock_driver_c cc_clock_driver; + clock_config_c cc_clock_cfg; + + reset_driver_c #(1'b1,10,0) cc_reset_driver; + + uvma_axi_agent_c master; + uvma_axi_agent_c slave; + + uvma_axi_cfg_c master_cfg ; + uvma_axi_cfg_c slave_cfg ; + + uvma_axi_transaction_cfg_c if_item_cfg; + + + + + + bp_agent aw_bp_agent ; + bp_agent w_bp_agent ; + bp_agent b_bp_agent ; + bp_agent ar_bp_agent ; + bp_agent r_bp_agent ; + + bp_virtual_sequence aw_bp_vseq ; + bp_virtual_sequence w_bp_vseq ; + bp_virtual_sequence b_bp_vseq ; + bp_virtual_sequence ar_bp_vseq ; + bp_virtual_sequence r_bp_vseq ; + + dut_cfg_c agent_config; + + `uvm_component_utils(dut_env) + + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + m_wd = watchdog_c::type_id::create("m_wd",this); + + cc_clock_driver = clock_driver_c::type_id::create("cc_clock_driver", this ); + cc_clock_cfg = clock_config_c::type_id::create("cc_clock_cfg", this ); + cc_clock_driver.m_clk_cfg = cc_clock_cfg; + cc_reset_driver = reset_driver_c#( 1'b1,10,0 )::type_id::create("cc_reset_driver", this ); + + aw_bp_agent = bp_agent::type_id::create( "aw_bp_agent" , this ); + w_bp_agent = bp_agent::type_id::create( "w_bp_agent" , this ); + b_bp_agent = bp_agent::type_id::create( "b_bp_agent" , this ); + ar_bp_agent = bp_agent::type_id::create( "ar_bp_agent" , this ); + r_bp_agent = bp_agent::type_id::create( "r_bp_agent" , this ); + + aw_bp_vseq = bp_virtual_sequence::type_id::create( "aw_bp_sequence" , this); + w_bp_vseq = bp_virtual_sequence::type_id::create( "w_bp_sequence" , this); + b_bp_vseq = bp_virtual_sequence::type_id::create( "b_bp_sequence" , this); + ar_bp_vseq = bp_virtual_sequence::type_id::create( "ar_bp_sequence" , this); + r_bp_vseq = bp_virtual_sequence::type_id::create( "r_bp_sequence" , this); + + agent_config = dut_cfg_c::type_id::create("dut_cfg_c"); + + master = axi_superset_agent_c::type_id::create("MASTER_AGENT",this); + slave = axi_superset_agent_c::type_id::create("SLAVE_AGENT",this); + + if_item_cfg = new("TB_TXN_CFG"); + if_item_cfg.set_id_width(16); + if_item_cfg.set_addr_width(32); + if_item_cfg.set_data_width(64); + if_item_cfg.set_user_width(100); + if_item_cfg.set_max_delay_cycles(5); + + master_cfg = axi_superset_config_c::type_id::create("MASTER_CFG", this); + master_cfg.set_axi_version(AXI5); + master_cfg.set_interface_name("AXI_SUPERSET_IF"); + master_cfg.set_is_master_side(1'b1); + master_cfg.set_driver_idle_value_cfg(UNDEFINED); + master_cfg.set_txn_config(if_item_cfg); + master_cfg.set_is_reactive(1'b0); + master_cfg.set_id_management_enable(1'b0); + master_cfg.set_protocol_checker_enable(1'b1); + master_cfg.set_covergroup_enable(1'b1); + master_cfg.max_outstanding_write_trs = 256; + master_cfg.max_outstanding_read_trs = 256; + master.set_agent_config(master_cfg); + + slave_cfg = axi_superset_config_c::type_id::create("SLAVE_CFG", this); + slave_cfg.set_axi_version(AXI5); + slave_cfg.set_interface_name("AXI_SUPERSET_IF"); + slave_cfg.set_is_master_side(1'b0); + slave_cfg.set_driver_idle_value_cfg(UNDEFINED); + slave_cfg.set_txn_config(if_item_cfg); + slave_cfg.set_is_reactive(1'b1); + slave_cfg.set_id_management_enable(1'b0); + slave_cfg.max_outstanding_write_trs = 256; + slave_cfg.max_outstanding_read_trs = 256; + slave_cfg.set_protocol_checker_enable(1'b0); + slave_cfg.set_covergroup_enable(1'b0); + slave.set_agent_config(slave_cfg); + + master.is_active = UVM_ACTIVE; + slave.is_active = UVM_ACTIVE; + + `uvm_info(get_full_name( ), "Build stage complete.", UVM_LOW) + endfunction: build_phase + + function void connect_phase(uvm_phase phase); + cc_clock_cfg.randomize() with {m_starting_signal_level == 0; m_clock_frequency == 1000; m_duty_cycle == 50;}; + + aw_bp_vseq.bp_sqr = aw_bp_agent.m_sequencer ; + w_bp_vseq.bp_sqr = w_bp_agent.m_sequencer ; + b_bp_vseq.bp_sqr = b_bp_agent.m_sequencer ; + ar_bp_vseq.bp_sqr = ar_bp_agent.m_sequencer ; + r_bp_vseq.bp_sqr = r_bp_agent.m_sequencer ; + + `uvm_info(get_full_name( ), "Connect phase complete.", UVM_LOW) + endfunction: connect_phase + + // at end_of_elaboration, print topology and factory state to verify + function void end_of_elaboration_phase(uvm_phase phase); + uvm_top.print_topology(); + endfunction + +endclass: dut_env diff --git a/lib/uvm_agents/uvma_axi5/example/sv/dut_env_axi_ohg.sv b/lib/uvm_agents/uvma_axi5/example/sv/dut_env_axi_ohg.sv new file mode 100644 index 0000000000..e3cba8e204 --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/sv/dut_env_axi_ohg.sv @@ -0,0 +1,151 @@ +// ---------------------------------------------------------------------------- +//Copyright 2023 CEA* +//*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +// +//Licensed under the Apache License, Version 2.0 (the "License"); +//you may not use this file except in compliance with the License. +//You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +//Unless required by applicable law or agreed to in writing, software +//distributed under the License is distributed on an "AS IS" BASIS, +//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +//See the License for the specific language governing permissions and +//limitations under the License. +//[END OF HEADER] +// ---------------------------------------------------------------------------- + + +class dut_env extends uvm_env; + + watchdog_c m_wd; + + clock_driver_c cc_clock_driver; + clock_config_c cc_clock_cfg; + + reset_driver_c #(1'b1,10,0) cc_reset_driver; + + uvma_axi_agent_c master; + uvma_axi_agent_c slave; + + uvma_axi_cfg_c master_cfg ; + uvma_axi_cfg_c slave_cfg ; + + uvma_axi_transaction_cfg_c if_item_cfg; + + uvma_axi_memory_data_checker_c mem_protocol_checker; + + bp_agent aw_bp_agent ; + bp_agent w_bp_agent ; + bp_agent b_bp_agent ; + bp_agent ar_bp_agent ; + bp_agent r_bp_agent ; + + bp_virtual_sequence aw_bp_vseq ; + bp_virtual_sequence w_bp_vseq ; + bp_virtual_sequence b_bp_vseq ; + bp_virtual_sequence ar_bp_vseq ; + bp_virtual_sequence r_bp_vseq ; + + dut_cfg_c agent_config; + + `uvm_component_utils(dut_env) + + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + m_wd = watchdog_c::type_id::create("m_wd",this); + + cc_clock_driver = clock_driver_c::type_id::create("cc_clock_driver", this ); + cc_clock_cfg = clock_config_c::type_id::create("cc_clock_cfg", this ); + cc_clock_driver.m_clk_cfg = cc_clock_cfg; + cc_reset_driver = reset_driver_c#( 1'b1,10,0 )::type_id::create("cc_reset_driver", this ); + + aw_bp_agent = bp_agent::type_id::create( "aw_bp_agent" , this ); + w_bp_agent = bp_agent::type_id::create( "w_bp_agent" , this ); + b_bp_agent = bp_agent::type_id::create( "b_bp_agent" , this ); + ar_bp_agent = bp_agent::type_id::create( "ar_bp_agent" , this ); + r_bp_agent = bp_agent::type_id::create( "r_bp_agent" , this ); + + aw_bp_vseq = bp_virtual_sequence::type_id::create( "aw_bp_sequence" , this); + w_bp_vseq = bp_virtual_sequence::type_id::create( "w_bp_sequence" , this); + b_bp_vseq = bp_virtual_sequence::type_id::create( "b_bp_sequence" , this); + ar_bp_vseq = bp_virtual_sequence::type_id::create( "ar_bp_sequence" , this); + r_bp_vseq = bp_virtual_sequence::type_id::create( "r_bp_sequence" , this); + + agent_config = dut_cfg_c::type_id::create("dut_cfg_c"); + + master = uvma_axi_agent_c::type_id::create("MASTER_AGENT",this); + slave = uvma_axi_agent_c::type_id::create("SLAVE_AGENT",this); + + mem_protocol_checker = uvma_axi_memory_data_checker_c::type_id::create("SB",this); + + if_item_cfg = new("TB_TXN_CFG"); + if_item_cfg.set_id_width(16); + if_item_cfg.set_addr_width(32); + if_item_cfg.set_data_width(64); + if_item_cfg.set_user_width(100); + if_item_cfg.set_max_delay_cycles(5); + + master_cfg = uvma_axi_cfg_c::type_id::create("MASTER_CFG", this); + master_cfg.set_axi_version(AXI5); + master_cfg.set_interface_name("AXI_SUPERSET_IF"); + master_cfg.set_axi_lite(LITE) ; // Set the version of the AXI protocol: only AXI4 is supported currently + master_cfg.set_is_master_side(1'b1); + master_cfg.set_driver_idle_value_cfg(UNDEFINED); + master_cfg.set_txn_config(if_item_cfg); + master_cfg.set_id_management_enable(1'b0); + mem_protocol_checker.set_agent_config(master_cfg); + + slave_cfg = uvma_axi_cfg_c::type_id::create("SLAVE_CFG", this); + slave_cfg.set_axi_version(AXI5); + slave_cfg.set_interface_name("AXI_SUPERSET_IF"); + slave_cfg.set_is_master_side(1'b0); + slave_cfg.set_driver_idle_value_cfg(UNDEFINED); + slave_cfg.set_txn_config(if_item_cfg); + slave_cfg.set_id_management_enable(1'b0); + slave_cfg.max_outstanding_write_trs = 256; + slave_cfg.max_outstanding_read_trs = 256; + slave_cfg.ordering_write_mode = UVMA_AXI_ORDERING_MODE_FIFO; + slave_cfg.ordering_read_mode = UVMA_AXI_ORDERING_MODE_FIFO; + master.is_active = UVM_ACTIVE; + slave.is_active = UVM_ACTIVE; + + master_cfg.is_active = UVM_ACTIVE; + slave_cfg.is_active = UVM_ACTIVE; + + uvm_config_db#(uvma_axi_cfg_c)::set(this, "*MASTER_AGENT", "cfg", master_cfg); + uvm_config_db#(uvma_axi_cfg_c)::set(this, "*SLAVE_AGENT", "cfg", slave_cfg); + + `uvm_info(get_full_name( ), "Build stage complete.", UVM_LOW) + endfunction: build_phase + + function void connect_phase(uvm_phase phase); + cc_clock_cfg.randomize() with {m_starting_signal_level == 0; m_clock_frequency == 1000; m_duty_cycle == 50;}; + + aw_bp_vseq.bp_sqr = aw_bp_agent.m_sequencer ; + w_bp_vseq.bp_sqr = w_bp_agent.m_sequencer ; + b_bp_vseq.bp_sqr = b_bp_agent.m_sequencer ; + ar_bp_vseq.bp_sqr = ar_bp_agent.m_sequencer ; + r_bp_vseq.bp_sqr = r_bp_agent.m_sequencer ; + + // Connecting the monitor to the protocol checker module + master.monitor.m_uvma_axi_write_rsp_packets_collected.connect( mem_protocol_checker.m_write_rsp_packets_collected.analysis_export ) ; + master.monitor.m_uvma_axi_read_rsp_packets_collected .connect( mem_protocol_checker.m_read_rsp_packets_collected.analysis_export ) ; + master.monitor.m_uvma_axi_read_req_packets_collected .connect( mem_protocol_checker.m_read_req_packets_collected.analysis_export ) ; + master.monitor.m_uvma_axi_write_req_packets_collected.connect( mem_protocol_checker.m_write_req_packets_collected.analysis_export ) ; + + `uvm_info(get_full_name( ), "Connect phase complete.", UVM_LOW) + endfunction: connect_phase + + // at end_of_elaboration, print topology and factory state to verify + function void end_of_elaboration_phase(uvm_phase phase); + uvm_top.print_topology(); + endfunction + +endclass: dut_env diff --git a/lib/uvm_agents/uvma_axi5/example/sv/dut_env_pkg.sv b/lib/uvm_agents/uvma_axi5/example/sv/dut_env_pkg.sv new file mode 100644 index 0000000000..f8ae15e02b --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/sv/dut_env_pkg.sv @@ -0,0 +1,36 @@ +// ---------------------------------------------------------------------------- +//Copyright 2023 CEA* +//*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +// +//Licensed under the Apache License, Version 2.0 (the "License"); +//you may not use this file except in compliance with the License. +//You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +//Unless required by applicable law or agreed to in writing, software +//distributed under the License is distributed on an "AS IS" BASIS, +//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +//See the License for the specific language governing permissions and +//limitations under the License. +//[END OF HEADER] +// ---------------------------------------------------------------------------- + +package dut_env_pkg; + import uvm_pkg::*; + import watchdog_pkg::*; + import clock_driver_pkg::*; + import reset_driver_pkg::*; + import bp_driver_pkg::*; + import uvma_axi_pkg::*; + typedef enum { + NO_BP, + HEAVY_BP, + OCCASSIONAL_BP + } bp_type_t; + `include "uvm_macros.svh" + `include "bp_virtual_sequence.svh" + `include "dut_cfg_c.svh" + `include "mem_protocol_checker.sv" + `include "dut_env_axi_ohg.sv" +endpackage: dut_env_pkg diff --git a/lib/uvm_agents/uvma_axi5/example/sv/mem_protocol_checker.sv b/lib/uvm_agents/uvma_axi5/example/sv/mem_protocol_checker.sv new file mode 100644 index 0000000000..725cf609be --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/sv/mem_protocol_checker.sv @@ -0,0 +1,482 @@ +// ---------------------------------------------------------------------------- +//Copyright 2023 CEA* +//*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +// +//Licensed under the Apache License, Version 2.0 (the "License"); +//you may not use this file except in compliance with the License. +//You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +//Unless required by applicable law or agreed to in writing, software +//distributed under the License is distributed on an "AS IS" BASIS, +//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +//See the License for the specific language governing permissions and +//limitations under the License. +//[END OF HEADER] +// ---------------------------------------------------------------------------- +// Description : Collect request/response from the monitor and the response +// model and compare them to verify the uvma_axi protocol +// +// ---------------------------------------------------------------------------- + +// ----------------------------------------------------------------------- +// Class uvma_axi_protocol_checker_c +// ----------------------------------------------------------------------- +class uvma_axi_memory_data_checker_c extends uvm_scoreboard; + + `uvm_component_utils(uvma_axi_memory_data_checker_c) + + protected string name ; + event reset_asserted ; + event reset_deasserted ; + + // ----------------------------------------------------------------------- + // Analysis Ports + // ----------------------------------------------------------------------- + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) m_write_req_packets_collected ; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) m_read_req_packets_collected ; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) m_write_rsp_packets_collected ; + uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) m_read_rsp_packets_collected ; + + // ----------------------------------------------------------------------- + // Data Structures to store uvma_axi/chi req/rsp + // ----------------------------------------------------------------------- + // Data structure to store analysis port outputs + uvma_axi_transaction_c m_wreq_packet ; + uvma_axi_transaction_c m_rreq_packet ; + uvma_axi_transaction_c m_wrsp_packet ; + uvma_axi_transaction_c m_rrsp_packet ; + + // Associative array to store transaction + uvma_axi_transaction_c m_read_txn_db[uvma_axi_sig_id_t][$] ; + uvma_axi_transaction_c m_write_txn_db[uvma_axi_sig_id_t][$] ; + + logic [7:0] m_mem_array[uvma_axi_sig_addr_t] ; + + // ----------------------------------------------------------------------- + // Counter for the number of request/response + // ----------------------------------------------------------------------- + protected int m_count_read_req ; + protected int m_count_write_req ; + protected int m_count_read_rsp ; + protected int m_count_write_rsp ; + + uvma_axi_cfg_c agent_cfg ; + + // ------------------------------------------------------------------------ + // Constructor + // ------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + this.name = name; + endfunction: new + + // ----------------------------------------------------------------------- + // Build Phase + // ----------------------------------------------------------------------- + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + // Initialisation of the uvm_tlm_analysis_fifo for uvma_axi interface + m_write_req_packets_collected = new("m_write_req_packets_collected" , this) ; + m_read_req_packets_collected = new("m_read_req_packets_collected" , this) ; + m_write_rsp_packets_collected = new("m_write_rsp_packets_collected" , this) ; + m_read_rsp_packets_collected = new("m_read_rsp_packets_collected" , this) ; + + // Initialisation of the counters of the testbench + // uvma_axi transactions counters + m_count_read_req = 0 ; + m_count_write_req = 0 ; + m_count_read_rsp = 0 ; + m_count_write_rsp = 0 ; + + `uvm_info(this.name, "Build stage complete.", UVM_LOW) + endfunction: build_phase + + // ----------------------------------------------------------------------- + // Functions set/get + // ----------------------------------------------------------------------- + // AGENT CONFIGURATION + function uvma_axi_cfg_c get_agent_config(); + get_agent_config = agent_cfg ; + endfunction : get_agent_config + + function void set_agent_config( uvma_axi_cfg_c config_i ); + `uvm_info(this.name, + $sformatf("Setting the agent configuraiton CFG=%0s", config_i.convert2string() ), + UVM_DEBUG) + agent_cfg = config_i ; + endfunction: set_agent_config + + // ------------------------------------------------------------------------ + // Pre reset phase + // ------------------------------------------------------------------------ + virtual task pre_reset_phase(uvm_phase phase); + -> reset_asserted; + `uvm_info(this.name, "Pre Reset stage complete.", UVM_LOW) + endtask : pre_reset_phase + + // ------------------------------------------------------------------------ + // Reset phase + // ------------------------------------------------------------------------ + task reset_phase(uvm_phase phase ); + super.reset_phase(phase); + + // Flushing the uvma_axi uvm_tlm_analysis_fifo + m_write_req_packets_collected.flush() ; + m_read_req_packets_collected.flush() ; + m_write_rsp_packets_collected.flush() ; + m_read_rsp_packets_collected.flush() ; + + // Reset of the associative arrays + m_read_txn_db.delete() ; + m_write_txn_db.delete() ; + + // Initialisation of the counters of the testbench + // uvma_axi transactions counters + m_count_read_req = 0 ; + m_count_write_req = 0 ; + m_count_read_rsp = 0 ; + m_count_write_rsp = 0 ; + + `uvm_info(this.name, "Reset stage complete.", UVM_LOW) + endtask: reset_phase + + // ------------------------------------------------------------------------ + // Post reset phase + // ------------------------------------------------------------------------ + virtual task post_reset_phase(uvm_phase phase); + -> reset_deasserted; + `uvm_info(this.name, "Post Reset stage complete.", UVM_LOW) + endtask : post_reset_phase + + // ----------------------------------------------------------------------- + // Run Phase + // ----------------------------------------------------------------------- + virtual task run_phase(uvm_phase phase); + super.run_phase(phase); + forever begin + @(reset_deasserted); + fork + + collect_write_req ( phase ) ; + collect_read_req ( phase ) ; + collect_write_rsp ( phase ) ; + collect_read_rsp ( phase ) ; + + join_none + @(reset_asserted); + disable fork; + end + endtask: run_phase + + + // ----------------------------------------------------------------------- + // ----------------------------------------------------------------------- + // Interface tasks + // ----------------------------------------------------------------------- + // ----------------------------------------------------------------------- + + // ----------------------------------------------------------------------- + // Task collect_write_req + // + // Collect input write requests from the axi interface + // ----------------------------------------------------------------------- + virtual task collect_write_req( uvm_phase phase ); + uvma_axi_transaction_c write_req; + + forever begin + // Wait to receive a packet from the analysis port and store it in the + // m_uvma_axi_req_packet data structure + m_write_req_packets_collected.get(m_wreq_packet); + + // Creating a new object to store the input packet data structure, + // before storing it inside a queue + write_req = new; + $cast(write_req, m_wreq_packet.clone()); + write_req.set_config(agent_cfg.get_txn_config()); + write_req.post_randomize() ; + + // Register the uvma_axi transaction in an associative array + m_write_txn_db[write_req.m_id].push_front(write_req); + + // Increment write request counter + m_count_write_req++; + + end // forever + endtask: collect_write_req + + // ----------------------------------------------------------------------- + // Task collect_read_req + // + // Collect input read requests from the axi interface + // ----------------------------------------------------------------------- + virtual task collect_read_req( uvm_phase phase ); + string ids_s; + uvma_axi_transaction_c read_req; + + forever begin + // Wait to receive a packet from the analysis port and store it in the + // m_req_packet data structure + m_read_req_packets_collected.get(m_rreq_packet); + + // Creating a new object to store the input packet data structure, + // before storing it inside a queue + read_req = new; + $cast(read_req, m_rreq_packet.clone()); + read_req.set_config(agent_cfg.get_txn_config()); + read_req.post_randomize() ; + + // Register the axi transaction in an associative array + m_read_txn_db[read_req.m_id].push_front(read_req); + + // Increment read request counter + m_count_read_req++; + + end // forever + endtask: collect_read_req + + // ----------------------------------------------------------------------- + // Task collect_write_rsp + // + // Collect input write response from the axi interface + // ----------------------------------------------------------------------- + virtual task collect_write_rsp( uvm_phase phase ); + uvma_axi_transaction_c write_req; + uvma_axi_transaction_c write_rsp; + + forever begin + // Wait to receive a packet from the analysis port and store it in the + // m_rsp_packet data structure + m_write_rsp_packets_collected.get( m_wrsp_packet ); + + // Creating a new object to store the response packet information, + // before storing it inside a queue + write_rsp = new; + $cast( write_rsp, m_wrsp_packet.clone() ); + + if ( m_write_txn_db.exists( write_rsp.m_id ) ) begin + write_req = m_write_txn_db[write_rsp.m_id].pop_back() ; + end else begin + `uvm_error(this.name, + $sformatf("No corresponding read request found in database m_write_txn_db: ID=%0h(h)", write_rsp.m_id) ) + end + `uvm_info(this.name, + $sformatf("WRITE_REQ=%0s", write_req.convert2string() ), + UVM_NONE) + `uvm_info(this.name, + $sformatf("WRITE_RSP=%0s", write_rsp.convert2string() ), + UVM_NONE) + + // Verification of the axi write response + if ( write_rsp.m_resp[0] == OKAY ) begin + write_mem ( write_req ); + end else begin + `uvm_error(this.name, + $sformatf("Since the memory sent back an error for the write transaction ID=%0h(h), the memory is not updated with the corresponding data", write_rsp.m_id) ) + end + + // Increment the write rsp counter + m_count_write_rsp++; + + // Remove the transaction from the transaction associative array + if ( m_write_txn_db[write_rsp.m_id].size() == 0 ) + m_write_txn_db.delete(write_rsp.m_id); + end + endtask : collect_write_rsp + + // ----------------------------------------------------------------------- + // Task collect_read_rsp + // + // Collect input read response from the axi interface + // ----------------------------------------------------------------------- + virtual task collect_read_rsp( uvm_phase phase ); + uvma_axi_transaction_c read_rsp; + + forever begin + // Wait to receive a packet from the analysis port and store it in the + // m_rsp_packet data structure + m_read_rsp_packets_collected.get( m_rrsp_packet ); + + // Creating a new object to store the response packet information, + // before storing it inside a queue + read_rsp = new; + $cast( read_rsp, m_rrsp_packet.clone() ); + + // If the rsp is the last of its burst, increment the corresponding + // counter and register the event for the perf mon + // Call the corresponding task to compare requests/responses + read_mem ( read_rsp ); + + // Increment the read rsp counter + m_count_read_rsp++; + + // Remove the transaction from the transaction associative array + if ( m_read_txn_db[read_rsp.m_id].size() == 0 ) + m_read_txn_db.delete(read_rsp.m_id); + + end + endtask : collect_read_rsp + + + // ----------------------------------------------------------------------- + // ----------------------------------------------------------------------- + // + // MEMORY TASKS + // + // ----------------------------------------------------------------------- + // ----------------------------------------------------------------------- + + // ----------------------------------------------------------------------- + // Task check_write_req + // + // Compare the corresponding write request from the source to the write + // request received on the dest interface + // ----------------------------------------------------------------------- + task write_mem ( + uvma_axi_transaction_c write_req + ); + int nb_flits ; // Number of flits of data of the transaction + int bus_nbytes ; // Number of bytes of the data bus + int nb_bytes ; // Maximum number of bytes of the transaction for each flit of data + + // Variables used for the byte lane computing + uvma_axi_sig_addr_t aligned_addr, address_n ; + int flag_wrap ; + + // Computing some values necessary for the verification of the transaction + nb_flits = write_req.m_len + 1 ; + bus_nbytes = agent_cfg.get_txn_config().get_data_width()/8 ; + nb_bytes = 2**write_req.m_size ; + + foreach( write_req.m_wstrb[i] ) begin + + aligned_addr = uvma_axi_sig_addr_t'( write_req.m_flit_addr[i] / bus_nbytes ) * bus_nbytes ; + address_n = aligned_addr; + for ( int j = 0 ; j < bus_nbytes ; j++ ) begin + if ( write_req.m_wstrb[i][j] ) begin + m_mem_array[address_n] = write_req.m_data[i][8*j +: 8]; + end + address_n += 1; + end + end // foreach + + endtask: write_mem + + // ----------------------------------------------------------------------- + // Task check_read_rsp + // + // Compare the corresponding read response from the dest to the read + // response received on the source interface + // ----------------------------------------------------------------------- + task read_mem ( + uvma_axi_transaction_c read_rsp + ); + uvma_axi_transaction_c read_req ; + + int nb_flits ; // Number of flits of data of the transaction + int bus_nbytes ; // Number of bytes of the data bus + int nb_bytes ; // Maximum number of bytes of the transaction for each flit of data + + // Variables used for the byte lane computing + uvma_axi_sig_addr_t aligned_addr, address_n ; + uvma_axi_sig_addr_t wrap_boundary ; + int flag_wrap ; + + if ( m_read_txn_db.exists( read_rsp.m_id ) ) begin + read_req = m_read_txn_db[read_rsp.m_id].pop_back() ; + end else begin + `uvm_error(this.name, + $sformatf("No corresponding read request found in database m_read_txn_db: ID=%0h(h)", read_rsp.m_id) ) + end + + `uvm_info(this.name, + $sformatf("READ_REQ=%0s", read_req.convert2string() ), + UVM_NONE) + `uvm_info(this.name, + $sformatf("READ_RSP=%0s", read_rsp.convert2string() ), + UVM_NONE) + // Computing some values necessary for the verification of the transaction + nb_flits = read_req.m_len + 1 ; + bus_nbytes = agent_cfg.get_txn_config().get_data_width()/8 ; + nb_bytes = 2**read_req.m_size ; + + // Check that the number of bytes exchanged for each flit respect the + // protocol depending of the start address, the size of the transaction + // and the number of flit exchanged + wrap_boundary = uvma_axi_sig_addr_t'( read_req.m_addr / ( nb_bytes * nb_flits ) ) * ( nb_bytes * nb_flits ) ; + flag_wrap = 0 ; + address_n = 0 ; + foreach( read_rsp.m_data[i] ) begin + uvma_axi_sig_data_t read_data_flit; + + // Using the equation of the specification, section A3.4 of the IHI022H + // version of the amba axi protocol to check if the position of the + // exchanged bytes in the write strobe respects the protocol axi + // Equation from the specification + if ( read_req.m_burst != FIXED ) begin // Burst mode INCR or WRAP + + // Computing the address and byte lane for the first flit of the + // transaction + if ( i == 0 ) begin + address_n = read_req.m_addr ; + end else begin + // Computing the flit address depending of the burst mode, and + // if the transaction has wrapped or not. + if ( ( read_req.m_burst == WRAP ) && flag_wrap ) begin // If burst mode is WRAP and the transaction has already wrapped + address_n = read_req.m_addr + ( i * nb_bytes ) - ( nb_bytes * nb_flits ) ; + end else begin // For burst mode INCR, and WRAP if the transaction has not wrapped + address_n = aligned_addr + i * nb_bytes; + end + + end + aligned_addr = uvma_axi_sig_addr_t'( read_req.m_addr / nb_bytes ) * nb_bytes ; + + // Checking for the burst mode WRAP if the address has wrapped + if ( ( address_n == ( wrap_boundary + ( nb_bytes * nb_flits ) ) ) && + ( read_req.m_burst == WRAP ) ) begin + flag_wrap = 1 ; + address_n = wrap_boundary ; + end // if wrap + + end else begin // Burst mode FIXED + // Constant addr and byte lane for all flits of the transaction + address_n = read_req.m_addr ; + end // if FIXED + + address_n = uvma_axi_sig_addr_t'( address_n / bus_nbytes ) * bus_nbytes ; + read_data_flit = 'h0; + for ( int j = 0 ; j < bus_nbytes ; j++ ) begin + if ( m_mem_array.exists( address_n) ) begin // This memory bytes was already accessed by a previous write + read_data_flit[8*j +: 8] = m_mem_array[address_n] ; + end else begin + read_data_flit[8*j +: 8] = 8'h0 ; + end + address_n += 1; + end + + if ( read_data_flit != read_rsp.m_data[i] ) begin + `uvm_error(this.name, + $sformatf("The data flit are not corresponding: READ_TXN_ID=%0h(h) SB_DATA_FLIT=%0h(h) DUT_DATA_FLIT=%0h(h)", read_rsp.m_id, read_data_flit, read_rsp.m_data[i]) ) + end + end // foreach + + endtask: read_mem + + // ----------------------------------------------------------------------- + // Report phase + // ----------------------------------------------------------------------- + virtual function void report_phase(uvm_phase phase); + // ----------------------------------------------------------------------- + // Check that the dynamic arrays are empty at the end of the + // simulation + // ----------------------------------------------------------------------- + if ( m_read_txn_db.num() != 0 ) + `uvm_error(this.name, "The read response dynamic array is not empty") + if ( m_write_txn_db.num() != 0 ) + `uvm_error(this.name, "The write response dynamic array is not empty") + + endfunction: report_phase + +endclass: uvma_axi_memory_data_checker_c diff --git a/lib/uvm_agents/uvma_axi5/example/test/base_test_c.svh b/lib/uvm_agents/uvma_axi5/example/test/base_test_c.svh new file mode 100644 index 0000000000..83d69f4bed --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/test/base_test_c.svh @@ -0,0 +1,67 @@ +// ---------------------------------------------------------------------------- +//Copyright 2023 CEA* +//*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +// +//Licensed under the Apache License, Version 2.0 (the "License"); +//you may not use this file except in compliance with the License. +//You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +//Unless required by applicable law or agreed to in writing, software +//distributed under the License is distributed on an "AS IS" BASIS, +//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +//See the License for the specific language governing permissions and +//limitations under the License. +//[END OF HEADER] +// ---------------------------------------------------------------------------- +// Description : Class that serve as a base for all test subclasses +// Contains the build, the end_of_elaboration and the run phases +// +// +// ---------------------------------------------------------------------------- +class base_test_c extends uvm_test; + `uvm_component_utils(base_test_c) + + dut_env env; + uvm_table_printer printer; + + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + env = dut_env::type_id::create("ENV", this); + printer = new( ); + printer.knobs.depth = 5; + endfunction:build_phase + + task configure_phase(uvm_phase phase); + super.configure_phase(phase); + + if ( !env.agent_config.randomize() ) begin + `uvm_fatal("RANDOMIZE_FAILED", "Failed randomization of the bp_gen config") + end + `uvm_info("BP_WHICH", $sformatf("BP_MODE=%p", env.agent_config.aw_bp), UVM_LOW) + env.aw_bp_vseq.which_bp = env.agent_config.aw_bp ; + env.w_bp_vseq.which_bp = env.agent_config.w_bp ; + env.b_bp_vseq.which_bp = env.agent_config.b_bp ; + env.ar_bp_vseq.which_bp = env.agent_config.ar_bp ; + env.r_bp_vseq.which_bp = env.agent_config.r_bp ; + + endtask : configure_phase + + virtual function void end_of_elaboration_phase(uvm_phase phase); + `uvm_info(get_type_name( ), $sformatf("Printing the test topology :\n%s", this.sprint(printer)), UVM_LOW) + // factory.print(); + endfunction: end_of_elaboration_phase + + virtual task main_phase(uvm_phase phase); + super.main_phase(phase); + phase.raise_objection(this); + #2000ns + phase.drop_objection(this); + endtask: main_phase + +endclass: base_test_c diff --git a/lib/uvm_agents/uvma_axi5/example/test/bursty_test_c.svh b/lib/uvm_agents/uvma_axi5/example/test/bursty_test_c.svh new file mode 100644 index 0000000000..acc1d90610 --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/test/bursty_test_c.svh @@ -0,0 +1,111 @@ +// ---------------------------------------------------------------------------- +//Copyright 2023 CEA* +//*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +// +//Licensed under the Apache License, Version 2.0 (the "License"); +//you may not use this file except in compliance with the License. +//You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +//Unless required by applicable law or agreed to in writing, software +//distributed under the License is distributed on an "AS IS" BASIS, +//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +//See the License for the specific language governing permissions and +//limitations under the License. +//[END OF HEADER] +// ---------------------------------------------------------------------------- +// Description : This class creates, configures and start a test with +// the bursty_sequence_c class +// +// +// ---------------------------------------------------------------------------- +class bursty_test_c extends base_test_c; + `uvm_component_utils(bursty_test_c) + + uvma_axi_master_sequence_c master_seq[5]; + uvma_axi_master_write_sequence_c master_write_seq[5]; + uvma_axi_master_read_sequence_c master_read_seq[5]; + uvma_axi_master_excl_sequence_c master_excl_seq[5]; + + uvma_axi_slv_seq_c slave_seq; + + //--------------------------- + // Factory + //--------------------------- + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + //--------------------------- + // Build phase + //--------------------------- + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction: build_phase + + //--------------------------- + // Run phase + //--------------------------- + virtual task main_phase(uvm_phase phase); + int num_seq = 1; + + fork + env.aw_bp_vseq.start(null); + env.w_bp_vseq.start(null); + env.b_bp_vseq.start(null); + env.ar_bp_vseq.start(null); + env.r_bp_vseq.start(null); + slave_seq.start(env.slave.vsequencer); + join_none + + phase.raise_objection(this); + + for ( int i = 0 ; i < num_seq ; i ++) begin + // FIXME : passing the argument via the create doesn't work. Need to + // pass via the function new. + master_seq[i] = uvma_axi_master_sequence_c::type_id::create( $sformatf("master_seq_%0d", i)); + master_write_seq[i] = uvma_axi_master_write_sequence_c::type_id::create( $sformatf("master_write_seq_%0d", i)); + master_read_seq[i] = uvma_axi_master_read_sequence_c::type_id::create( $sformatf("master_read_seq_%0d", i)); + master_excl_seq[i] = uvma_axi_master_excl_sequence_c::type_id::create( $sformatf("master_excl_seq_%0d", i)); + master_seq[i].set_num_txn( (i+1)*300 ); + master_write_seq[i].set_num_txn( (i+1)*300 ); + master_read_seq[i].set_num_txn( (i+1)*300 ); + master_excl_seq[i].set_num_txn( (i+1)*300 ); + + master_seq[i] = new( $sformatf("master_seq_%0d" , i), (i + 1)*300 ); + master_write_seq[i] = new( $sformatf("master_write_seq_%0d" , i), (i + 1)*300 ); + master_read_seq[i] = new( $sformatf("master_read_seq_%0d" , i), (i + 1)*300 ); + master_excl_seq[i] = new( $sformatf("master_excl_seq_%0d" , i), (i + 1)*10 ); + // + slave_seq = uvma_axi_slv_seq_c::type_id::create("slave_seq"); + end + + fork begin + for ( int i = 0 ; i < num_seq ; i ++) begin + fork + automatic int j = i; + master_seq[j].start(env.master.vsequencer); + master_write_seq[j].start(env.master.vsequencer); + master_read_seq[j].start(env.master.vsequencer); + // master_excl_seq[j].start(env.master.m_sequencer); + join_none + end + wait fork; + end join + // wait fork; + + phase.drop_objection(this); + env.aw_bp_vseq.bp_sqr.stop_sequences(); + env.w_bp_vseq.bp_sqr.stop_sequences(); + env.b_bp_vseq.bp_sqr.stop_sequences(); + env.ar_bp_vseq.bp_sqr.stop_sequences(); + env.r_bp_vseq.bp_sqr.stop_sequences(); + env.slave.vsequencer.stop_sequences(); + + `uvm_info("TEST", "Sequence proto is ending", UVM_DEBUG) + + super.main_phase(phase); + endtask: main_phase + +endclass: bursty_test_c diff --git a/lib/uvm_agents/uvma_axi5/example/test/test_pkg.sv b/lib/uvm_agents/uvma_axi5/example/test/test_pkg.sv new file mode 100644 index 0000000000..8e47fab771 --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/test/test_pkg.sv @@ -0,0 +1,35 @@ +// ---------------------------------------------------------------------------- +//Copyright 2023 CEA* +//*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +// +//Licensed under the Apache License, Version 2.0 (the "License"); +//you may not use this file except in compliance with the License. +//You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +//Unless required by applicable law or agreed to in writing, software +//distributed under the License is distributed on an "AS IS" BASIS, +//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +//See the License for the specific language governing permissions and +//limitations under the License. +//[END OF HEADER] +// ---------------------------------------------------------------------------- +// Description : +// +// +// ---------------------------------------------------------------------------- + +package test_pkg; + + import uvm_pkg::*; + import uvma_axi_pkg::*; + import dut_env_pkg::*; + `include "uvm_macros.svh"; + `include "base_test_c.svh"; + `include "bursty_test_c.svh"; + + +endpackage : test_pkg + + diff --git a/lib/uvm_agents/uvma_axi5/example/top/run.do b/lib/uvm_agents/uvma_axi5/example/top/run.do new file mode 100644 index 0000000000..4ed8a948fd --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/top/run.do @@ -0,0 +1 @@ +run -all diff --git a/lib/uvm_agents/uvma_axi5/example/top/run_test.do b/lib/uvm_agents/uvma_axi5/example/top/run_test.do new file mode 100644 index 0000000000..c416cb6fd1 --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/top/run_test.do @@ -0,0 +1,2 @@ +coverage save -onexit ucdb/cov_test_ucdb +run -all diff --git a/lib/uvm_agents/uvma_axi5/example/top/top.sv b/lib/uvm_agents/uvma_axi5/example/top/top.sv new file mode 100644 index 0000000000..bf5c4da7c4 --- /dev/null +++ b/lib/uvm_agents/uvma_axi5/example/top/top.sv @@ -0,0 +1,165 @@ +// ---------------------------------------------------------------------------- +//Copyright 2023 CEA* +//*Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) +// +//Licensed under the Apache License, Version 2.0 (the "License"); +//you may not use this file except in compliance with the License. +//You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +//Unless required by applicable law or agreed to in writing, software +//distributed under the License is distributed on an "AS IS" BASIS, +//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +//See the License for the specific language governing permissions and +//limitations under the License. +//[END OF HEADER] +// ---------------------------------------------------------------------------- + + +module top; + + timeunit 1ns; + timeprecision 100ps; + + import uvm_pkg::*; + import test_pkg::*; + + bit clk_i; + bit reset; + bit reset_n; + bit post_shutdown_phase; + + xrtl_clock_vif clock_if( .clock(clk_i)); + xrtl_reset_vif #(1'b1,10,0) reset_if(.clk(clk_i), + .reset(reset), + .reset_n(reset_n), + .post_shutdown_phase(post_shutdown_phase) + ); + + bp_vif #(1) aw_bp ( .clk( clk_i ), .rstn( reset_n ) ); + bp_vif #(1) w_bp ( .clk( clk_i ), .rstn( reset_n ) ); + bp_vif #(1) b_bp ( .clk( clk_i ), .rstn( reset_n ) ); + bp_vif #(1) ar_bp ( .clk( clk_i ), .rstn( reset_n ) ); + bp_vif #(1) r_bp ( .clk( clk_i ), .rstn( reset_n ) ); + + uvma_axi_intf axi_assert_if( .clk(clk_i), .rst_n(reset_n) ); +// axi_superset_if axi_vif (.clk_i(clk_i), .reset_n(reset_n)); + uvma_axi_mst_intf axi_vif( .clk(clk_i), .rst_n(reset_n) ); + uvma_axi_intf axi_slv_vif( .clk(clk_i), .rst_n(reset_n) ); + + assign axi_vif.aw_ready = axi_slv_vif.aw_ready; + assign axi_vif.w_ready = axi_slv_vif.w_ready; + assign axi_vif.ar_ready = axi_slv_vif.ar_ready; + assign axi_vif.b_ready = ~b_bp.bp_out ; + assign axi_vif.r_ready = ~r_bp.bp_out ; + + assign axi_slv_vif.b_ready = axi_vif.b_ready ; + assign axi_slv_vif.r_ready = axi_vif.r_ready ; + + assign axi_slv_vif.aw_id = axi_vif.aw_id; + assign axi_slv_vif.aw_addr = axi_vif.aw_addr; + assign axi_slv_vif.aw_user = axi_vif.aw_user; + assign axi_slv_vif.aw_len = axi_vif.aw_len; + assign axi_slv_vif.aw_size = axi_vif.aw_size; + assign axi_slv_vif.aw_burst = axi_vif.aw_burst; + assign axi_slv_vif.aw_lock = axi_vif.aw_lock; + assign axi_slv_vif.aw_cache = axi_vif.aw_cache; + assign axi_slv_vif.aw_prot = axi_vif.aw_prot; + assign axi_slv_vif.aw_qos = axi_vif.aw_qos; + assign axi_slv_vif.aw_region = axi_vif.aw_region; + assign axi_slv_vif.aw_valid = axi_vif.aw_valid; + assign axi_slv_vif.aw_atop = axi_vif.aw_atop; + assign axi_slv_vif.aw_trace = axi_vif.aw_trace; + assign axi_slv_vif.aw_loop = axi_vif.aw_loop; + assign axi_slv_vif.aw_mmusecsid = axi_vif.aw_mmusecsid; + assign axi_slv_vif.aw_mmusid = axi_vif.aw_mmusid; + assign axi_slv_vif.aw_mmussidv = axi_vif.aw_mmussidv; + assign axi_slv_vif.aw_mmussid = axi_vif.aw_mmussid; + assign axi_slv_vif.aw_mmuatst = axi_vif.aw_mmuatst; + assign axi_slv_vif.aw_nsaid = axi_vif.aw_nsaid; + assign axi_slv_vif.aw_idunq = axi_vif.aw_idunq; + + + assign axi_slv_vif.w_data = axi_vif.w_data; + assign axi_slv_vif.w_strb = axi_vif.w_strb; + assign axi_slv_vif.w_user = axi_vif.w_user; + assign axi_slv_vif.w_last = axi_vif.w_last; + assign axi_slv_vif.w_datachk = axi_vif.w_datachk; + assign axi_slv_vif.w_poison = axi_vif.w_poison; + assign axi_slv_vif.w_trace = axi_vif.w_trace; + assign axi_slv_vif.w_valid = axi_vif.w_valid; + + + assign axi_vif.b_id = axi_slv_vif.b_id; + assign axi_vif.b_user = axi_slv_vif.b_user; + assign axi_vif.b_resp = axi_slv_vif.b_resp; + assign axi_vif.b_trace = axi_slv_vif.b_trace; + assign axi_vif.b_loop = axi_slv_vif.b_loop; + assign axi_vif.b_idunq = axi_slv_vif.b_idunq; + assign axi_vif.b_valid = axi_slv_vif.b_valid; + + + assign axi_slv_vif.ar_id = axi_vif.ar_id; + assign axi_slv_vif.ar_addr = axi_vif.ar_addr; + assign axi_slv_vif.ar_user = axi_vif.ar_user; + assign axi_slv_vif.ar_len = axi_vif.ar_len; + assign axi_slv_vif.ar_size = axi_vif.ar_size; + assign axi_slv_vif.ar_burst = axi_vif.ar_burst; + assign axi_slv_vif.ar_lock = axi_vif.ar_lock; + assign axi_slv_vif.ar_cache = axi_vif.ar_cache; + assign axi_slv_vif.ar_prot = axi_vif.ar_prot; + assign axi_slv_vif.ar_qos = axi_vif.ar_qos; + assign axi_slv_vif.ar_region = axi_vif.ar_region; + assign axi_slv_vif.ar_valid = axi_vif.ar_valid; + assign axi_slv_vif.ar_trace = axi_vif.ar_trace; + assign axi_slv_vif.ar_loop = axi_vif.ar_loop; + assign axi_slv_vif.ar_mmusecsid = axi_vif.ar_mmusecsid; + assign axi_slv_vif.ar_mmusid = axi_vif.ar_mmusid; + assign axi_slv_vif.ar_mmussidv = axi_vif.ar_mmussidv; + assign axi_slv_vif.ar_mmussid = axi_vif.ar_mmussid; + assign axi_slv_vif.ar_mmuatst = axi_vif.ar_mmuatst; + assign axi_slv_vif.ar_nsaid = axi_vif.ar_nsaid; + assign axi_slv_vif.ar_idunq = axi_vif.ar_idunq; + + + assign axi_vif.r_id = axi_slv_vif.r_id; + assign axi_vif.r_data = axi_slv_vif.r_data; + assign axi_vif.r_user = axi_slv_vif.r_user; + assign axi_vif.r_resp = axi_slv_vif.r_resp; + assign axi_vif.r_last = axi_slv_vif.r_last; + assign axi_vif.r_datachk = axi_slv_vif.r_datachk; + assign axi_vif.r_poison = axi_slv_vif.r_poison; + assign axi_vif.r_trace = axi_slv_vif.r_trace; + assign axi_vif.r_loop = axi_slv_vif.r_loop; + assign axi_vif.r_idunq = axi_slv_vif.r_idunq; + assign axi_vif.r_valid = axi_slv_vif.r_valid; + + uvma_axi_aw_assert axi_aw_assert(.axi_assert(axi_assert_if)); + uvma_axi_w_assert axi_w_assert(.axi_assert(axi_assert_if)); + uvma_axi_ar_assert axi_ar_assert(.axi_assert(axi_assert_if)); + uvma_axi_r_assert axi_r_assert(.axi_assert(axi_assert_if)); + uvma_axi_b_assert axi_b_assert(.axi_assert(axi_assert_if)); + uvma_axi_assert axi_assert(.axi_assert(axi_assert_if)); + uvma_axi_amo_assert axi_amo_assert(.axi_assert(axi_assert_if)); + + initial begin + uvm_config_db #(virtual xrtl_clock_vif )::set(uvm_root::get(), "*", "cc_clock_driver", clock_if ); + uvm_config_db #(virtual xrtl_reset_vif #( 1'b1,10,0) )::set(uvm_root::get(), "*", "cc_reset_driver", reset_if ); + + uvm_config_db #(virtual bp_vif #(1) )::set(uvm_root::get(), "*", "aw_bp_agent" , aw_bp ) ; + uvm_config_db #(virtual bp_vif #(1) )::set(uvm_root::get(), "*", "w_bp_agent" , w_bp ) ; + uvm_config_db #(virtual bp_vif #(1) )::set(uvm_root::get(), "*", "b_bp_agent" , b_bp ) ; + uvm_config_db #(virtual bp_vif #(1) )::set(uvm_root::get(), "*", "ar_bp_agent" , ar_bp ) ; + uvm_config_db #(virtual bp_vif #(1) )::set(uvm_root::get(), "*", "r_bp_agent" , r_bp ) ; + + uvm_config_db #(virtual uvma_axi_mst_intf)::set(null,"*", "axi_mst_vif", axi_vif); + uvm_config_db #(virtual uvma_axi_intf)::set(null,"*", "axi_vif", axi_slv_vif); + +// uvm_config_db #(virtual axi_superset_if )::set(uvm_root::get(), "*", "AXI_SUPERSET_IF", axi_vif); + + run_test(); + end + +endmodule +