From 91b04f93cd0a1802fa702393b59ee16ce0a6da36 Mon Sep 17 00:00:00 2001 From: Mario Date: Tue, 8 Aug 2023 16:04:43 +0000 Subject: [PATCH] Add tohost and adapt existing tests * cv32e20/bsp/crt0.s: add tohost symbol declaration * cv32e20/bsp/link.ld: add tohost symbol linking address * cv32e20/bsp/syscalls.c: add tohost store in the exit function * cv32e20/env/corev-dv/cv32e20_instr_gen_config.sv: add rule to enforce not ZERO reg used in the scratch reg. This constraint was already implemented but not working with vsim * cv32e20/env/uvme/uvme_cv32e20_env.sv: add mechanism to load symbols from the binary for the execution exit. * cv32e20/env/uvme/vseq/uvme_cv32e20_vp_status_flags_seq.sv: Adapt code to host format ( {exit_value, 1} ) * cv32e40p/env/uvme/uvme_rv32isa_covg_trn.sv: substitute uvm_objects_utils(begin/end) for a simple uvm_object_utils * lib/corev-dv/corev_asm_program_gen.sv: delete wfi for locking the core and add tohost mechanism * lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_mon.sv: vsim complaining for using passive_mp * lib/uvm_libs/uvml_sb/uvml_sb_cntxt.sv: delete T_TRN type for event as it causes vsim to fail simulation * mk/Common.mk: add compilation for elfloader vendor * mk/uvmt/vsim.mk: add comilation for elfloader vendor and delete clean_riscv-dv on each corev-dv generation * vendor/elfloader/Makefile: add elfloader vendor * vendor/elfloader/elfloader.cc: add elfloader vendor * lib/corev-dv/corev_asm_program_gen.sv: delete wfi and add syscall on ecall * cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_*: change align of trap handler to 8 --- cv32e20/bsp/Makefile | 14 +- cv32e20/bsp/crt0.S | 2 +- cv32e20/bsp/csr.c | 19 + cv32e20/bsp/csr.h | 93 +++ cv32e20/bsp/csr_encoding.h | 759 ++++++++++++++++++ cv32e20/bsp/link.ld | 15 +- cv32e20/bsp/syscalls.c | 379 +-------- cv32e20/bsp/syscalls.h | 42 + cv32e20/bsp/syscalls_kernel.c | 300 +++++++ .../env/corev-dv/cv32e20_instr_gen_config.sv | 18 +- cv32e20/env/uvme/uvme_cv32e20_cfg.sv | 10 + cv32e20/env/uvme/uvme_cv32e20_env.sv | 71 +- .../vseq/uvme_cv32e20_vp_status_flags_seq.sv | 39 +- cv32e20/tb/uvmt/uvmt_cv32e20_dut_wrap.sv | 6 +- cv32e20/tests/asm/user_define.h | 2 +- .../programs/custom/all_csr_por/all_csr_por.c | 9 +- .../programs/custom/branch_zero/branch_zero.c | 6 +- .../custom/csr_instr_asm/csr_instr_asm.S | 12 +- .../csr_instructions/csr_instructions.c | 14 +- .../programs/custom/debug_test/debug_test.c | 62 +- .../debug_test_known_miscompares/debug_test.c | 18 +- .../debug_test_known_miscompares/handlers.S | 44 +- .../custom/debug_test_reset/debugger.S | 11 +- .../custom/debug_test_trigger/debug_test.c | 24 +- .../generic_exception_test.S | 27 +- .../illegal_instr_test/illegal_instr_test.S | 8 +- .../custom/isa_fcov_holes/isa_fcov_holes.S | 112 +-- .../load_store_rs1_zero/load_store_rs1_zero.S | 44 +- .../riscv_arithmetic_basic_test_0.S | 80 +- .../riscv_arithmetic_basic_test_1.S | 40 +- .../custom/riscv_csr/custom_handlers.S | 48 +- .../programs/custom/riscv_csr/gen_csr_test.py | 157 ++-- .../programs/custom/riscv_csr/riscv_csr.c | 30 +- .../riscv_ebreak_test_0/riscv_ebreak_test_0.S | 35 +- cv32e40p/env/uvme/uvme_rv32isa_covg_trn.sv | 23 +- docs/VerifStrat/source/test_programs.rst | 26 +- lib/corev-dv/corev_asm_program_gen.sv | 13 +- .../src/comps/uvma_obi_memory_mon.sv | 2 +- .../uvma_obi_memory_vp_virtual_printer_seq.sv | 2 +- lib/uvm_libs/uvml_sb/uvml_sb_cntxt.sv | 46 +- mk/Common.mk | 25 +- mk/uvmt/vcs.mk | 4 +- mk/uvmt/vsim.mk | 5 +- vendor/elfloader/Makefile | 45 ++ vendor/elfloader/elfloader.cc | 149 ++++ 45 files changed, 1955 insertions(+), 935 deletions(-) create mode 100644 cv32e20/bsp/csr.c create mode 100644 cv32e20/bsp/csr.h create mode 100644 cv32e20/bsp/csr_encoding.h create mode 100644 cv32e20/bsp/syscalls.h create mode 100644 cv32e20/bsp/syscalls_kernel.c create mode 100644 vendor/elfloader/Makefile create mode 100644 vendor/elfloader/elfloader.cc diff --git a/cv32e20/bsp/Makefile b/cv32e20/bsp/Makefile index 08159f3ab7..604ef5eb11 100644 --- a/cv32e20/bsp/Makefile +++ b/cv32e20/bsp/Makefile @@ -10,25 +10,29 @@ RISCV ?= $(CV_SW_TOOLCHAIN) RISCV_EXE_PREFIX ?= $(RISCV)/bin/riscv32-unknown-elf- RISCV_GCC = $(RISCV_EXE_PREFIX)gcc RISCV_AR = $(RISCV_EXE_PREFIX)ar -SRC = crt0.S handlers.S syscalls.c vectors.S -OBJ = crt0.o handlers.o syscalls.o vectors.o -LIBCV-VERIF = libcv-verif.a +C_FILES = syscalls_kernel.c csr.c csr.h syscalls.c syscalls.h +SRC = crt0.S handlers.S syscalls.c syscalls_kernel.c vectors.S csr.c +OBJ = crt0.o handlers.o syscalls.o syscalls_kernel.o vectors.o csr.o +LIBCV-VERIF = libcv-verif.a CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(CV_SW_MARCH) -Wall -pedantic all: $(LIBCV-VERIF) -$(LIBCV-VERIF): $(OBJ) +$(LIBCV-VERIF): $(OBJ) $(RISCV_AR) rcs $@ $(OBJ) %.o : %.c $(RISCV_GCC) $(CFLAGS) -c $< -o $@ - + %.o : %.S $(RISCV_GCC) $(CFLAGS) -c $< -o $@ clean: rm -f $(OBJ) $(LIBCV-VERIF) +format: + clang-format -i --style=llvm $(C_FILES) + vars: @echo "make bsp variables:" diff --git a/cv32e20/bsp/crt0.S b/cv32e20/bsp/crt0.S index 3422360011..e1349b770c 100644 --- a/cv32e20/bsp/crt0.S +++ b/cv32e20/bsp/crt0.S @@ -55,7 +55,7 @@ _start: li a2, 0 call main - tail exit + tail _exit .size _start, .-_start diff --git a/cv32e20/bsp/csr.c b/cv32e20/bsp/csr.c new file mode 100644 index 0000000000..fe5d7bec7a --- /dev/null +++ b/cv32e20/bsp/csr.c @@ -0,0 +1,19 @@ +#include "csr.h" + +void return_to_machine() { + char *argv[] = {"return_to_machine"}; + execve("return_to_machine", argv, NULL); +} + +inline void set_status_pp(priv_e new_mode) { + + csr_set_mask(mstatus, CSR_MSTATUS_MPP, new_mode); + asm volatile("la t0, 1f;" + "csrrw t0, mepc, t0;" + "mret;" + "1:"); +} + +void test_fail() { exit(1); } + +void test_pass() { exit(0); } diff --git a/cv32e20/bsp/csr.h b/cv32e20/bsp/csr.h new file mode 100644 index 0000000000..8877ba67f2 --- /dev/null +++ b/cv32e20/bsp/csr.h @@ -0,0 +1,93 @@ +#ifndef CSR_H +#define CSR_H + +#include "csr_encoding.h" +#include "syscalls.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#undef errno +#ifndef __ASSEMBLER__ + +extern int errno; + +typedef enum priv_enum { PRIV_M = 0x3, PRIV_S = 0x1, PRIV_U = 0x0 } priv_e; + +inline const char *priv_to_string(priv_e val) { + switch (val) { + case PRIV_M: + return "PRIV_M"; + case PRIV_S: + return "PRIV_S"; + case PRIV_U: + return "PRIV_U"; + default: + return "PRIV"; + } +} + +void set_status_pp(priv_e new_mode); + +void return_to_machine(); + +void test_fail(); + +void test_pass(); + +#define BITS2SHIFT(mask) (mask & -mask) + +#define csr_read(reg) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; \ + }) + +#define csr_write(reg, val) ({ asm volatile("csrw " #reg ", %0" ::"rK"(val)); }) + +#define csr_swap(reg, val) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; \ + }) + +#define csr_set(reg, bit) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; \ + }) + +#define csr_clear(reg, bit) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; \ + }) + +#define csr_clear_mask(reg, mask) csr_clear(reg, BITS2SHIFT(mask)) + +#define csr_set_mask(reg, mask, value) \ + ({ \ + unsigned long __tmp = csr_read(reg); \ + __tmp = __tmp & mask; \ + __tmp |= (value << BITS2SHIFT(mask)); \ + csr_write(reg, __tmp); \ + __tmp; \ + }) + +#define rdtime() csr_read(time) +#define rdcycle() csr_read(cycle) +#define rdinstret() csr_read(instret) + +#endif + +#endif diff --git a/cv32e20/bsp/csr_encoding.h b/cv32e20/bsp/csr_encoding.h new file mode 100644 index 0000000000..0e5ccdd10d --- /dev/null +++ b/cv32e20/bsp/csr_encoding.h @@ -0,0 +1,759 @@ +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_VSTART 0x8 +#define CSR_VXSAT 0x9 +#define CSR_VXRM 0xa +#define CSR_VCSR 0xf +#define CSR_SEED 0x15 +#define CSR_JVT 0x17 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SENVCFG 0x10a +#define CSR_SSTATEEN0 0x10c +#define CSR_SSTATEEN1 0x10d +#define CSR_SSTATEEN2 0x10e +#define CSR_SSTATEEN3 0x10f +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_STIMECMP 0x14d +#define CSR_SISELECT 0x150 +#define CSR_SIREG 0x151 +#define CSR_STOPEI 0x15c +#define CSR_SATP 0x180 +#define CSR_SCONTEXT 0x5a8 +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSTIMECMP 0x24d +#define CSR_VSISELECT 0x250 +#define CSR_VSIREG 0x251 +#define CSR_VSTOPEI 0x25c +#define CSR_VSATP 0x280 +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 +#define CSR_HVIEN 0x608 +#define CSR_HVICTL 0x609 +#define CSR_HENVCFG 0x60a +#define CSR_HSTATEEN0 0x60c +#define CSR_HSTATEEN1 0x60d +#define CSR_HSTATEEN2 0x60e +#define CSR_HSTATEEN3 0x60f +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HVIPRIO1 0x646 +#define CSR_HVIPRIO2 0x647 +#define CSR_HTINST 0x64a +#define CSR_HGATP 0x680 +#define CSR_HCONTEXT 0x6a8 +#define CSR_HGEIP 0xe12 +#define CSR_VSTOPI 0xeb0 +#define CSR_SCOUNTOVF 0xda0 +#define CSR_STOPI 0xdb0 +#define CSR_UTVT 0x7 +#define CSR_UNXTI 0x45 +#define CSR_UINTSTATUS 0x46 +#define CSR_USCRATCHCSW 0x48 +#define CSR_USCRATCHCSWL 0x49 +#define CSR_STVT 0x107 +#define CSR_SNXTI 0x145 +#define CSR_SINTSTATUS 0x146 +#define CSR_SSCRATCHCSW 0x148 +#define CSR_SSCRATCHCSWL 0x149 +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 +#define CSR_MINTSTATUS 0x346 +#define CSR_MSCRATCHCSW 0x348 +#define CSR_MSCRATCHCSWL 0x349 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MVIEN 0x308 +#define CSR_MVIP 0x309 +#define CSR_MENVCFG 0x30a +#define CSR_MSTATEEN0 0x30c +#define CSR_MSTATEEN1 0x30d +#define CSR_MSTATEEN2 0x30e +#define CSR_MSTATEEN3 0x30f +#define CSR_MCOUNTINHIBIT 0x320 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_MTINST 0x34a +#define CSR_MTVAL2 0x34b +#define CSR_MISELECT 0x350 +#define CSR_MIREG 0x351 +#define CSR_MTOPEI 0x35c +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPCFG4 0x3a4 +#define CSR_PMPCFG5 0x3a5 +#define CSR_PMPCFG6 0x3a6 +#define CSR_PMPCFG7 0x3a7 +#define CSR_PMPCFG8 0x3a8 +#define CSR_PMPCFG9 0x3a9 +#define CSR_PMPCFG10 0x3aa +#define CSR_PMPCFG11 0x3ab +#define CSR_PMPCFG12 0x3ac +#define CSR_PMPCFG13 0x3ad +#define CSR_PMPCFG14 0x3ae +#define CSR_PMPCFG15 0x3af +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_PMPADDR16 0x3c0 +#define CSR_PMPADDR17 0x3c1 +#define CSR_PMPADDR18 0x3c2 +#define CSR_PMPADDR19 0x3c3 +#define CSR_PMPADDR20 0x3c4 +#define CSR_PMPADDR21 0x3c5 +#define CSR_PMPADDR22 0x3c6 +#define CSR_PMPADDR23 0x3c7 +#define CSR_PMPADDR24 0x3c8 +#define CSR_PMPADDR25 0x3c9 +#define CSR_PMPADDR26 0x3ca +#define CSR_PMPADDR27 0x3cb +#define CSR_PMPADDR28 0x3cc +#define CSR_PMPADDR29 0x3cd +#define CSR_PMPADDR30 0x3ce +#define CSR_PMPADDR31 0x3cf +#define CSR_PMPADDR32 0x3d0 +#define CSR_PMPADDR33 0x3d1 +#define CSR_PMPADDR34 0x3d2 +#define CSR_PMPADDR35 0x3d3 +#define CSR_PMPADDR36 0x3d4 +#define CSR_PMPADDR37 0x3d5 +#define CSR_PMPADDR38 0x3d6 +#define CSR_PMPADDR39 0x3d7 +#define CSR_PMPADDR40 0x3d8 +#define CSR_PMPADDR41 0x3d9 +#define CSR_PMPADDR42 0x3da +#define CSR_PMPADDR43 0x3db +#define CSR_PMPADDR44 0x3dc +#define CSR_PMPADDR45 0x3dd +#define CSR_PMPADDR46 0x3de +#define CSR_PMPADDR47 0x3df +#define CSR_PMPADDR48 0x3e0 +#define CSR_PMPADDR49 0x3e1 +#define CSR_PMPADDR50 0x3e2 +#define CSR_PMPADDR51 0x3e3 +#define CSR_PMPADDR52 0x3e4 +#define CSR_PMPADDR53 0x3e5 +#define CSR_PMPADDR54 0x3e6 +#define CSR_PMPADDR55 0x3e7 +#define CSR_PMPADDR56 0x3e8 +#define CSR_PMPADDR57 0x3e9 +#define CSR_PMPADDR58 0x3ea +#define CSR_PMPADDR59 0x3eb +#define CSR_PMPADDR60 0x3ec +#define CSR_PMPADDR61 0x3ed +#define CSR_PMPADDR62 0x3ee +#define CSR_PMPADDR63 0x3ef +#define CSR_MSECCFG 0x747 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_TINFO 0x7a4 +#define CSR_TCONTROL 0x7a5 +#define CSR_MCONTEXT 0x7a8 +#define CSR_MSCONTEXT 0x7aa +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH0 0x7b2 +#define CSR_DSCRATCH1 0x7b3 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 +#define CSR_MTOPI 0xfb0 +#define CSR_SIEH 0x114 +#define CSR_SIPH 0x154 +#define CSR_STIMECMPH 0x15d +#define CSR_VSIEH 0x214 +#define CSR_VSIPH 0x254 +#define CSR_VSTIMECMPH 0x25d +#define CSR_HTIMEDELTAH 0x615 +#define CSR_HIDELEGH 0x613 +#define CSR_HVIENH 0x618 +#define CSR_HENVCFGH 0x61a +#define CSR_HVIPH 0x655 +#define CSR_HVIPRIO1H 0x656 +#define CSR_HVIPRIO2H 0x657 +#define CSR_HSTATEEN0H 0x61c +#define CSR_HSTATEEN1H 0x61d +#define CSR_HSTATEEN2H 0x61e +#define CSR_HSTATEEN3H 0x61f +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MSTATUSH 0x310 +#define CSR_MIDELEGH 0x313 +#define CSR_MIEH 0x314 +#define CSR_MVIENH 0x318 +#define CSR_MVIPH 0x319 +#define CSR_MENVCFGH 0x31a +#define CSR_MSTATEEN0H 0x31c +#define CSR_MSTATEEN1H 0x31d +#define CSR_MSTATEEN2H 0x31e +#define CSR_MSTATEEN3H 0x31f +#define CSR_MIPH 0x354 +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 +#define CSR_MSECCFGH 0x757 +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + + +#define CSR_MSTATUS_UIE 0x00000001 +#define CSR_MSTATUS_SIE 0x00000002 +#define CSR_MSTATUS_HIE 0x00000004 +#define CSR_MSTATUS_MIE 0x00000008 +#define CSR_MSTATUS_UPIE 0x00000010 +#define CSR_MSTATUS_SPIE 0x00000020 +#define CSR_MSTATUS_UBE 0x00000040 +#define CSR_MSTATUS_MPIE 0x00000080 +#define CSR_MSTATUS_SPP 0x00000100 +#define CSR_MSTATUS_VS 0x00000600 +#define CSR_MSTATUS_MPP 0x00001800 +#define CSR_MSTATUS_FS 0x00006000 +#define CSR_MSTATUS_XS 0x00018000 +#define CSR_MSTATUS_MPRV 0x00020000 +#define CSR_MSTATUS_SUM 0x00040000 +#define CSR_MSTATUS_MXR 0x00080000 +#define CSR_MSTATUS_TVM 0x00100000 +#define CSR_MSTATUS_TW 0x00200000 +#define CSR_MSTATUS_TSR 0x00400000 +#define CSR_MSTATUS32_SD 0x80000000 +#define CSR_MSTATUS_UXL 0x0000000300000000 +#define CSR_MSTATUS_SXL 0x0000000C00000000 +#define CSR_MSTATUS_SBE 0x0000001000000000 +#define CSR_MSTATUS_MBE 0x0000002000000000 +#define CSR_MSTATUS_GVA 0x0000004000000000 +#define CSR_MSTATUS_MPV 0x0000008000000000 +#define CSR_MSTATUS64_SD 0x8000000000000000 + +#define CSR_MSTATUSH_SBE 0x00000010 +#define CSR_MSTATUSH_MBE 0x00000020 +#define CSR_MSTATUSH_GVA 0x00000040 +#define CSR_MSTATUSH_MPV 0x00000080 + +#define CSR_SSTATUS_UIE 0x00000001 +#define CSR_SSTATUS_SIE 0x00000002 +#define CSR_SSTATUS_UPIE 0x00000010 +#define CSR_SSTATUS_SPIE 0x00000020 +#define CSR_SSTATUS_UBE 0x00000040 +#define CSR_SSTATUS_SPP 0x00000100 +#define CSR_SSTATUS_VS 0x00000600 +#define CSR_SSTATUS_FS 0x00006000 +#define CSR_SSTATUS_XS 0x00018000 +#define CSR_SSTATUS_SUM 0x00040000 +#define CSR_SSTATUS_MXR 0x00080000 +#define CSR_SSTATUS32_SD 0x80000000 +#define CSR_SSTATUS_UXL 0x0000000300000000 +#define CSR_SSTATUS64_SD 0x8000000000000000 + +#define CSR_HSTATUS_VSXL 0x300000000 +#define CSR_HSTATUS_VTSR 0x00400000 +#define CSR_HSTATUS_VTW 0x00200000 +#define CSR_HSTATUS_VTVM 0x00100000 +#define CSR_HSTATUS_VGEIN 0x0003f000 +#define CSR_HSTATUS_HU 0x00000200 +#define CSR_HSTATUS_SPVP 0x00000100 +#define CSR_HSTATUS_SPV 0x00000080 +#define CSR_HSTATUS_GVA 0x00000040 +#define CSR_HSTATUS_VSBE 0x00000020 + +#define CSR_USTATUS_UIE 0x00000001 +#define CSR_USTATUS_UPIE 0x00000010 + +#define CSR_MNSTATUS_NMIE 0x00000008 +#define CSR_MNSTATUS_MNPP 0x00001800 +#define CSR_MNSTATUS_MNPV 0x00000080 + +#define CSR_DCSR_XDEBUGVER (3U<<30) +#define CSR_DCSR_NDRESET (1<<29) +#define CSR_DCSR_FULLRESET (1<<28) +#define CSR_DCSR_EBREAKM (1<<15) +#define CSR_DCSR_EBREAKH (1<<14) +#define CSR_DCSR_EBREAKS (1<<13) +#define CSR_DCSR_EBREAKU (1<<12) +#define CSR_DCSR_STOPCYCLE (1<<10) +#define CSR_DCSR_STOPTIME (1<<9) +#define CSR_DCSR_CAUSE (7<<6) +#define CSR_DCSR_DEBUGINT (1<<5) +#define CSR_DCSR_HALT (1<<3) +#define CSR_DCSR_STEP (1<<2) +#define CSR_DCSR_PRV (3<<0) + +#define CSR_DCSR_CAUSE_NONE 0 +#define CSR_DCSR_CAUSE_SWBP 1 +#define CSR_DCSR_CAUSE_HWBP 2 +#define CSR_DCSR_CAUSE_DEBUGINT 3 +#define CSR_DCSR_CAUSE_STEP 4 +#define CSR_DCSR_CAUSE_HALT 5 +#define CSR_DCSR_CAUSE_GROUP 6 + +#define CSR_MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define CSR_MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define CSR_MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define CSR_MCONTROL_SELECT (1<<19) +#define CSR_MCONTROL_TIMING (1<<18) +#define CSR_MCONTROL_ACTION (0x3f<<12) +#define CSR_MCONTROL_CHAIN (1<<11) +#define CSR_MCONTROL_MATCH (0xf<<7) +#define CSR_MCONTROL_M (1<<6) +#define CSR_MCONTROL_H (1<<5) +#define CSR_MCONTROL_S (1<<4) +#define CSR_MCONTROL_U (1<<3) +#define CSR_MCONTROL_EXECUTE (1<<2) +#define CSR_MCONTROL_STORE (1<<1) +#define CSR_MCONTROL_LOAD (1<<0) + +#define CSR_MCONTROL_TYPE_NONE 0 +#define CSR_MCONTROL_TYPE_MATCH 2 + +#define CSR_MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define CSR_MCONTROL_ACTION_DEBUG_MODE 1 +#define CSR_MCONTROL_ACTION_TRACE_START 2 +#define CSR_MCONTROL_ACTION_TRACE_STOP 3 +#define CSR_MCONTROL_ACTION_TRACE_EMIT 4 + +#define CSR_MCONTROL_MATCH_EQUAL 0 +#define CSR_MCONTROL_MATCH_NAPOT 1 +#define CSR_MCONTROL_MATCH_GE 2 +#define CSR_MCONTROL_MATCH_LT 3 +#define CSR_MCONTROL_MATCH_MASK_LOW 4 +#define CSR_MCONTROL_MATCH_MASK_HIGH 5 + +#define CSR_MIP_USIP (1 << IRQ_U_SOFT) +#define CSR_MIP_SSIP (1 << IRQ_S_SOFT) +#define CSR_MIP_VSSIP (1 << IRQ_VS_SOFT) +#define CSR_MIP_MSIP (1 << IRQ_M_SOFT) +#define CSR_MIP_UTIP (1 << IRQ_U_TIMER) +#define CSR_MIP_STIP (1 << IRQ_S_TIMER) +#define CSR_MIP_VSTIP (1 << IRQ_VS_TIMER) +#define CSR_MIP_MTIP (1 << IRQ_M_TIMER) +#define CSR_MIP_UEIP (1 << IRQ_U_EXT) +#define CSR_MIP_SEIP (1 << IRQ_S_EXT) +#define CSR_MIP_VSEIP (1 << IRQ_VS_EXT) +#define CSR_MIP_MEIP (1 << IRQ_M_EXT) +#define CSR_MIP_SGEIP (1 << IRQ_S_GEXT) +#define CSR_MIP_LCOFIP (1 << IRQ_LCOF) + +#define CSR_MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) +#define CSR_MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define CSR_MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) + +#define CSR_MIDELEG_FORCED_MASK MIP_HS_MASK + +#define CSR_SIP_SSIP MIP_SSIP +#define CSR_SIP_STIP MIP_STIP + +#define CSR_MENVCFG_FIOM 0x00000001 +#define CSR_MENVCFG_CBIE 0x00000030 +#define CSR_MENVCFG_CBCFE 0x00000040 +#define CSR_MENVCFG_CBZE 0x00000080 +#define CSR_MENVCFG_HADE 0x2000000000000000 +#define CSR_MENVCFG_PBMTE 0x4000000000000000 +#define CSR_MENVCFG_STCE 0x8000000000000000 + +#define CSR_MENVCFGH_HADE 0x20000000 +#define CSR_MENVCFGH_PBMTE 0x40000000 +#define CSR_MENVCFGH_STCE 0x80000000 + +#define CSR_MSTATEEN0_CS 0x00000001 +#define CSR_MSTATEEN0_FCSR 0x00000002 +#define CSR_MSTATEEN0_JVT 0x00000004 +#define CSR_MSTATEEN0_HCONTEXT 0x0200000000000000 +#define CSR_MSTATEEN0_HENVCFG 0x4000000000000000 +#define CSR_MSTATEEN_HSTATEEN 0x8000000000000000 + +#define CSR_MSTATEEN0H_HCONTEXT 0x02000000 +#define CSR_MSTATEEN0H_HENVCFG 0x40000000 +#define CSR_MSTATEENH_HSTATEEN 0x80000000 + +#define CSR_MHPMEVENT_VUINH 0x0400000000000000 +#define CSR_MHPMEVENT_VSINH 0x0800000000000000 +#define CSR_MHPMEVENT_UINH 0x1000000000000000 +#define CSR_MHPMEVENT_SINH 0x2000000000000000 +#define CSR_MHPMEVENT_MINH 0x4000000000000000 +#define CSR_MHPMEVENT_OF 0x8000000000000000 + +#define CSR_MHPMEVENTH_VUINH 0x04000000 +#define CSR_MHPMEVENTH_VSINH 0x08000000 +#define CSR_MHPMEVENTH_UINH 0x10000000 +#define CSR_MHPMEVENTH_SINH 0x20000000 +#define CSR_MHPMEVENTH_MINH 0x40000000 +#define CSR_MHPMEVENTH_OF 0x80000000 + +#define CSR_HENVCFG_FIOM 0x00000001 +#define CSR_HENVCFG_CBIE 0x00000030 +#define CSR_HENVCFG_CBCFE 0x00000040 +#define CSR_HENVCFG_CBZE 0x00000080 +#define CSR_HENVCFG_HADE 0x2000000000000000 +#define CSR_HENVCFG_PBMTE 0x4000000000000000 +#define CSR_HENVCFG_STCE 0x8000000000000000 + +#define CSR_HENVCFGH_HADE 0x20000000 +#define CSR_HENVCFGH_PBMTE 0x40000000 +#define CSR_HENVCFGH_STCE 0x80000000 + +#define CSR_HSTATEEN0_CS 0x00000001 +#define CSR_HSTATEEN0_FCSR 0x00000002 +#define CSR_HSTATEEN0_JVT 0x00000004 +#define CSR_HSTATEEN0_SCONTEXT 0x0200000000000000 +#define CSR_HSTATEEN0_SENVCFG 0x4000000000000000 +#define CSR_HSTATEEN_SSTATEEN 0x8000000000000000 + +#define CSR_HSTATEEN0H_SCONTEXT 0x02000000 +#define CSR_HSTATEEN0H_SENVCFG 0x40000000 +#define CSR_HSTATEENH_SSTATEEN 0x80000000 + +#define CSR_SENVCFG_FIOM 0x00000001 +#define CSR_SENVCFG_CBIE 0x00000030 +#define CSR_SENVCFG_CBCFE 0x00000040 +#define CSR_SENVCFG_CBZE 0x00000080 + +#define CSR_SSTATEEN0_CS 0x00000001 +#define CSR_SSTATEEN0_FCSR 0x00000002 +#define CSR_SSTATEEN0_JVT 0x00000004 + +#define CSR_MSECCFG_MML 0x00000001 +#define CSR_MSECCFG_MMWP 0x00000002 +#define CSR_MSECCFG_RLB 0x00000004 +#define CSR_MSECCFG_USEED 0x00000100 +#define CSR_MSECCFG_SSEED 0x00000200 + +/* jvt fields */ +#define CSR_JVT_MODE 0x3F +#define CSR_JVT_BASE (~0x3F) + +#define CSR_PRV_U 0 +#define CSR_PRV_S 1 +#define CSR_PRV_M 3 + +#define CSR_PRV_HS (PRV_S + 1) + +#define CSR_SATP32_MODE 0x80000000 +#define CSR_SATP32_ASID 0x7FC00000 +#define CSR_SATP32_PPN 0x003FFFFF +#define CSR_SATP64_MODE 0xF000000000000000 +#define CSR_SATP64_ASID 0x0FFFF00000000000 +#define CSR_SATP64_PPN 0x00000FFFFFFFFFFF + +#define CSR_SATP_MODE_OFF 0 +#define CSR_SATP_MODE_SV32 1 +#define CSR_SATP_MODE_SV39 8 +#define CSR_SATP_MODE_SV48 9 +#define CSR_SATP_MODE_SV57 10 +#define CSR_SATP_MODE_SV64 11 + +#define CSR_HGATP32_MODE 0x80000000 +#define CSR_HGATP32_VMID 0x1FC00000 +#define CSR_HGATP32_PPN 0x003FFFFF + +#define CSR_HGATP64_MODE 0xF000000000000000 +#define CSR_HGATP64_VMID 0x03FFF00000000000 +#define CSR_HGATP64_PPN 0x00000FFFFFFFFFFF + +#define CSR_HGATP_MODE_OFF 0 +#define CSR_HGATP_MODE_SV32X4 1 +#define CSR_HGATP_MODE_SV39X4 8 +#define CSR_HGATP_MODE_SV48X4 9 +#define CSR_HGATP_MODE_SV57X4 10 + +#define CSR_PMP_R 0x01 +#define CSR_PMP_W 0x02 +#define CSR_PMP_X 0x04 +#define CSR_PMP_A 0x18 +#define CSR_PMP_L 0x80 +#define CSR_PMP_SHIFT 2 + +#define CSR_PMP_TOR 0x08 +#define CSR_PMP_NA4 0x10 +#define CSR_PMP_NAPOT 0x18 + +#define CSR_IRQ_U_SOFT 0 +#define CSR_IRQ_S_SOFT 1 +#define CSR_IRQ_VS_SOFT 2 +#define CSR_IRQ_M_SOFT 3 +#define CSR_IRQ_U_TIMER 4 +#define CSR_IRQ_S_TIMER 5 +#define CSR_IRQ_VS_TIMER 6 +#define CSR_IRQ_M_TIMER 7 +#define CSR_IRQ_U_EXT 8 +#define CSR_IRQ_S_EXT 9 +#define CSR_IRQ_VS_EXT 10 +#define CSR_IRQ_M_EXT 11 +#define CSR_IRQ_S_GEXT 12 +#define CSR_IRQ_COP 12 +#define CSR_IRQ_LCOF 13 + +/* page table entry (PTE) fields */ +#define CSR_PTE_V 0x001 /* Valid */ +#define CSR_PTE_R 0x002 /* Read */ +#define CSR_PTE_W 0x004 /* Write */ +#define CSR_PTE_X 0x008 /* Execute */ +#define CSR_PTE_U 0x010 /* User */ +#define CSR_PTE_G 0x020 /* Global */ +#define CSR_PTE_A 0x040 /* Accessed */ +#define CSR_PTE_D 0x080 /* Dirty */ +#define CSR_PTE_SOFT 0x300 /* Reserved for Software */ +#define CSR_PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ +#define CSR_PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ +#define CSR_PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ +#define CSR_PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ + +#define CSR_PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + + +#endif + +#endif diff --git a/cv32e20/bsp/link.ld b/cv32e20/bsp/link.ld index bac16cd15d..e7cfe8bf16 100644 --- a/cv32e20/bsp/link.ld +++ b/cv32e20/bsp/link.ld @@ -58,7 +58,7 @@ SECTIONS KEEP (*(.text.start)) } >ram -/* CORE-V: interrupt vectors */ + /* CORE-V: interrupt vectors */ .vectors : ALIGN(256) { PROVIDE(__vector_start = .); @@ -119,6 +119,19 @@ SECTIONS { KEEP (*(SORT_NONE(.fini))) } >ram + + /* tohost symbol to detect end-of-test */ + .tohost : ALIGN (256) + { + *(.tohost); + } >ram + + /* tohost symbol to detect end-of-test */ + .stdout_reg : ALIGN (256) + { + *(.stdout_reg); + } >ram + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); diff --git a/cv32e20/bsp/syscalls.c b/cv32e20/bsp/syscalls.c index ac35737f85..df4824c9f3 100644 --- a/cv32e20/bsp/syscalls.c +++ b/cv32e20/bsp/syscalls.c @@ -19,361 +19,26 @@ * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#undef errno -extern int errno; - -/* write to this reg for outputting strings */ -#define STDOUT_REG 0x10000000 -/* write test result of program to this reg */ -#define RESULT_REG 0x20000000 -/* write exit value of program to this reg */ -#define EXIT_REG 0x20000004 - -#define STDOUT_FILENO 1 - -/* It turns out that older newlib versions use different symbol names which goes - * against newlib recommendations. Anyway this is fixed in later version. - */ -#if __NEWLIB__ <= 2 && __NEWLIB_MINOR__ <= 5 -#define _sbrk sbrk -#define _write write -#define _close close -#define _lseek lseek -#define _read read -#define _fstat fstat -#define _isatty isatty -#endif -/* Upstream newlib now defines this in libgloss/riscv/internal_syscall.h. */ -long -__syscall_error(long a0) -{ - errno = -a0; - return -1; -} - -void unimplemented_syscall() -{ - const char *p = "BSP: Unimplemented system call called!\n"; - while (*p) - *(volatile int *)STDOUT_REG = *(p++); -} - -int nanosleep(const struct timespec *rqtp, struct timespec *rmtp) -{ - errno = ENOSYS; - return -1; -} - -int _access(const char *file, int mode) -{ - errno = ENOSYS; - return -1; -} - -int _chdir(const char *path) -{ - errno = ENOSYS; - return -1; -} - -int _chmod(const char *path, mode_t mode) -{ - errno = ENOSYS; - return -1; -} - -int _chown(const char *path, uid_t owner, gid_t group) -{ - errno = ENOSYS; - return -1; -} - -int _close(int file) -{ - return -1; -} - -int _execve(const char *name, char *const argv[], char *const env[]) -{ - errno = ENOMEM; - return -1; -} - -void _exit(int exit_status) -{ - *(volatile int *)EXIT_REG = exit_status; - asm volatile("wfi"); - /* _exit should not return */ - while (1) {}; -} - -int _faccessat(int dirfd, const char *file, int mode, int flags) -{ - errno = ENOSYS; - return -1; -} - -int _fork(void) -{ - errno = EAGAIN; - return -1; -} - -int _fstat(int file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; - // errno = -ENOSYS; - // return -1; -} - -int _fstatat(int dirfd, const char *file, struct stat *st, int flags) -{ - errno = ENOSYS; - return -1; -} - -int _ftime(struct timeb *tp) -{ - errno = ENOSYS; - return -1; -} - -char *_getcwd(char *buf, size_t size) -{ - errno = -ENOSYS; - return NULL; -} - -int _getpid() -{ - return 1; -} - -int _gettimeofday(struct timeval *tp, void *tzp) -{ - errno = -ENOSYS; - return -1; -} - -int _isatty(int file) -{ - return (file == STDOUT_FILENO); -} - -int _kill(int pid, int sig) -{ - errno = EINVAL; - return -1; -} - -int _link(const char *old_name, const char *new_name) -{ - errno = EMLINK; - return -1; -} - -off_t _lseek(int file, off_t ptr, int dir) -{ - return 0; -} - -int _lstat(const char *file, struct stat *st) -{ - errno = ENOSYS; - return -1; -} - -int _open(const char *name, int flags, int mode) -{ - return -1; -} - -int _openat(int dirfd, const char *name, int flags, int mode) -{ - errno = ENOSYS; - return -1; -} - -ssize_t _read(int file, void *ptr, size_t len) -{ - return 0; -} - -int _stat(const char *file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; - // errno = ENOSYS; - // return -1; -} - -long _sysconf(int name) -{ - - return -1; -} - -clock_t _times(struct tms *buf) -{ - return -1; -} - -int _unlink(const char *name) -{ - errno = ENOENT; - return -1; -} - -int _utime(const char *path, const struct utimbuf *times) -{ - errno = ENOSYS; - return -1; -} - -int _wait(int *status) -{ - errno = ECHILD; - return -1; -} - -ssize_t _write(int file, const void *ptr, size_t len) -{ - const char *cptr = (char *)ptr; - if (file != STDOUT_FILENO) - { - errno = ENOSYS; - return -1; - } - - const void *eptr = cptr + len; - while (cptr != eptr) - *(volatile int *)STDOUT_REG = *cptr++; - return len; -} - -extern char __heap_start[]; -extern char __heap_end[]; -static char *brk = __heap_start; - -int _brk(void *addr) -{ - brk = addr; - return 0; -} - -void *_sbrk(ptrdiff_t incr) -{ - char *old_brk = brk; - register long sp asm("sp"); - - char *new_brk = brk += incr; - if (new_brk < (char *) sp && new_brk < __heap_end) - { - brk = new_brk; - - return old_brk; - } - else - { - errno = ENOMEM; - return (void *) -1; - } -} - -void handle_syscall (long a0, - long a1, - long a2, - long a3, - __attribute__((unused)) long a4, - __attribute__((unused)) long a5, - __attribute__((unused)) long a6, - long a7) { - #ifdef __riscv_32e - register long syscall_id asm("t0"); - #else - long syscall_id = a7; - #endif - - switch (syscall_id) { - case SYS_exit: - _exit (a0); - break; - case SYS_read: - _read (a0, (void *) a1, a2); - break; - case SYS_write: - _write (a0, (const void *) a1, a2); - break; - case SYS_getpid: - _getpid (); - break; - case SYS_kill: - _kill (a0, a1); - break; - case SYS_open: - _open ((const char *) a0, a1, a2); - break; - case SYS_openat: - _openat (a0, (const char *) a1, a2, a3); - break; - case SYS_close: - _close (a0); - break; - case SYS_lseek: - _lseek (a0, a1, a2); - break; - case SYS_brk: - _brk ((void *) a0); - break; - case SYS_link: - _link ((const char *) a0, (const char *) a1); - break; - case SYS_unlink: - _unlink ((const char *) a0); - break; - case SYS_chdir: - _chdir ((const char *) a0); - break; - case SYS_getcwd: - _getcwd ((char *) a0, a1); - break; - case SYS_stat: - _stat ((const char *) a0, (struct stat *) a1); - break; - case SYS_fstat: - _fstat (a0, (struct stat *) a1); - break; - case SYS_lstat: - _lstat ((const char *) a0, (struct stat *) a1); - break; - case SYS_fstatat: - _fstatat (a0, (const char *) a1, (struct stat *) a2, a3); - break; - case SYS_access: - _access ((const char *) a0, a1); - break; - case SYS_faccessat: - _faccessat (a0, (const char *) a1, a2, a3); - break; - case SYS_gettimeofday: - _gettimeofday ((struct timeval *) a0, (void *) a1); - break; - case SYS_times: - _times ((struct tms *) a0); - break; - default: - unimplemented_syscall (); - break; - } +#include "syscalls.h" + +void exit(int value) { + asm inline(" \ + mv a7, %0; \ + mv t0, %0; \ + mv a0, %1; \ + ecall;" + : + : "r"(SYS_exit), "r"(value)); +} + +int execve(const char *name, char *const argv[], char *const env[]) { + asm inline(" \ + mv a7, %0; \ + mv t0, %0; \ + mv a0, %1; \ + mv a1, %2; \ + mv a2, %3; \ + ecall;" + : + : "r"(SYS_execve), "r"(name), "r"(argv), "r"(env)); } diff --git a/cv32e20/bsp/syscalls.h b/cv32e20/bsp/syscalls.h new file mode 100644 index 0000000000..a2e5d1414d --- /dev/null +++ b/cv32e20/bsp/syscalls.h @@ -0,0 +1,42 @@ +#ifndef SYSCALLS_H +#define SYSCALLS_H +#include "csr.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#undef errno + +extern int errno; +extern volatile uint64_t tohost; +extern volatile uint64_t fromhost; + +extern volatile uint64_t stdout_reg; + +#define STDOUT_FILENO 1 + +/* It turns out that older newlib versions use different symbol names which goes + * against newlib recommendations. Anyway this is fixed in later version. + */ +#if __NEWLIB__ <= 2 && __NEWLIB_MINOR__ <= 5 +#define _sbrk sbrk +#define _write write +#define _close close +#define _lseek lseek +#define _read read +#define _fstat fstat +#define _isatty isatty +#endif + +#ifndef SYS_execve +#define SYS_execve 59 +#endif + +void exit(int value); + +#endif diff --git a/cv32e20/bsp/syscalls_kernel.c b/cv32e20/bsp/syscalls_kernel.c new file mode 100644 index 0000000000..7644fdbc07 --- /dev/null +++ b/cv32e20/bsp/syscalls_kernel.c @@ -0,0 +1,300 @@ +// Copyright (c) 2021 OpenHW Group +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +/* An extremely minimalist syscalls.c for newlib + * Based on riscv newlib libgloss/riscv/sys_*.c + * + * Copyright 2019 Claire Wolf + * Copyright 2019 ETH Zürich and University of Bologna + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "syscalls.h" + +volatile uint64_t tohost __attribute__((section(".tohost"))) = 0; +volatile uint64_t fromhost __attribute__((section(".tohost"))) = 0; +volatile uint64_t stdout_reg __attribute__((section(".stdout_reg"))) = 0; + +/* Upstream newlib now defines this in libgloss/riscv/internal_syscall.h. */ +long __syscall_error(long a0) { + errno = -a0; + return -1; +} + +void unimplemented_syscall() { + const char *p = "BSP: Unimplemented system call called!\n"; + while (*p) + stdout_reg = *(p++); +} + +int nanosleep(const struct timespec *rqtp, struct timespec *rmtp) { + errno = ENOSYS; + return -1; +} + +int _access(const char *file, int mode) { + errno = ENOSYS; + return -1; +} + +int _chdir(const char *path) { + errno = ENOSYS; + return -1; +} + +int _chmod(const char *path, mode_t mode) { + errno = ENOSYS; + return -1; +} + +int _chown(const char *path, uid_t owner, gid_t group) { + errno = ENOSYS; + return -1; +} + +int _close(int file) { return -1; } + +int _execve(const char *name, char *const argv[], char *const env[]) { + if (name == "return_to_machine") { + { + printf("Returning to Machine"); + csr_set_mask(mstatus, CSR_MSTATUS_MPP, PRIV_M); + } + } + return 0; +} + +void _exit(int exit_status) { + tohost = (exit_status << 1) | 1; + + asm volatile("wfi"); + /* _exit should not return */ + while (1) { + }; +} + +int _faccessat(int dirfd, const char *file, int mode, int flags) { + errno = ENOSYS; + return -1; +} + +int _fork(void) { + errno = EAGAIN; + return -1; +} + +int _fstat(int file, struct stat *st) { + st->st_mode = S_IFCHR; + return 0; + // errno = -ENOSYS; + // return -1; +} + +int _fstatat(int dirfd, const char *file, struct stat *st, int flags) { + errno = ENOSYS; + return -1; +} + +int _ftime(struct timeb *tp) { + errno = ENOSYS; + return -1; +} + +char *_getcwd(char *buf, size_t size) { + errno = -ENOSYS; + return NULL; +} + +int _getpid() { return 1; } + +int _gettimeofday(struct timeval *tp, void *tzp) { + errno = -ENOSYS; + return -1; +} + +int _isatty(int file) { return (file == STDOUT_FILENO); } + +int _kill(int pid, int sig) { + errno = EINVAL; + return -1; +} + +int _link(const char *old_name, const char *new_name) { + errno = EMLINK; + return -1; +} + +off_t _lseek(int file, off_t ptr, int dir) { return 0; } + +int _lstat(const char *file, struct stat *st) { + errno = ENOSYS; + return -1; +} + +int _open(const char *name, int flags, int mode) { return -1; } + +int _openat(int dirfd, const char *name, int flags, int mode) { + errno = ENOSYS; + return -1; +} + +ssize_t _read(int file, void *ptr, size_t len) { return 0; } + +int _stat(const char *file, struct stat *st) { + st->st_mode = S_IFCHR; + return 0; + // errno = ENOSYS; + // return -1; +} + +long _sysconf(int name) { return -1; } + +clock_t _times(struct tms *buf) { return -1; } + +int _unlink(const char *name) { + errno = ENOENT; + return -1; +} + +int _utime(const char *path, const struct utimbuf *times) { + errno = ENOSYS; + return -1; +} + +int _wait(int *status) { + errno = ECHILD; + return -1; +} + +ssize_t _write(int file, const void *ptr, size_t len) { + const char *cptr = (char *)ptr; + if (file != STDOUT_FILENO) { + errno = ENOSYS; + return -1; + } + + const void *eptr = cptr + len; + while (cptr != eptr) + stdout_reg = *cptr++; + return len; +} + +extern char __heap_start[]; +extern char __heap_end[]; +static char *brk = __heap_start; + +int _brk(void *addr) { + brk = addr; + return 0; +} + +void *_sbrk(ptrdiff_t incr) { + char *old_brk = brk; + register long sp asm("sp"); + + char *new_brk = brk += incr; + if (new_brk < (char *)sp && new_brk < __heap_end) { + brk = new_brk; + + return old_brk; + } else { + errno = ENOMEM; + return (void *)-1; + } +} + +void handle_syscall(long a0, long a1, long a2, long a3, + __attribute__((unused)) long a4, + __attribute__((unused)) long a5, + __attribute__((unused)) long a6, long a7) { +#ifdef __riscv_32e + register long syscall_id asm("t0"); +#else + long syscall_id = a7; +#endif + + switch (syscall_id) { + case SYS_exit: + _exit(a0); + break; + case SYS_read: + _read(a0, (void *)a1, a2); + break; + case SYS_write: + _write(a0, (const void *)a1, a2); + break; + case SYS_getpid: + _getpid(); + break; + case SYS_kill: + _kill(a0, a1); + break; + case SYS_open: + _open((const char *)a0, a1, a2); + break; + case SYS_openat: + _openat(a0, (const char *)a1, a2, a3); + break; + case SYS_close: + _close(a0); + break; + case SYS_lseek: + _lseek(a0, a1, a2); + break; + case SYS_brk: + _brk((void *)a0); + break; + case SYS_link: + _link((const char *)a0, (const char *)a1); + break; + case SYS_unlink: + _unlink((const char *)a0); + break; + case SYS_chdir: + _chdir((const char *)a0); + break; + case SYS_getcwd: + _getcwd((char *)a0, a1); + break; + case SYS_stat: + _stat((const char *)a0, (struct stat *)a1); + break; + case SYS_fstat: + _fstat(a0, (struct stat *)a1); + break; + case SYS_lstat: + _lstat((const char *)a0, (struct stat *)a1); + break; + case SYS_fstatat: + _fstatat(a0, (const char *)a1, (struct stat *)a2, a3); + break; + case SYS_access: + _access((const char *)a0, a1); + break; + case SYS_faccessat: + _faccessat(a0, (const char *)a1, a2, a3); + break; + case SYS_gettimeofday: + _gettimeofday((struct timeval *)a0, (void *)a1); + break; + case SYS_times: + _times((struct tms *)a0); + break; + case SYS_execve: + _execve((const char *)a0, (char *const)a1, (char *const)a2); + break; + default: + unimplemented_syscall(); + break; + } +} diff --git a/cv32e20/env/corev-dv/cv32e20_instr_gen_config.sv b/cv32e20/env/corev-dv/cv32e20_instr_gen_config.sv index 62e4447f80..de8481947a 100644 --- a/cv32e20/env/corev-dv/cv32e20_instr_gen_config.sv +++ b/cv32e20/env/corev-dv/cv32e20_instr_gen_config.sv @@ -42,7 +42,7 @@ class cv32e20_instr_gen_config extends riscv_instr_gen_config; // Debug pointer may not be the return address, stack pointer, nor thread pointer if (!gen_debug_section) { dp == ZERO; - } else { + } else { !(dp inside {sp, tp, ra, scratch_reg, GP, RA, ZERO}); foreach (gpr[i]) { !(gpr[i] inside {dp}); @@ -64,15 +64,19 @@ class cv32e20_instr_gen_config extends riscv_instr_gen_config; }; } + constraint scratch_reg_c_not_zero { + scratch_reg != ZERO; + } + constraint fast_intr_handler_c { if (!enable_fast_interrupt_handler) { knob_zero_fast_intr_handlers == 1; } - + // Nver use fast handler for exceptions (interrupt 0) use_fast_intr_handler[0] == 0; - knob_zero_fast_intr_handlers -> !use_fast_intr_handler; + knob_zero_fast_intr_handlers -> !use_fast_intr_handler; // VECTORED mode required for any fast interrupts if (use_fast_intr_handler) { @@ -86,7 +90,7 @@ class cv32e20_instr_gen_config extends riscv_instr_gen_config; `uvm_field_enum(riscv_reg_t, dp, UVM_DEFAULT) `uvm_field_enum(riscv_reg_t, scratch_reg, UVM_DEFAULT) `uvm_field_int(enable_fast_interrupt_handler, UVM_DEFAULT) - `uvm_field_int(use_fast_intr_handler, UVM_DEFAULT) + `uvm_field_int(use_fast_intr_handler, UVM_DEFAULT) `uvm_object_utils_end function new(string name=""); @@ -105,13 +109,13 @@ class cv32e20_instr_gen_config extends riscv_instr_gen_config; // In the debug ROM some combinations are not valid because they use the same register (dscratch0) if (gen_debug_section) begin - if ((enable_ebreak_in_debug_rom || set_dcsr_ebreak) && + if ((enable_ebreak_in_debug_rom || set_dcsr_ebreak) && enable_debug_single_step) begin - `uvm_fatal("CVINSTGENCFG", + `uvm_fatal("CVINSTGENCFG", $sformatf("Illegal combination of debug plusargs: enable_ebreak_in_debug_rom = %0d, set_dcsr_ebreakl = %0d, enable_debug_single_step = %0d", enable_ebreak_in_debug_rom, set_dcsr_ebreak, enable_debug_single_step)) end - end + end endfunction : post_randomize endclass : cv32e20_instr_gen_config diff --git a/cv32e20/env/uvme/uvme_cv32e20_cfg.sv b/cv32e20/env/uvme/uvme_cv32e20_cfg.sv index ac2f5ddb08..70ae61bb1e 100644 --- a/cv32e20/env/uvme/uvme_cv32e20_cfg.sv +++ b/cv32e20/env/uvme/uvme_cv32e20_cfg.sv @@ -46,6 +46,16 @@ class uvme_cv32e20_cfg_c extends uvm_object; rand uvma_obi_memory_cfg_c obi_memory_instr_cfg; rand uvma_obi_memory_cfg_c obi_memory_data_cfg; + longint unsigned vp_virtual_printer_symbol = 32'h1000_0000; + longint unsigned vp_virtual_printer_legacy = 32'h1000_0000; + longint unsigned vp_rand_num = 32'h1500_1000; + longint unsigned vp_cycle_counter = 32'h1500_1004; + longint unsigned vp_sig_writer = 32'h2000_0008; + longint unsigned vp_status_flags_symbol = 32'h2000_0000; + longint unsigned vp_status_flags_legacy = 32'h2000_0000; + longint unsigned vp_interrupt_timer = 32'h1500_0000; + longint unsigned vp_debug_control = 32'h1500_0008; + // Objects // TODO Add scoreboard configuration handles // Ex: rand uvml_sb_cfg_c sb_egress_cfg; diff --git a/cv32e20/env/uvme/uvme_cv32e20_env.sv b/cv32e20/env/uvme/uvme_cv32e20_env.sv index f90d4090bf..c919866cea 100644 --- a/cv32e20/env/uvme/uvme_cv32e20_env.sv +++ b/cv32e20/env/uvme/uvme_cv32e20_env.sv @@ -26,6 +26,8 @@ typedef class uvme_cv32e20_vp_sig_writer_seq_c; typedef class uvme_cv32e20_vp_status_flags_seq_c; typedef class uvme_cv32e20_vp_rand_num_seq_c; +import "DPI-C" function longint read_symbol(input string symbol, output longint unsigned address); +import "DPI-C" function read_elf(input string filename); /** * Top-level component that encapsulates, builds and connects all other * CV32E20 environment components. @@ -49,7 +51,8 @@ class uvme_cv32e20_env_c extends uvm_env; uvma_obi_memory_agent_c obi_memory_instr_agent; uvma_obi_memory_agent_c obi_memory_data_agent ; - + byte vp_status_flags_symbol_present = 0; + byte vp_virtual_printer_symbol_present = 0; `uvm_component_utils_begin(uvme_cv32e20_env_c) `uvm_field_object(cfg , UVM_DEFAULT) @@ -142,6 +145,11 @@ class uvme_cv32e20_env_c extends uvm_env; */ extern virtual function void assemble_vsequencer(); + /** + * Load binary into elfloader to enable aux functions + */ + extern virtual function void load_binary(); + endclass : uvme_cv32e20_env_c @@ -181,6 +189,7 @@ function void uvme_cv32e20_env_c::build_phase(uvm_phase phase); create_env_components(); if (cfg.is_active) begin + load_binary(); create_vsequencer(); end @@ -242,15 +251,18 @@ task uvme_cv32e20_env_c::run_phase(uvm_phase phase); data_slv_seq = uvma_obi_memory_slv_seq_c::type_id::create("data_slv_seq"); // Install the virtual peripheral registers - void'(data_slv_seq.register_vp_vseq("vp_virtual_printer", 32'h1000_0000, uvma_obi_memory_vp_virtual_printer_seq_c::get_type())); - void'(data_slv_seq.register_vp_vseq("vp_cycle_counter", 32'h1500_1004, uvma_obi_memory_vp_cycle_counter_seq_c::get_type())); + void'(data_slv_seq.register_vp_vseq("vp_virtual_printer_legacy", cfg.vp_virtual_printer_legacy, uvma_obi_memory_vp_virtual_printer_seq_c::get_type())); + if (vp_virtual_printer_symbol_present) + void'(data_slv_seq.register_vp_vseq("vp_virtual_printer_symbol", cfg.vp_virtual_printer_symbol, uvma_obi_memory_vp_virtual_printer_seq_c::get_type())); + + void'(data_slv_seq.register_vp_vseq("vp_cycle_counter", cfg.vp_cycle_counter, uvma_obi_memory_vp_cycle_counter_seq_c::get_type())); // FIXME:strichmo:When RVVI/RVFI ported, the core-specific random number sequence is no longer needed // Use this one instead: //void'(data_slv_seq.register_vp_vseq("vp_rand_num", 32'h1500_1000, 1, uvma_obi_memory_vp_rand_num_seq_c::get_type())); begin uvme_cv32e20_vp_rand_num_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_rand_num", 32'h1500_1000, uvme_cv32e20_vp_rand_num_seq_c::get_type()))) begin + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_rand_num", cfg.vp_rand_num, uvme_cv32e20_vp_rand_num_seq_c::get_type()))) begin `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_rand_num correctly")); end vp_seq.cv32e20_cntxt = cntxt; @@ -258,15 +270,27 @@ task uvme_cv32e20_env_c::run_phase(uvm_phase phase); begin uvme_cv32e20_vp_sig_writer_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_sig_writer", 32'h2000_0008, uvme_cv32e20_vp_sig_writer_seq_c::get_type()))) begin + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_sig_writer", cfg.vp_sig_writer, uvme_cv32e20_vp_sig_writer_seq_c::get_type()))) begin `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_sig_writes correctly")); end vp_seq.cv32e20_cntxt = cntxt; end + begin + if (vp_status_flags_symbol_present) begin + uvme_cv32e20_vp_status_flags_seq_c vp_seq; + `uvm_info("CV32E20VPSEQ", $sformatf("Setting up vp_status with addr %h", cfg.vp_status_flags_symbol), UVM_LOW) + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_status_flags", cfg.vp_status_flags_symbol, uvme_cv32e20_vp_status_flags_seq_c::get_type()))) begin + `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_status_flags correctly")); + end + vp_seq.cv32e20_cntxt = cntxt; + end + end + begin uvme_cv32e20_vp_status_flags_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_status_flags", 32'h2000_0000, uvme_cv32e20_vp_status_flags_seq_c::get_type()))) begin + `uvm_info("CV32E20VPSEQ", $sformatf("Setting up vp_status with addr %h", cfg.vp_status_flags_legacy), UVM_LOW) + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_status_flags", cfg.vp_status_flags_legacy, uvme_cv32e20_vp_status_flags_seq_c::get_type()))) begin `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_status_flags correctly")); end vp_seq.cv32e20_cntxt = cntxt; @@ -274,7 +298,7 @@ task uvme_cv32e20_env_c::run_phase(uvm_phase phase); begin uvme_cv32e20_vp_interrupt_timer_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_interrupt_timer", 32'h1500_0000, uvme_cv32e20_vp_interrupt_timer_seq_c::get_type()))) begin + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_interrupt_timer", cfg.vp_interrupt_timer, uvme_cv32e20_vp_interrupt_timer_seq_c::get_type()))) begin `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_interrupt_timer correctly")); end vp_seq.cv32e20_cntxt = cntxt; @@ -282,7 +306,7 @@ task uvme_cv32e20_env_c::run_phase(uvm_phase phase); begin uvme_cv32e20_vp_debug_control_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_debug_control", 32'h1500_0008, uvme_cv32e20_vp_debug_control_seq_c::get_type()))) begin + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_debug_control", cfg.vp_debug_control, uvme_cv32e20_vp_debug_control_seq_c::get_type()))) begin `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_debug_control correctly")); end vp_seq.cv32e20_cntxt = cntxt; @@ -449,5 +473,36 @@ function void uvme_cv32e20_env_c::assemble_vsequencer(); endfunction: assemble_vsequencer +function void uvme_cv32e20_env_c::load_binary(); + + string binary; + + $value$plusargs("vp_virtual_printer_legacy=%0h", cfg.vp_virtual_printer_legacy); + $value$plusargs("vp_rand_num=%0h", cfg.vp_rand_num); + $value$plusargs("vp_cycle_counter=%0h", cfg.vp_cycle_counter); + $value$plusargs("vp_sig_writer=%0h", cfg.vp_sig_writer); + $value$plusargs("vp_status_flags_legacy=%0h", cfg.vp_status_flags_legacy); + $value$plusargs("vp_interrupt_timer=%0h",cfg.vp_interrupt_timer); + $value$plusargs("vp_debug_control=%0h", cfg.vp_debug_control); + + if ($value$plusargs("elf_file=%s", binary)) + begin + read_elf(binary); + vp_status_flags_symbol_present = ! read_symbol("tohost", cfg.vp_status_flags_symbol); + if (vp_status_flags_symbol_present) begin + `uvm_info("cv32e20_env", $sformatf("Loading tohost symbol: %h", cfg.vp_status_flags_symbol), UVM_LOW) + end else begin + `uvm_info("cv32e20_env", "tohost symbol not present" , UVM_LOW) + end + vp_virtual_printer_symbol_present = ! read_symbol("stdout_reg", cfg.vp_virtual_printer_symbol); + if (vp_virtual_printer_symbol_present) begin + `uvm_info("cv32e20_env", $sformatf("Loading stdout_reg symbol: %h", cfg.vp_virtual_printer_symbol), UVM_LOW) + end else begin + `uvm_info("cv32e20_env", "stdout_reg symbol not present" , UVM_LOW) + end + end + +endfunction: load_binary + `endif // __UVME_CV32E20_ENV_SV__ diff --git a/cv32e20/env/uvme/vseq/uvme_cv32e20_vp_status_flags_seq.sv b/cv32e20/env/uvme/vseq/uvme_cv32e20_vp_status_flags_seq.sv index 66bf2c7bc7..447e2c3671 100644 --- a/cv32e20/env/uvme/vseq/uvme_cv32e20_vp_status_flags_seq.sv +++ b/cv32e20/env/uvme/vseq/uvme_cv32e20_vp_status_flags_seq.sv @@ -1,27 +1,27 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Silicon Labs // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVME_CV32E20_VP_STATUS_FLAGS_SEQ_SV__ `define __UVME_CV32E20_VP_STATUS_FLAGS_SEQ_SV__ /** - * Sequence implementing the virtual status flags decoding + * Sequence implementing the virtual status flags decoding */ class uvme_cv32e20_vp_status_flags_seq_c extends uvma_obi_memory_vp_base_seq_c; @@ -31,7 +31,7 @@ class uvme_cv32e20_vp_status_flags_seq_c extends uvma_obi_memory_vp_base_seq_c; `uvm_object_utils_begin(uvme_cv32e20_vp_status_flags_seq_c) `uvm_object_utils_end - + /** * Default constructor. */ @@ -55,9 +55,9 @@ class uvme_cv32e20_vp_status_flags_seq_c extends uvma_obi_memory_vp_base_seq_c; endclass : uvme_cv32e20_vp_status_flags_seq_c function uvme_cv32e20_vp_status_flags_seq_c::new(string name="uvme_cv32e20_vp_status_flags_seq_c"); - + super.new(name); - + endfunction : new function int unsigned uvme_cv32e20_vp_status_flags_seq_c::get_num_words(); @@ -81,31 +81,20 @@ task uvme_cv32e20_vp_status_flags_seq_c::vp_body(uvma_obi_memory_mon_trn_c mon_t uvma_obi_memory_slv_seq_item_c slv_rsp; `uvm_create(slv_rsp) - - slv_rsp.orig_trn = mon_trn; + + slv_rsp.orig_trn = mon_trn; slv_rsp.err = 1'b0; if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_WRITE) begin `uvm_info("VP_VSEQ", $sformatf("Call to virtual peripheral 'vp_status_flags':\n%s", mon_trn.sprint()), UVM_DEBUG) case (get_vp_index(mon_trn)) 0: begin - if (mon_trn.data == 'd123456789) begin - `uvm_info("VP_VSEQ", "virtual peripheral: TEST PASSED", UVM_DEBUG) - cv32e20_cntxt.vp_status_vif.tests_passed = 1; - cv32e20_cntxt.vp_status_vif.exit_valid = 1; - cv32e20_cntxt.vp_status_vif.exit_value = 0; - end - else if (mon_trn.data == 'd1) begin - cv32e20_cntxt.vp_status_vif.tests_failed = 1; + if (mon_trn.data[0] == 1) begin + cv32e20_cntxt.vp_status_vif.exit_value = mon_trn.data >> 1; cv32e20_cntxt.vp_status_vif.exit_valid = 1; - cv32e20_cntxt.vp_status_vif.exit_value = 1; + `uvm_info("VP_VSEQ", $sformatf("virtual peripheral: TEST PASSED WITH CODE %h", cv32e20_cntxt.vp_status_vif.exit_value), UVM_LOW) end end - 1: begin - `uvm_info("VP_VSEQ", "virtual peripheral: END OF SIM", UVM_DEBUG) - cv32e20_cntxt.vp_status_vif.exit_valid = 1; - cv32e20_cntxt.vp_status_vif.exit_value = mon_trn.data; - end endcase end else if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_READ) begin diff --git a/cv32e20/tb/uvmt/uvmt_cv32e20_dut_wrap.sv b/cv32e20/tb/uvmt/uvmt_cv32e20_dut_wrap.sv index 4303d57725..2296104e1c 100644 --- a/cv32e20/tb/uvmt/uvmt_cv32e20_dut_wrap.sv +++ b/cv32e20/tb/uvmt/uvmt_cv32e20_dut_wrap.sv @@ -117,8 +117,8 @@ module uvmt_cv32e20_dut_wrap #( // ------------------------------------------------------------------------ // Instantiate the core -// cve2_top #( - cve2_top_tracing #( +// cve2_top #( + cve2_top_tracing #( .MHPMCounterNum (MHPMCounterNum), .MHPMCounterWidth (MHPMCounterWidth), .RV32E (RV32E), @@ -136,7 +136,7 @@ module uvmt_cv32e20_dut_wrap #( .ram_cfg_i ( prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT ), .hart_id_i ( 32'h0000_0000 ), - .boot_addr_i ( 32'h0000_0000 ), //<---MJS changing to 0 + .boot_addr_i ( 32'h0000_0000 ), //<---MJS changing to 0 // Instruction memory interface .instr_req_o ( obi_memory_instr_if.req ), // core to agent diff --git a/cv32e20/tests/asm/user_define.h b/cv32e20/tests/asm/user_define.h index ce0e72199a..3d21341305 100644 --- a/cv32e20/tests/asm/user_define.h +++ b/cv32e20/tests/asm/user_define.h @@ -5,7 +5,7 @@ .section .data .global test_results test_results: - .word 123456789 + .word 000000001 #TODO: figure out how to move this to the end of the program #.section .text diff --git a/cv32e20/tests/programs/custom/all_csr_por/all_csr_por.c b/cv32e20/tests/programs/custom/all_csr_por/all_csr_por.c index 590c1f919b..268843b857 100644 --- a/cv32e20/tests/programs/custom/all_csr_por/all_csr_por.c +++ b/cv32e20/tests/programs/custom/all_csr_por/all_csr_por.c @@ -1,19 +1,19 @@ /* ** ** Copyright 2020,2022 OpenHW Group -** +** ** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); ** you may not use this file except in compliance with the License. ** You may obtain a copy of the License at -** +** ** https://solderpad.org/licenses/ -** +** ** Unless required by applicable law or agreed to in writing, software ** distributed under the License is distributed on an "AS IS" BASIS, ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ** See the License for the specific language governing permissions and ** limitations under the License. -** +** ******************************************************************************* ** ** Modeled CSR power-on-reset test: @@ -47,5 +47,4 @@ int main(int argc, char *argv[]) { printf("End Test\n\n"); return EXIT_SUCCESS; - } diff --git a/cv32e20/tests/programs/custom/branch_zero/branch_zero.c b/cv32e20/tests/programs/custom/branch_zero/branch_zero.c index 82568ba141..d3e418843d 100644 --- a/cv32e20/tests/programs/custom/branch_zero/branch_zero.c +++ b/cv32e20/tests/programs/custom/branch_zero/branch_zero.c @@ -3,8 +3,8 @@ #include #include -#define TIMER_REG_ADDR ((volatile uint32_t *) 0x15000000) -#define TIMER_VAL_ADDR ((volatile uint32_t *) 0x15000004) +#define TIMER_REG_ADDR ((volatile uint32_t *) 0x15000000) +#define TIMER_VAL_ADDR ((volatile uint32_t *) 0x15000004) void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { *TIMER_REG_ADDR = mask; @@ -168,4 +168,4 @@ int main() { : "i"(a) : "x15" ); -} \ No newline at end of file +} diff --git a/cv32e20/tests/programs/custom/csr_instr_asm/csr_instr_asm.S b/cv32e20/tests/programs/custom/csr_instr_asm/csr_instr_asm.S index 1b1ff520a2..e81dee1487 100644 --- a/cv32e20/tests/programs/custom/csr_instr_asm/csr_instr_asm.S +++ b/cv32e20/tests/programs/custom/csr_instr_asm/csr_instr_asm.S @@ -1,13 +1,13 @@ ################################################################################ # # Copyright 2020,2022 OpenHW Group -# +# # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # https://solderpad.org/licenses/ -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -15,7 +15,7 @@ # limitations under the License. # # SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 -# +# ################################################################################ # Script-generated, brute force and ignorance approach to running all legal CSR # instructions for the MSCRATCH CSR. Implements all 6 real (not pseudo) CSR @@ -6292,7 +6292,7 @@ extra_store_load: bne x16, x18, csr_fail csr_pass: - li x18, 123456789 + li x18, 1 li x17, 0x20000000 sw x18,0(x17) wfi @@ -6323,7 +6323,7 @@ csr_fail: sw a1,0(a0) sw a1,0(a0) - li x18, 1 + li x18, 2 li x17, 0x20000000 sw x18,0(x17) wfi diff --git a/cv32e20/tests/programs/custom/csr_instructions/csr_instructions.c b/cv32e20/tests/programs/custom/csr_instructions/csr_instructions.c index 309b848ec7..ed43df618d 100644 --- a/cv32e20/tests/programs/custom/csr_instructions/csr_instructions.c +++ b/cv32e20/tests/programs/custom/csr_instructions/csr_instructions.c @@ -1,19 +1,19 @@ /* ** ** Copyright 2020,2022 OpenHW Group -** +** ** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); ** you may not use this file except in compliance with the License. ** You may obtain a copy of the License at -** +** ** https://solderpad.org/licenses/ -** +** ** Unless required by applicable law or agreed to in writing, software ** distributed under the License is distributed on an "AS IS" BASIS, ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ** See the License for the specific language governing permissions and ** limitations under the License. -** +** ******************************************************************************* ** ** CSR instruction test: Execute each Zicsr instruction at least once. @@ -107,11 +107,11 @@ int main(int argc, char *argv[]) printf("DONE!\n\n"); - if (!err_cnt) { + if (!err_cnt) { return EXIT_SUCCESS; - } else { + } else { printf("\n%0d failures\n", sum); return EXIT_FAILURE; - } + } } diff --git a/cv32e20/tests/programs/custom/debug_test/debug_test.c b/cv32e20/tests/programs/custom/debug_test/debug_test.c index e81e4aab6c..3863736d2c 100644 --- a/cv32e20/tests/programs/custom/debug_test/debug_test.c +++ b/cv32e20/tests/programs/custom/debug_test/debug_test.c @@ -1,19 +1,19 @@ /* ** ** Copyright 2020,2022 OpenHW Group -** +** ** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); ** you may not use this file except in compliance with the License. ** You may obtain a copy of the License at -** +** ** https://solderpad.org/licenses/ -** +** ** Unless required by applicable law or agreed to in writing, software ** distributed under the License is distributed on an "AS IS" BASIS, ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ** See the License for the specific language governing permissions and ** limitations under the License. -** +** ******************************************************************************* ** Basic debugger test. Needs more work and bugs fixed ** It will launch a debug request and have debugger code execute (debugger.S) @@ -39,7 +39,7 @@ volatile int glb_expect_illegal_insn = 0; volatile int glb_expect_ebreak_handler = 0; volatile int glb_expect_debug_entry = 0; volatile int glb_expect_debug_exception = 0; -volatile int glb_expect_irq_entry = 0; +volatile int glb_expect_irq_entry = 0; volatile int glb_irq_timeout = 0; // Counter values // Checked at start and end of debug code @@ -51,10 +51,10 @@ volatile int glb_minstret_end = 0; // generic loop counter volatile int wait_cnt = 0; -#define TEST_FAILED *(volatile int *)0x20000000 = 1 -#define TEST_PASSED *(volatile int *)0x20000000 = 123456789 +#define TEST_PASSED *(volatile int *)0x20000000 = 1 +#define TEST_FAILED *(volatile int *)0x20000000 = 2 -extern int __stack_start; +extern int __stack_start; typedef union { struct { unsigned int start_delay : 15; // 14: 0 @@ -67,8 +67,8 @@ typedef union { unsigned int bits; } debug_req_control_t; #define DEBUG_REQ_CONTROL_REG *(volatile int *)0x15000008 -#define TIMER_REG_ADDR ((volatile uint32_t *) 0x15000000) -#define TIMER_VAL_ADDR ((volatile uint32_t *) 0x15000004) +#define TIMER_REG_ADDR ((volatile uint32_t *) 0x15000000) +#define TIMER_VAL_ADDR ((volatile uint32_t *) 0x15000004) typedef union { struct { unsigned int uie : 1; // 0 // Implemented if USER mode enabled @@ -483,12 +483,12 @@ int main(int argc, char *argv[]) glb_expect_illegal_insn = 1; glb_exception_ebreak_status = 1; glb_expect_debug_entry = 1; - // DCSR read will cause illegal instruction. + // DCSR read will cause illegal instruction. // Exception routine reads glb_exception_ebreak_status=1 and executes c.ebreak __asm__ volatile("csrr %0, dcsr" : "=r"(temp)); // Debug DCSR while(glb_debug_status != glb_hart_status){ printf("Wait for Debugger\n"); - } + } check_illegal_insn_status("Test 14", expected_illegal_instruction_count++); check_debug_status(114, glb_hart_status); @@ -499,12 +499,12 @@ int main(int argc, char *argv[]) glb_expect_illegal_insn = 1; __asm__ volatile("dret"); - check_illegal_insn_status("Test 16", expected_illegal_instruction_count++); + check_illegal_insn_status("Test 16", expected_illegal_instruction_count++); printf("------------------------\n"); printf("Test 17: WFI before debug_req_i and WFI in debug mode\n"); printf("If test hangs, WFI is NOT converted to NOP\n"); - + glb_expect_debug_entry = 1; glb_hart_status = 17; // start_delay is set to 200, should get the wfi executing before dbg request is asserted @@ -523,7 +523,7 @@ int main(int argc, char *argv[]) while(glb_expect_irq_entry == 1); mm_ram_assert_irq(0,0); printf("Irq check done\n"); - + printf("\n Jumping to Test 21\n\n"); // Check that stoupcount bit (10) in dcsr has no affect @@ -531,7 +531,7 @@ int main(int argc, char *argv[]) printf("Test 21: Setting stopcount bit=1\n"); glb_expect_debug_entry = 1; glb_hart_status = 21; - + DEBUG_REQ_CONTROL_REG = debug_req_control.bits; while(glb_debug_status != glb_hart_status){ printf("Wait for Debugger\n"); @@ -545,14 +545,14 @@ int main(int argc, char *argv[]) printf("Test 18: Single stepping\n"); glb_hart_status = 18; // Run single step code (in single_step.S) - _single_step(0); + _single_step(0); // Single step code should generate 2 illegal insn temp1++; check_illegal_insn_status("Test 18", temp1++); check_debug_status(118, glb_hart_status); - printf("Stepped %d times\n", glb_step_count); + printf("Stepped %d times\n", glb_step_count); printf("------------------------\n"); printf("Test 19: irq in debug\n"); glb_hart_status = 19; @@ -562,17 +562,17 @@ int main(int argc, char *argv[]) // Timeout added in debug code to check for taken irq or not glb_expect_irq_entry = 1; DEBUG_REQ_CONTROL_REG=debug_req_control.bits; - + while(glb_debug_status != glb_hart_status){ printf("Wait for Debugger\n"); - } - + } + check_debug_status(119, glb_hart_status); if(glb_irq_timeout != 0) { printf("glb_irq_timeout != 0, interrupt taken in debug.\n"); TEST_FAILED; - } - + } + // Test debug req vs irq timing printf("-----------------------\n"); printf("Test 20: Asserting debug_req and irq at the same cycle\n"); @@ -593,11 +593,11 @@ int main(int argc, char *argv[]) glb_expect_debug_entry = 1; glb_hart_status = 22; DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - + while(glb_debug_status != glb_hart_status) { printf("Wait for debugger\n"); - } - + } + check_debug_status(121, glb_hart_status); printf("------------------------\n"); printf("Test 23: trigger match in debug mode with match disabled\n"); @@ -605,11 +605,11 @@ int main(int argc, char *argv[]) glb_expect_debug_entry = 1; // Request debug DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - + while(glb_debug_status != glb_hart_status){ printf("Wait for Debugger\n"); - } - + } + check_debug_status(123, glb_hart_status); printf("------------------------\n"); printf("Test 24: trigger register access in D-mode\n"); @@ -617,10 +617,10 @@ int main(int argc, char *argv[]) glb_expect_debug_entry = 1; // Request debug DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - + while(glb_debug_status != glb_hart_status){ printf("Wait for Debugger\n"); - } + } check_debug_status(124, glb_hart_status); //-------------------------------- //return EXIT_FAILURE; diff --git a/cv32e20/tests/programs/custom/debug_test_known_miscompares/debug_test.c b/cv32e20/tests/programs/custom/debug_test_known_miscompares/debug_test.c index 1080c358ee..eb7bc096f3 100644 --- a/cv32e20/tests/programs/custom/debug_test_known_miscompares/debug_test.c +++ b/cv32e20/tests/programs/custom/debug_test_known_miscompares/debug_test.c @@ -1,19 +1,19 @@ /* ** ** Copyright 2020,2022 OpenHW Group -** +** ** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); ** you may not use this file except in compliance with the License. ** You may obtain a copy of the License at -** +** ** https://solderpad.org/licenses/ -** +** ** Unless required by applicable law or agreed to in writing, software ** distributed under the License is distributed on an "AS IS" BASIS, ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ** See the License for the specific language governing permissions and ** limitations under the License. -** +** ******************************************************************************* ** Basic debugger test. Needs more work and bugs fixed ** It will launch a debug request and have debugger code execute (debugger.S) @@ -34,10 +34,10 @@ volatile int glb_expect_ebreak_handler = 0; volatile int glb_expect_irq_entry = 0; volatile int glb_exception_ebreak_status = 0; volatile int glb_ebreak_status = 0; -#define TEST_FAILED *(volatile int *)0x20000000 = 1 -#define TEST_PASSED *(volatile int *)0x20000000 = 123456789 +#define TEST_PASSED *(volatile int *)0x20000000 = 1 +#define TEST_FAILED *(volatile int *)0x20000000 = 2 -extern int __stack_start; +extern int __stack_start; extern void _single_step(int d); typedef union { struct { @@ -76,7 +76,7 @@ void check_illegal_insn_status(int tag, int value) int main(int argc, char *argv[]) { debug_req_control_t debug_req_control; - + printf("------------------------\n"); printf("Test 1: debug_req while processing illegal insn\n"); @@ -97,7 +97,7 @@ int main(int argc, char *argv[]) while(glb_debug_status != glb_hart_status){ printf("Wait for Debugger\n"); - } + } check_debug_status(11, glb_hart_status); check_illegal_insn_status(1,1); diff --git a/cv32e20/tests/programs/custom/debug_test_known_miscompares/handlers.S b/cv32e20/tests/programs/custom/debug_test_known_miscompares/handlers.S index 736b9b5039..dbd4bb102d 100644 --- a/cv32e20/tests/programs/custom/debug_test_known_miscompares/handlers.S +++ b/cv32e20/tests/programs/custom/debug_test_known_miscompares/handlers.S @@ -68,8 +68,6 @@ .global glb_expect_ebreak_handler .global glb_exception_ebreak_status .global glb_expect_irq_entry -.set test_ret_val, 0x20000000 -.set test_fail, 0x1 /* exception handling */ __no_irq_handler: @@ -93,7 +91,7 @@ __no_irq_handler: la a0, no_exception_handler_msg jal ra, puts - + // Check if we expected to enter irq la a1, glb_expect_irq_entry lw t0, 0(a1) @@ -103,7 +101,7 @@ __no_irq_handler: li t0, 0 sw t0, 0(a1) //j __no_irq_handler - + // Return lw ra, 0(sp) lw a0, 4(sp) @@ -123,12 +121,10 @@ __no_irq_handler: lw t6, 60(sp) addi sp,sp,64 mret - + _irq_fail: - li a0, test_ret_val - li t0, test_fail - sw t0, 0(a0) - ret + li a0, 1 + j _exit u_sw_irq_handler: /* While we are still using puts in handlers, save all caller saved @@ -227,40 +223,36 @@ handle_ebreak: la a0, ebreak_msg jal ra, puts // Check if expecting ebreak handler - la a0, glb_expect_ebreak_handler + la a0, glb_expect_ebreak_handler lw t0, 0(a0) bne t0, x0, cont_handle_ebreak // Not expecting ebreak, assert test failed - li a0, test_ret_val - li t0, 1 - sw t0, 0(a0) + j test_fail j end_handler_incr_mepc cont_handle_ebreak: - //increment hart status + //increment hart status sw x0, 0(a0) - la a0, glb_ebreak_status + la a0, glb_ebreak_status lw t0, 0(a0) addi t0,t0,1 sw t0, 0(a0) j end_handler_incr_mepc - + handle_illegal_insn: la a0, illegal_insn_msg jal ra, puts // Check if expecting illegal instruction - la a0, glb_expect_illegal_insn + la a0, glb_expect_illegal_insn lw t0, 0(a0) - bne t0, x0, cont_illegal_insn - li a0, test_ret_val - li t0, 1 - sw t0, 0(a0) //Test Failed + bne t0, x0, cont_illegal_insn + j test_fail j end_handler_incr_mepc cont_illegal_insn: - //increment hart status + //increment hart status sw x0, 0(a0) - la a0, glb_illegal_insn_status + la a0, glb_illegal_insn_status lw t0, 0(a0) addi t0,t0,1 sw t0, 0(a0) @@ -270,11 +262,11 @@ cont_illegal_insn: lw t0, 0(a0) // End handler if no ebreak is to be executed beq t0, x0, end_handler_incr_mepc - + // Clear ebreak flag - sw x0, 0(a0) + sw x0, 0(a0) // Execute ebreak - .4byte 0x00100073 + .4byte 0x00100073 // Exit handler j end_handler_incr_mepc diff --git a/cv32e20/tests/programs/custom/debug_test_reset/debugger.S b/cv32e20/tests/programs/custom/debug_test_reset/debugger.S index 92289e3a3a..41fe1e40ab 100644 --- a/cv32e20/tests/programs/custom/debug_test_reset/debugger.S +++ b/cv32e20/tests/programs/custom/debug_test_reset/debugger.S @@ -23,8 +23,6 @@ .section .debugger, "ax" .global _debugger_start -.set test_ret_val, 0x20000000 -.set test_fail, 0x1 .set test_debugger_ok, 0xa5 _debugger_start: @@ -38,9 +36,7 @@ _debugger_start: // We don't have any globals or pointers // at this time, so we must rely on // memory (hopefully) not being used - la a0, test_debugger_entry - li t0, test_debugger_ok - sw t0, 0(a0) + j test_pass _debugger_trigger_regs_access: # R/W trigger regs otherwise not accessed @@ -477,10 +473,7 @@ _debugger_trigger_regs_access: dret _debugger_error: - li a0, test_ret_val - li t0, test_fail - sw t0, 0(a0) - dret + j test_fail .section .data .global test_debugger_entry diff --git a/cv32e20/tests/programs/custom/debug_test_trigger/debug_test.c b/cv32e20/tests/programs/custom/debug_test_trigger/debug_test.c index 275c1780a8..ea27355818 100644 --- a/cv32e20/tests/programs/custom/debug_test_trigger/debug_test.c +++ b/cv32e20/tests/programs/custom/debug_test_trigger/debug_test.c @@ -1,19 +1,19 @@ /* ** ** Copyright 2020,2022 OpenHW Group -** +** ** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); ** you may not use this file except in compliance with the License. ** You may obtain a copy of the License at -** +** ** https://solderpad.org/licenses/ -** +** ** Unless required by applicable law or agreed to in writing, software ** distributed under the License is distributed on an "AS IS" BASIS, ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ** See the License for the specific language governing permissions and ** limitations under the License. -** +** ******************************************************************************* ** Basic debugger test. Needs more work and bugs fixed ** It will launch a debug request and have debugger code execute (debugger.S) @@ -35,7 +35,7 @@ volatile int glb_expect_illegal_insn = 0; volatile int glb_expect_ebreak_handler = 0; volatile int glb_expect_debug_entry = 0; volatile int glb_expect_debug_exception = 0; -volatile int glb_expect_irq_entry = 0; +volatile int glb_expect_irq_entry = 0; // Counter values // Checked at start and end of debug code // Only lower 32 bits checked, as simulation cannot overflow on 32 bits @@ -43,10 +43,10 @@ volatile int glb_mcycle_start = 0; volatile int glb_mcycle_end = 0; volatile int glb_minstret_start = 0; volatile int glb_minstret_end = 0; -#define TEST_FAILED *(volatile int *)0x20000000 = 1 -#define TEST_PASSED *(volatile int *)0x20000000 = 123456789 +#define TEST_FAILED *(volatile int *)0x20000000 = 2 +#define TEST_PASSED *(volatile int *)0x20000000 = 1 -extern int __stack_start; +extern int __stack_start; extern int _trigger_code; extern int _trigger_code_ebreak; extern int _trigger_code_cebreak; @@ -66,8 +66,8 @@ typedef union { } debug_req_control_t; #define DEBUG_REQ_CONTROL_REG *(volatile int *)0x15000008 -#define TIMER_REG_ADDR ((volatile uint32_t *) 0x15000000) -#define TIMER_VAL_ADDR ((volatile uint32_t *) 0x15000004) +#define TIMER_REG_ADDR ((volatile uint32_t *) 0x15000000) +#define TIMER_VAL_ADDR ((volatile uint32_t *) 0x15000004) typedef union { struct { @@ -192,11 +192,11 @@ int main(int argc, char *argv[]) { debug_req_control_t debug_req_control; counters_enable(); - + // Enable interrupt mstatus_mie_enable(); mie_enable(30); - + // Assembly code from here to get better control of timing _trigger_test_combo(); diff --git a/cv32e20/tests/programs/custom/generic_exception_test/generic_exception_test.S b/cv32e20/tests/programs/custom/generic_exception_test/generic_exception_test.S index b2ea2b6f70..329ba54848 100644 --- a/cv32e20/tests/programs/custom/generic_exception_test/generic_exception_test.S +++ b/cv32e20/tests/programs/custom/generic_exception_test/generic_exception_test.S @@ -1,18 +1,18 @@ # # Copyright (C) 2020 by EM Microelectronic US Inc. -# +# # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # https://solderpad.org/licenses/ -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. -# +# # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 # ############################################################################### @@ -24,7 +24,7 @@ # # The pass/fail criteria is determined by checking x26 against MAGIC_NUMBER, # the value of which is determined by summing the following: -# - Exception code 2 (Illegal Instruction Exceptions (IIE)): 0x1 +# - Exception code 2 (Illegal Instruction Exceptions (IIE)): 0x1 # - Exception code 3 (Breakpoint): 0x10 # - Exception code 11 (Environment call): 0x100 # If the test has one of each exception code, MAGIC_NUMBER is 0x111 @@ -36,13 +36,16 @@ .globl exit .global debug .section .text -.global test_results +.global test_pass_value +.global test_fail_value .global u_sw_irq_handler #define MAGIC_NUMBER 0x2f3 -test_results: - .word 123456789 +test_pass_value: + .word 1 +test_fail_value: + .word 2 # main test main: li x15, 0x00001800 @@ -208,7 +211,7 @@ main: csrrc x14, mstatus, x0 nop nop - + added_by_mike: ############################################################################### # Randomly generated illegal instructions. Each one adds 0x1 to MAGIC_NUMBER @@ -390,10 +393,10 @@ added_by_mike: .word(0x00000F8F) # rd/imm5 =0b11111 .word(0x000F800F) # rs1 =0b11111 exit: - lw x18, test_results /* report passed result */ + lw x18, test_pass_value /* report passed result */ li x16, MAGIC_NUMBER beq x26, x16, test_end - li x18, 1 + li x18, test_fail_value /* report failed result */ test_end: li x17, 0x20000000 sw x18,0(x17) @@ -493,7 +496,7 @@ _end_trap_Generic_Handler_ASM: lw x31,4(sp) addi sp,sp,120 mret - + _exit: j _exit diff --git a/cv32e20/tests/programs/custom/illegal_instr_test/illegal_instr_test.S b/cv32e20/tests/programs/custom/illegal_instr_test/illegal_instr_test.S index 77e1700bc7..912d532276 100644 --- a/cv32e20/tests/programs/custom/illegal_instr_test/illegal_instr_test.S +++ b/cv32e20/tests/programs/custom/illegal_instr_test/illegal_instr_test.S @@ -47696,7 +47696,7 @@ main: .word(0x04008033) # p.abs [31:25]==000_0010, [14:12]==000, [6:0]==011_0011 nop .word(0x040080B3) # p.abs [31:25]==000_0010, [14:12]==000, [6:0]==011_0011 - + lw x5,80(sp) bne x5, x6, fail lw x5,76(sp) @@ -47738,11 +47738,11 @@ main: lw x5,4(sp) bne x5, x25, fail addi sp,sp,84 - li x18, 123456789 + li x18, 1 li x16, 47595 # this is the number of EXPECTED illegal instructions beq x31, x16, test_end fail: - li x18, 1 + li x18, 2 test_end: li x17, 0x20000000 sw x18,0(x17) @@ -47759,7 +47759,7 @@ u_sw_irq_handler: csrrw x0, mepc, x27 c.addi x31, 1 mret - + _exit: j _exit diff --git a/cv32e20/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S b/cv32e20/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S index 4b5f15b09c..96f220d2a0 100644 --- a/cv32e20/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S +++ b/cv32e20/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S @@ -29,66 +29,66 @@ _start0: li x7, 0xa5a5a5a5 csrrw x12, 2816, x7 li x7, 0x00000000 - bne x7, x12, csr_fail + bne x7, x12, test_fail li x7, 0x5a5a5a5a csrrw x12, 2816, x7 li x7, 0xa5a5a5a5 - bne x7, x12, csr_fail + bne x7, x12, test_fail li x7, 0xd5583a6b csrrw x12, 2816, x7 li x7, 0x5a5a5a5a - bne x7, x12, csr_fail + bne x7, x12, test_fail li x7, 0xa5a5a5a5 csrrs x12, 2816, x7 li x7, 0xd5583a6b - bne x7, x12, csr_fail + bne x7, x12, test_fail li x7, 0x5a5a5a5a csrrs x12, 2816, x7 li x7, 0xf5fdbfef - bne x7, x12, csr_fail + bne x7, x12, test_fail li x7, 0x1ac809f1 csrrs x12, 2816, x7 li x7, 0xffffffff - bne x7, x12, csr_fail + bne x7, x12, test_fail li x7, 0xa5a5a5a5 csrrc x12, 2816, x7 li x7, 0xffffffff - bne x7, x12, csr_fail + bne x7, x12, test_fail li x7, 0x5a5a5a5a csrrc x12, 2816, x7 li x7, 0x5a5a5a5a - bne x7, x12, csr_fail + bne x7, x12, test_fail li x7, 0xe34ffa80 csrrc x12, 2816, x7 li x7, 0x00000000 - bne x7, x12, csr_fail + bne x7, x12, test_fail csrrwi x12, 2816, 0b00101 li x7, 0x00000000 - bne x7, x12, csr_fail + bne x7, x12, test_fail csrrwi x12, 2816, 0b11010 li x7, 0x00000005 - bne x7, x12, csr_fail + bne x7, x12, test_fail csrrwi x12, 2816, 0b01111 li x7, 0x0000001a - bne x7, x12, csr_fail + bne x7, x12, test_fail csrrsi x12, 2816, 0b00101 li x7, 0x0000000f - bne x7, x12, csr_fail + bne x7, x12, test_fail csrrsi x12, 2816, 0b11010 li x7, 0x0000000f - bne x7, x12, csr_fail + bne x7, x12, test_fail csrrsi x12, 2816, 0b01100 li x7, 0x0000001f - bne x7, x12, csr_fail + bne x7, x12, test_fail csrrci x12, 2816, 0b00101 li x7, 0x0000001f - bne x7, x12, csr_fail + bne x7, x12, test_fail csrrci x12, 2816, 0b11010 li x7, 0x0000001a - bne x7, x12, csr_fail + bne x7, x12, test_fail csrrci x12, 2816, 0b11001 li x7, 0x00000000 - bne x7, x12, csr_fail + bne x7, x12, test_fail ################################################################################ # Generated code ends... @@ -107,7 +107,7 @@ _start0: add x2, x0, x3 sw x2, 0(x0) lw x1, 0(x0) # hole: load/store with rs1==x0 - bne x2, x1, csr_fail + bne x2, x1, test_fail li x1, 0xFFFFFFFF li x2, 0xFFFFFFFF @@ -117,7 +117,7 @@ _start0: add x2, x0, x3 sb x2, 0(x0) lb x1, 0(x0) # hole: load/store with rs1==x0 - bne x2, x1, csr_fail + bne x2, x1, test_fail li x1, 0xFFFFFFFF li x2, 0xFFFFFFFF @@ -127,7 +127,7 @@ _start0: add x2, x0, x3 sb x2, 0(x0) lbu x1, 0(x0) # hole: load/store with rs1==x0 - bne x2, x1, csr_fail + bne x2, x1, test_fail li x1, 0xFFFFFFFF li x2, 0xFFFFFFFF @@ -137,7 +137,7 @@ _start0: add x2, x0, x3 sh x2, 0(x0) lh x1, 0(x0) # hole: load/store with rs1==x0 - bne x2, x1, csr_fail + bne x2, x1, test_fail li x1, 0xFFFFFFFF li x2, 0xFFFFFFFF @@ -147,7 +147,7 @@ _start0: add x2, x0, x3 sh x2, 0(x0) lhu x1, 0(x0) # hole: load/store with rs1==x0 - bne x2, x1, csr_fail + bne x2, x1, test_fail lw x3, 4(x0) add x3, x0, x4 # hole: rs1==x0 @@ -368,7 +368,7 @@ next69: c.addi x2, 0 c.jal next70 next70: - c.addi16sp sp, -16 + c.addi16sp sp, -16 c.jal next71 next71: c.addi4spn a2, sp, 4 @@ -522,69 +522,7 @@ test_lui0: lui x28, 0 bne x0, x28, test_fail # we skipped lui x28, 0 -test_done: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'D' - sw a1,0(a0) - addi a1,zero,'O' - sw a1,0(a0) - addi a1,zero,'N' - sw a1,0(a0) - addi a1,zero,'E' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - -csr_pass: - li x18, 123456789 - li x17, 0x20000000 - sw x18,0(x17) - wfi - -csr_fail: -test_fail: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'F' - sw a1,0(a0) - addi a1,zero,'A' - sw a1,0(a0) - addi a1,zero,'I' - sw a1,0(a0) - addi a1,zero,'L' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - - li x18, 1 - li x17, 0x20000000 - sw x18,0(x17) - wfi + jal test_pass # # end # diff --git a/cv32e20/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S b/cv32e20/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S index a0f4d3bab2..73bf41a77b 100644 --- a/cv32e20/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S +++ b/cv32e20/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S @@ -17,7 +17,7 @@ # limitations under the License. # # SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 -# +# ################################################################################ # - Addresses coverage hole in which load and store instructions are not # generated for which operand rs1=ZERO. @@ -53,7 +53,7 @@ _start_main: li a3, 0xFFFFFF9A # Sign extended expected value lb a4, 2047(zero) bne a4, a3, test_fail - + # write/read mem[2047]=0xBC with sb and lbu (lbu does not sign extend) li a5, 0xBC sb a5, 2047(zero) @@ -66,13 +66,13 @@ _start_main: li a7, 0xFFFFDEF0 # Sign extended expected value lh a0, 2046(zero) bne a7, a0, test_fail - + # write/read mem[2047]=0x81 & mem[2046]=0x23 with sh and lhu (lhu does not sign extend) li a1, 0x8123 sh a1, 2046(zero) lhu a2, 2046(zero) bne a1, a2, test_fail - + test_done: lui a0,print_port>>12 addi a1,zero,'\n' @@ -99,42 +99,8 @@ test_done: sw a1,0(a0) sw a1,0(a0) -test_pass: - li x18, 123456789 - li x17, 0x20000000 - sw x18,0(x17) - wfi - -test_fail: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'F' - sw a1,0(a0) - addi a1,zero,'A' - sw a1,0(a0) - addi a1,zero,'I' - sw a1,0(a0) - addi a1,zero,'L' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) + j test_pass - li x18, 1 - li x17, 0x20000000 - sw x18,0(x17) - wfi # # end # diff --git a/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S b/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S index 7ef04e8b04..031c73c13e 100644 --- a/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S +++ b/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S @@ -2,10 +2,11 @@ #.include "user_define.h" #.globl _start #.section .text -#_start: +#_start: # END: riscv-dv # BEGIN: gtumbush .include "user_define.h" + .section .text.start .globl _start .section .text @@ -18,7 +19,7 @@ _start: .globl _start_main .section .text -_start_main: +_start_main: # END: gtumbush # BEGIN: riscv-dv csrr x5, mhartid @@ -29,20 +30,20 @@ _start_main: h0_start: li x30, 0x40001104 csrw misa, x30 -kernel_sp: +kernel_sp: la x13, kernel_stack_end -trap_vec_init: +trap_vec_init: la x30, mtvec_handler ori x30, x30, 1 csrw 0x305, x30 # MTVEC -mepc_setup: +mepc_setup: la x30, init csrw mepc, x30 j init_machine_mode -init: +init: li x0, 0xffae545d li x1, 0xf li x2, 0xfaea503e @@ -11305,22 +11306,7 @@ fast_exit: sw a5,0(a0) sw a5,0(a0) - li a0, test_ret_val - lw a1, test_results /* report result */ - sw a1,0(a0) - - wfi /* we are done */ -##End: Extracted from riscv_compliance_tests/riscv_test.h - - j test_done -test_done: - li gp, 1 - ecall -write_tohost: - sw gp, tohost, t5 - -_exit: - j write_tohost + j test_pass init_machine_mode: li x30, 0x1800 @@ -11328,13 +11314,9 @@ init_machine_mode: li x30, 0x0 csrw 0x304, x30 # MIE mret -instr_end: +instr_end: nop -.section .data -.align 6; .global tohost; tohost: .dword 0; -.align 6; .global fromhost; fromhost: .dword 0; -.section .user_stack,"aw",@progbits; .align 2 user_stack_start: .rept 4999 @@ -11384,7 +11366,7 @@ mmode_intr_vector_1: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_2: csrrw x12, 0x340, x12 @@ -11425,7 +11407,7 @@ mmode_intr_vector_2: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_3: csrrw x12, 0x340, x12 @@ -11466,7 +11448,7 @@ mmode_intr_vector_3: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_4: csrrw x12, 0x340, x12 @@ -11507,7 +11489,7 @@ mmode_intr_vector_4: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_5: csrrw x12, 0x340, x12 @@ -11548,7 +11530,7 @@ mmode_intr_vector_5: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_6: csrrw x12, 0x340, x12 @@ -11589,7 +11571,7 @@ mmode_intr_vector_6: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_7: csrrw x12, 0x340, x12 @@ -11630,7 +11612,7 @@ mmode_intr_vector_7: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_8: csrrw x12, 0x340, x12 @@ -11671,7 +11653,7 @@ mmode_intr_vector_8: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_9: csrrw x12, 0x340, x12 @@ -11712,7 +11694,7 @@ mmode_intr_vector_9: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_10: csrrw x12, 0x340, x12 @@ -11753,7 +11735,7 @@ mmode_intr_vector_10: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_11: csrrw x12, 0x340, x12 @@ -11794,7 +11776,7 @@ mmode_intr_vector_11: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_12: csrrw x12, 0x340, x12 @@ -11835,7 +11817,7 @@ mmode_intr_vector_12: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_13: csrrw x12, 0x340, x12 @@ -11876,7 +11858,7 @@ mmode_intr_vector_13: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_14: csrrw x12, 0x340, x12 @@ -11917,7 +11899,7 @@ mmode_intr_vector_14: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass mmode_intr_vector_15: csrrw x12, 0x340, x12 @@ -11958,10 +11940,10 @@ mmode_intr_vector_15: srli x30, x30, 0x1f beqz x30, 1f j mmode_intr_handler - 1: j test_done + 1: j test_pass -.align 2 -mtvec_handler: +.align 8 +mtvec_handler: .option norvc; j mmode_exception_handler j mmode_intr_vector_1 @@ -12041,9 +12023,9 @@ mmode_exception_handler: li x22, 0x2 # ILLEGAL_INSTRUCTION beq x30, x22, illegal_instr_handler csrr x22, 0x343 # MTVAL - 1: jal x1, test_done + 1: jal x1, test_pass -ecall_handler: +ecall_handler: la x30, _start sw x0, 0(x30) sw x1, 4(x30) @@ -12077,7 +12059,7 @@ ecall_handler: sw x29, 116(x30) sw x30, 120(x30) sw x31, 124(x30) - j write_tohost + j _exit instr_fault_handler: lw x1, 4(x12) lw x2, 8(x12) @@ -12189,7 +12171,7 @@ store_fault_handler: csrrw x12, 0x340, x12 mret -ebreak_handler: +ebreak_handler: csrr x30, mepc addi x30, x30, 4 csrw mepc, x30 @@ -12269,7 +12251,7 @@ illegal_instr_handler: csrrw x12, 0x340, x12 mret -pt_fault_handler: +pt_fault_handler: nop .align 2 diff --git a/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S b/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S index 4eeb125fe0..4e3705257a 100644 --- a/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S +++ b/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S @@ -2,7 +2,7 @@ #.include "user_define.h" #.globl _start #.section .text -#_start: +#_start: # END: riscv-dv # BEGIN: gtumbush .include "user_define.h" @@ -17,7 +17,7 @@ _start: .globl _start_main .section .text -_start_main: +_start_main: # END: gtumbush # BEGIN: riscv-dv csrr x5, mhartid @@ -28,20 +28,20 @@ _start_main: h0_start: li x10, 0x40001104 csrw misa, x10 -kernel_sp: +kernel_sp: la x31, kernel_stack_end -trap_vec_init: +trap_vec_init: la x10, mtvec_handler ori x10, x10, 1 csrw 0x305, x10 # MTVEC -mepc_setup: +mepc_setup: la x10, init csrw mepc, x10 j init_machine_mode -init: +init: li x0, 0xfd790eda li x1, 0x80000000 li x2, 0x6 @@ -11355,16 +11355,13 @@ fast_exit: lw a1, test_results /* report result */ sw a1,0(a0) - wfi /* we are done */ -##End: Extracted from riscv_compliance_tests/riscv_test.h - -test_done: +test_done: li gp, 1 ecall -write_tohost: +write_tohost: sw gp, tohost, t5 -_exit: +_exit: j write_tohost init_machine_mode: @@ -11373,12 +11370,9 @@ init_machine_mode: li x10, 0x0 csrw 0x304, x10 # MIE mret -instr_end: +instr_end: nop -.section .data -.align 6; .global tohost; tohost: .dword 0; -.align 6; .global fromhost; fromhost: .dword 0; .section .user_stack,"aw",@progbits; .align 2 user_stack_start: @@ -12005,8 +11999,8 @@ mmode_intr_vector_15: j mmode_intr_handler 1: j test_done -.align 2 -mtvec_handler: +.align 8 +mtvec_handler: .option norvc; j mmode_exception_handler j mmode_intr_vector_1 @@ -12086,9 +12080,9 @@ mmode_exception_handler: li x2, 0x2 # ILLEGAL_INSTRUCTION beq x10, x2, illegal_instr_handler csrr x2, 0x343 # MTVAL - 1: jal x1, test_done + 1: jal x1, test_done -ecall_handler: +ecall_handler: la x10, _start sw x0, 0(x10) sw x1, 4(x10) @@ -12234,7 +12228,7 @@ store_fault_handler: csrrw x15, 0x340, x15 mret -ebreak_handler: +ebreak_handler: csrr x10, mepc addi x10, x10, 4 csrw mepc, x10 @@ -12314,10 +12308,10 @@ illegal_instr_handler: csrrw x15, 0x340, x15 mret -pt_fault_handler: +pt_fault_handler: nop -.align 2 +.align 8 mmode_intr_handler: csrr x10, 0x300 # MSTATUS; csrr x10, 0x304 # MIE; diff --git a/cv32e20/tests/programs/custom/riscv_csr/custom_handlers.S b/cv32e20/tests/programs/custom/riscv_csr/custom_handlers.S index efd1c7f3e1..57b92f8ae5 100644 --- a/cv32e20/tests/programs/custom/riscv_csr/custom_handlers.S +++ b/cv32e20/tests/programs/custom/riscv_csr/custom_handlers.S @@ -1,23 +1,23 @@ /* ** -** Copyright 2023 Intrinsix -** +** Copyright 2023 Cadence +** ** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); ** you may not use this file except in compliance with the License. ** You may obtain a copy of the License at -** +** ** https://solderpad.org/licenses/ -** +** ** Unless required by applicable law or agreed to in writing, software ** distributed under the License is distributed on an "AS IS" BASIS, ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ** See the License for the specific language governing permissions and ** limitations under the License. -** +** ******************************************************************************* ** This file contains a modified version of the u_sw_irq_handler -** found in bsp/handler.S. The u_sw_irq_handler in that file is designated as -** a weak symbol while this one is not, so the one in this file should override +** found in bsp/handler.S. The u_sw_irq_handler in that file is designated as +** a weak symbol while this one is not, so the one in this file should override ** it. ** ** This version of u_sw_irq_handler calls different functions to handle @@ -34,7 +34,7 @@ #define EXCEPTION_BREAKPOINT 3 #define EXCEPTION_ECALL_M 11 - + .section .text.handlers .global __no_irq_handler .global u_sw_irq_handler @@ -44,10 +44,8 @@ .global csr_unexpected_int .global switch_to_user_mode .global switch_to_machine_mode -.set test_ret_val, 0x20000000 -.set test_fail, 0x1 - + u_sw_irq_handler: /* While we are still using puts in handlers, save all caller saved regs. Eventually, some of these saves could be deferred. */ @@ -91,7 +89,7 @@ handle_illegal_csr: csrrsi t0, mepc, 0 addi t0, t0, 0x8 csrrw t0, mepc, t0 -end_handler_ret: +end_handler_ret: lw ra, 0(sp) lw a0, 4(sp) lw a1, 8(sp) @@ -110,14 +108,14 @@ end_handler_ret: lw t6, 60(sp) addi sp,sp,64 mret - + handle_unknown: la a0, unknown_msg jal ra, puts /* We don't know what interrupt/exception is being handled, so don't increment mepc. */ j end_handler_ret - + end_handler_incr_mepc: csrr t0, mepc lb t1, 0(t0) @@ -130,9 +128,9 @@ end_handler_incr_mepc: end_handler_incr_mepc2: addi t0, t0, 2 csrw mepc, t0 - j end_handler_ret + j end_handler_ret + - /* This is unchanged from bsp/handlers.S * The handle_syscall function is in bsp/syscalls.c */ @@ -166,17 +164,17 @@ switch_to_user_mode: /*Write the return address into the mepc*/ csrrw x0, mepc, ra /*Return with 'mret' rather than ret instruction*/ - mret + mret switch_to_machine_mode: /*Force execution of the ebreak handler*/ ebreak - ret - + ret + /* Error reporting code. * Each of tehse labels does a printf of a different message, * then jumps to a failure loop. - */ + */ csr_mismatch: la a0, csr_mismatch_msg jal ra, printf @@ -186,7 +184,7 @@ csr_user_unauth: la a0, csr_user_unauth_msg jal ra, printf j csr_fail_loop - + csr_bad_impl: addi sp, sp,-8 sw ra, 0(sp) @@ -213,15 +211,13 @@ csr_unexpected_illegal_inst: j csr_fail_loop csr_fail_loop: - li t1, test_fail - li t2, test_ret_val - sw t1, 0(t2) + jal test_fail j csr_fail_loop - + /* Error messages. Pointers to these should go into a0(x10) before calling printf * Assumptions are that data is loaded into registers as follows: * a1(x11): CSR Address - * a2(x12): Expected Data + * a2(x12): Expected Data * a3(x13): Actual Data */ .section .rodata diff --git a/cv32e20/tests/programs/custom/riscv_csr/gen_csr_test.py b/cv32e20/tests/programs/custom/riscv_csr/gen_csr_test.py index 3916a68157..a051304795 100644 --- a/cv32e20/tests/programs/custom/riscv_csr/gen_csr_test.py +++ b/cv32e20/tests/programs/custom/riscv_csr/gen_csr_test.py @@ -48,8 +48,8 @@ the chosen signature address to indicate the test's result. """ TEST_RESULT = 1 -TEST_PASS = 123456789 -TEST_FAIL = 1 +TEST_PASS = 1 +TEST_FAIL = 2 PRIVILEGE_MODES = ["DRO", "DRW", "MRO", "MRW", "HRO", "HRW", "SRO", "SRW","URO", "URW"] PRIVILEGE_LEVELS = {'D' : 4, 'M' : 3, 'H' : 2, 'S' : 1, 'U' :0} INTERRUPT_CSRS = ["mtvec", "mepc", "mstatus", "mcause", "mtval"] @@ -263,7 +263,7 @@ def add_auto_gen_comment(test_file, csr_file): test_file.write("/* This is an auto-generated file not intended to be hand edited.\n") test_file.write(" * Changes should be made by editing the yaml file {}\n".format(csr_file)) test_file.write(" * Then invoking {} to regenerate this file.\n */\n".format(__file__)) - + def gen_setup(test_file): @@ -285,22 +285,22 @@ def gen_check_writeable_csr(test_file, source_reg, dest_reg, csr_instructions, x Writes self checking code for accesses to a writable CSR. Writes randomly generated values into the CSR and reads back the data. Does not expect any exceptions to occur. - Args: - test_file: File to write the code to. + Args: + test_file: File to write the code to. source_reg: Register used to store the value to be written to the CSR and - the expected read value. + the expected read value. dest_reg: Register used to store the value read from the CSR - csr_instructions: List of CSR access instructions to be tested. - xlen: ISA width, passed from command line. - The following come direclty from the yaml file: + csr_instructions: List of CSR access instructions to be tested. + xlen: ISA width, passed from command line. + The following come direclty from the yaml file: csr_address: The address of the CSR, as an integer. csr_val: The reset value for this csr. Used by the predict_csr_val funciton. csr_write_fields: A list of the CSR's fields. Used by the predict_csr_val funciton. csr_read_mask: A bitarray of readable fields. Used by the predict_csr_val funciton. - csr_is_volatile: Boolean value. If set, no data checking will be done. + csr_is_volatile: Boolean value. If set, no data checking will be done. """ reset_val = copy.deepcopy(csr_val) - + for op in csr_instructions: for i in range(3): # hex string @@ -344,30 +344,30 @@ def gen_check_writeable_csr(test_file, source_reg, dest_reg, csr_instructions, x test_file.write(branch_check) test_file.write("\tli {}, {}\n".format(source_reg, reset_val)) test_file.write("\tcsrw {}, {}\n".format(hex(csr_address),source_reg)) - + def gen_check_read_only_csr(test_file, source_reg, dest_reg, csr_instructions, xlen, csr_address, csr_val, csr_write_fields, csr_read_mask, csr_is_volatile): """ Writes self checking code for accesses to a read only CSR. All write accesses - should result in an exception. The code written assumes that the address of a - global variable used to flag expected illegal instructions is already loaded in + should result in an exception. The code written assumes that the address of a + global variable used to flag expected illegal instructions is already loaded in register t1 (x6). It also assumes that the exception handler will advance the PC past the unconditional branch to error code that it will place after the illegal access. - Args: - test_file: File to write the code to. + Args: + test_file: File to write the code to. source_reg: Register used to store the value to be written to the CSR and - the expected read value. + the expected read value. dest_reg: Register used to store the value read from the CSR - csr_instructions: List of CSR access instructions to be tested. - xlen: ISA width, passed from command line. - The following come direclty from the yaml file: + csr_instructions: List of CSR access instructions to be tested. + xlen: ISA width, passed from command line. + The following come direclty from the yaml file: csr_address: The address of the CSR, as an integer. csr_val: The reset value for this csr. Used by the predict_csr_valf funciton. csr_write_fields: A list of the CSR's fields. Used by the predict_csr_valf funciton. csr_read_mask: A bitarray of readable fields. Used by the predict_csr_valf funciton. - csr_is_volatile: Boolean value. If set, no data checking will be done. + csr_is_volatile: Boolean value. If set, no data checking will be done. """ for op in csr_instructions: for i in range(3): @@ -376,7 +376,7 @@ def gen_check_read_only_csr(test_file, source_reg, dest_reg, csr_instructions, if (op[4] == 'w'): test_file.write("\tlw t0, 0(t1)\n") test_file.write("\taddi t0, t0, 1\n") - test_file.write("\tsw t0, 0(t1)\n") + test_file.write("\tsw t0, 0(t1)\n") if op[-1] == "i": imm = rand_rs1_val[-5:] csr_inst = "\t{} {}, {}, 0b{}\n".format(op, @@ -411,28 +411,28 @@ def gen_check_read_only_csr(test_file, source_reg, dest_reg, csr_instructions, test_file.write(predict_li) test_file.write(branch_check) else: - test_file.write("\tj csr_user_unauth\n") + test_file.write("\tj csr_user_unauth\n") def gen_check_inaccessible_csr(test_file, source_reg, dest_reg, csr_instructions, xlen, csr_address): """ Writes self checking code for accesses to inaccessilbe CSRs. Every attempted access - should result in an exception. The code written assumes that the address of a - global variable used to flag expected illegal instructions is already loaded in + should result in an exception. The code written assumes that the address of a + global variable used to flag expected illegal instructions is already loaded in register t1 (x6). It also assumes that the exception handler will advance the PC past the unconditional branch to error code that it will place after the illegal access. - Args: - test_file: File to write the code to. + Args: + test_file: File to write the code to. source_reg: Register used to store the value to be written to the CSR and - the expected read value. + the expected read value. dest_reg: Register used to store the value read from the CSR - csr_instructions: List of CSR access instructions to be tested. - xlen: ISA width, passed from command line. - The following come direclty from the yaml file: - csr_address: The address of the CSR, as an integer. + csr_instructions: List of CSR access instructions to be tested. + xlen: ISA width, passed from command line. + The following come direclty from the yaml file: + csr_address: The address of the CSR, as an integer. """ - + for op in csr_instructions: rand_rs1_val = get_rs1_val(0, xlen) if op[-1] == "i": @@ -453,72 +453,72 @@ def gen_check_inaccessible_csr(test_file, source_reg, dest_reg, csr_instruction def gen_interrupt_csr_check_func(test_file, header_file, original_csr_map, csr_instructions, xlen): """ - Generates a function to check the interrupt related CSRs. This is done by calling - gen_check_writeable_csr on each CSR named in the global list INTERRUPT_CSRS. - - The value placed in mtvec by the C startup code is preserved by this funciton. + Generates a function to check the interrupt related CSRs. This is done by calling + gen_check_writeable_csr on each CSR named in the global list INTERRUPT_CSRS. + + The value placed in mtvec by the C startup code is preserved by this funciton. This allows the interrupt related CSR's to be checked, but still allows for exception - related features to be exercised in machine mode. + related features to be exercised in machine mode. Args: test_file: File to write assembly test code out to. - header_file: File to write C headers to. + header_file: File to write C headers to. original_csr_map: The dictionary containing CSR mappings generated by get_csr_map() csr_instructions: A list of all supported CSR instructions in string form. xlen: The RISC-V ISA bit length. """ csr_map = copy.deepcopy(original_csr_map) source_reg = "x12" - dest_reg = "x13" + dest_reg = "x13" test_file.write(".globl interrupt_csr_check\n") test_file.write("interrupt_csr_check:\n") header_file.write("void interrupt_csr_check();\n") for csr in INTERRUPT_CSRS: csr_address, csr_val, csr_write_fields, csr_read_mask, csr_privilege_mode, \ - csr_is_volatile, csr_skip_me = csr_map.get( csr) - test_file.write("\t# {}\n".format(csr)) - if (csr_skip_me): + csr_is_volatile, csr_skip_me = csr_map.get( csr) + test_file.write("\t# {}\n".format(csr)) + if (csr_skip_me): test_file.write("\t# \tCSR marked SKIP_ME: {}\n".format(csr_skip_me)) - continue - test_file.write("\tli a1, {}\n".format(hex(csr_address))) + continue + test_file.write("\tli a1, {}\n".format(hex(csr_address))) if (csr == "mtvec"): - test_file.write("\tli t0, {}\n".format(csr_val)) + test_file.write("\tli t0, {}\n".format(csr_val)) test_file.write("\tcsrrw t1, {}, t0\n".format(hex(csr_address))) gen_check_writeable_csr(test_file, source_reg, dest_reg,csr_instructions, xlen, csr_address, csr_val, csr_write_fields, csr_read_mask, csr_is_volatile) if (csr == "mtvec"): test_file.write("\tcsrrw t0, {}, t1\n".format(hex(csr_address))) - + test_file.write("\tret\n"); - + def gen_csr_check_func(test_file, header_file, original_csr_map, csr_instructions, xlen, function_name, privilege): - + """ - Generates a function to check CSR accesses. This is done by calling + Generates a function to check CSR accesses. This is done by calling gen_check_writeable_csr, gen_check_read_only_csr, or gen_check_inaccessible_csr - as approriate based on the privilege leve of the CSR and the privilege - level being tested. - + as approriate based on the privilege leve of the CSR and the privilege + level being tested. + Machine and debug level will skip testing CSR's in the global INTERRUPT_CSR list; - This allows exception to be taken during the function without worrying about + This allows exception to be taken during the function without worrying about the exception related CSR's chaning in ways that are difficult to predict. These - CSR's should be tested using the function generated by gen_interrupt_csr_check_func - above. + CSR's should be tested using the function generated by gen_interrupt_csr_check_func + above. - This function is coded to handle all possible privilege levels, but only Machine and User - are actually used by this script. + This function is coded to handle all possible privilege levels, but only Machine and User + are actually used by this script. Args: test_file: File to write assembly test code out to. - header_file: File to write C headers to. + header_file: File to write C headers to. original_csr_map: The dictionary containing CSR mappings generated by get_csr_map() csr_instructions: A list of all supported CSR instructions in string form. xlen: The RISC-V ISA bit length. - fucntion_name: The name of the function to create. + fucntion_name: The name of the function to create. privilege: A single character indicating the privilege level to test. """ csr_map = copy.deepcopy(original_csr_map) @@ -536,14 +536,14 @@ def gen_csr_check_func(test_file, header_file, original_csr_map, csr_instruction csr_address, csr_val, csr_write_fields, csr_read_mask, csr_privilege_mode, \ csr_is_volatile, csr_skip_me = csr_map.get( csr) test_file.write("\t# {}\n".format(csr)) - - if (csr_skip_me): + + if (csr_skip_me): test_file.write("\t# \tCSR marked SKIP_ME: {}\n".format(csr_skip_me)) continue test_file.write("\tli a1, {}\n".format(hex(csr_address))) if (PRIVILEGE_LEVELS[privilege] < PRIVILEGE_LEVELS[csr_privilege_mode[0]]): gen_check_inaccessible_csr(test_file, source_reg, dest_reg, csr_instructions, xlen, - csr_address) + csr_address) elif ( csr_privilege_mode[-2:] == "RO"): gen_check_read_only_csr(test_file, source_reg, dest_reg, csr_instructions, xlen, csr_address, csr_val, csr_write_fields, csr_read_mask, @@ -552,26 +552,24 @@ def gen_csr_check_func(test_file, header_file, original_csr_map, csr_instruction gen_check_writeable_csr(test_file, source_reg, dest_reg,csr_instructions, xlen, csr_address, csr_val, csr_write_fields, csr_read_mask, csr_is_volatile) - - test_file.write("\tret\n"); def gen_csr_check_unimplemented(test_file, header_file, original_csr_map): - + """ Generates a function to that verifies that no CSR accesses are possible to CSR address not listed int the .yaml file. - + This function will do a read access to every possible address not listed in the .yaml file, setting the glbl_expect_illegal_insn for each one - and branching to csr_bad_impl if the exectption is not taken. + and branching to csr_bad_impl if the exectption is not taken. CSR address with the "SKIP_ME" entry in the .yaml file will not be accessed - by this function. + by this function. Args: test_file: File to write assembly test code out to. - header_file: File to write C headers to. + header_file: File to write C headers to. original_csr_map: The dictionary containing CSR mappings generated by get_csr_map() """ csr_map = copy.deepcopy(original_csr_map) @@ -590,20 +588,19 @@ def gen_csr_check_unimplemented(test_file, header_file, original_csr_map): for addr in range (0x1000): if (addr in csr_addrs): continue - else : - test_file.write("\tli a1, {}\n".format(hex(addr))) + else : + test_file.write("\tli a1, {}\n".format(hex(addr))) test_file.write("\tlw t0, 0(t1)\n") test_file.write("\taddi t0, t0, 1\n") test_file.write("\tsw t0, 0(t1)\n") test_file.write("\tcsrr t0, {}\n".format(hex(addr))) test_file.write("\tjal ra, csr_bad_impl\n") - - test_file.write("\tlw ra, 0(sp)\n") + + test_file.write("\tlw ra, 0(sp)\n") test_file.write("\taddi sp, sp, 4\n") - test_file.write("\tret\n"); - - - + test_file.write("\tret\n"); + + def main(): """Main entry point of CSR test generation script. Will set up a list of all supported CSR instructions, @@ -641,7 +638,7 @@ def main(): add_auto_gen_comment(csr_test_file, args.csr_file) csr_header_file = open("{}/riscv_csr_test_{}.h".format(args.out, 0), "w") add_auto_gen_comment(csr_header_file, args.csr_file) - + gen_setup(csr_test_file) gen_interrupt_csr_check_func(csr_test_file, csr_header_file, csr_map, csr_ops, args.xlen) @@ -652,6 +649,6 @@ def main(): csr_map, csr_ops, args.xlen, "user_mode_check", 'U') csr_test_file.close() csr_header_file.close() - + if __name__ == "__main__": main() diff --git a/cv32e20/tests/programs/custom/riscv_csr/riscv_csr.c b/cv32e20/tests/programs/custom/riscv_csr/riscv_csr.c index 777b2a03a6..9bfc0c6c96 100644 --- a/cv32e20/tests/programs/custom/riscv_csr/riscv_csr.c +++ b/cv32e20/tests/programs/custom/riscv_csr/riscv_csr.c @@ -1,30 +1,30 @@ /* ** ** Copyright 2023 Intrinsix -** +** ** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); ** you may not use this file except in compliance with the License. ** You may obtain a copy of the License at -** +** ** https://solderpad.org/licenses/ -** +** ** Unless required by applicable law or agreed to in writing, software ** distributed under the License is distributed on an "AS IS" BASIS, ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ** See the License for the specific language governing permissions and ** limitations under the License. -** +** ******************************************************************************* ** CSR access test -** This tests consists of calling the functions generated by gen_csr_test.py -** in the proper privilege modes. -** It also checks that there are no expected exceptions that did not occur. -** -** Recomended method of invoking the gen_csr_test.py script is to run it the same +** This tests consists of calling the functions generated by gen_csr_test.py +** in the proper privilege modes. +** It also checks that there are no expected exceptions that did not occur. +** +** Recomended method of invoking the gen_csr_test.py script is to run it the same ** directory as this file with the following command line: ** ** python3 gen_csr_test.py --csr_file ../../../../env/corev-dv/cv32e20_csr_template.yaml -** +** ******************************************************************************* */ @@ -39,10 +39,10 @@ volatile int glb_fail_count = 0; volatile int glb_csr_address = 0; -#define TEST_FAILED *(volatile int*)(0x20000000) = 1 -#define TEST_PASSED *(volatile int*)(0x20000000) = 123456789 +#define TEST_FAILED *(volatile int*)(0x20000000) = 2 +#define TEST_PASSED *(volatile int*)(0x20000000) = 1 + - int main(int argc, char *argv[]) { interrupt_csr_check(); @@ -75,13 +75,13 @@ int main(int argc, char *argv[]) { printf ("ERROR: Still expecting %d illegal instruction interrupt(s) after checking unimplmented addresses.", glb_expect_illegal_insn); TEST_FAILED; - } + } switch_to_machine_mode(); machine_mode_check(); if (glb_expect_illegal_insn != 0) { printf ("ERROR: Still expecting %d illegal instruction interrupt(s) at end of test.", glb_expect_illegal_insn); TEST_FAILED; - } + } TEST_PASSED; } diff --git a/cv32e20/tests/programs/custom/riscv_ebreak_test_0/riscv_ebreak_test_0.S b/cv32e20/tests/programs/custom/riscv_ebreak_test_0/riscv_ebreak_test_0.S index c822eb8390..d1bfad049a 100644 --- a/cv32e20/tests/programs/custom/riscv_ebreak_test_0/riscv_ebreak_test_0.S +++ b/cv32e20/tests/programs/custom/riscv_ebreak_test_0/riscv_ebreak_test_0.S @@ -49,20 +49,20 @@ _start_main: li x31, 0x5912efde li x4, 0x40001104 csrw misa, x4 -kernel_sp: +kernel_sp: la x24, _kernel_stack_end -trap_vec_init: +trap_vec_init: la x4, mtvec_handler ori x4, x4, 0 csrw 0x305, x4 # MTVEC -mepc_setup: +mepc_setup: la x4, _init csrw mepc, x4 j init_machine_mode -_init: +_init: la x2, _user_stack_end _main: la s1, region_2+5617 #start riscv_load_store_rand_instr_stream_9 sb s5, 64(s1) @@ -5274,9 +5274,7 @@ main_51_0_t: srl gp, s5, t4 sub ra, s5, t0 csrrc ra, 0x340, t1 3041: remu t3, t1, t4 -test_done: - li gp, 1 - ecall + j test_pass sub_2: c.nop addi sp, sp, -64 sw gp, 4(sp) @@ -16622,14 +16620,8 @@ j_sub_3_sub_4_4: jalr gp, s11, -414 xori s2, ra, 102 c.slli a5, 22 654: c.jr x3 -write_tohost: - sw gp, tohost, t5 - -_exit: - li a0, 0x20000004 - li a1, 0 - sw a1, 0(a0) - j write_tohost + li a0, 0 + j test_exit init_machine_mode: li x4, 0x101800 @@ -17710,7 +17702,7 @@ _user_stack_end: _kernel_instr_start: .align 12 .text .align 12 -mtvec_handler: +mtvec_handler: csrrw x2, 0x340, x2 add x2, x24, zero 1: addi x2, x2, -124 @@ -17775,9 +17767,10 @@ mmode_exception_handler: li x7, 0x2 # ILLEGAL_INSTRUCTION beq x4, x7, illegal_instr_handler csrr x7, 0x343 # MTVAL - 1: jal x1, test_done + li a0, 0 + 1: jal x1, _exit -ebreak_handler: +ebreak_handler: csrr x4, mepc addi x4, x4, 4 csrw mepc, x4 @@ -17817,7 +17810,7 @@ ebreak_handler: csrrw x2, 0x340, x2 mret -ecall_handler: +ecall_handler: la x4, _start sw x0, 0(x4) sw x1, 4(x4) @@ -17851,7 +17844,7 @@ ecall_handler: sw x29, 116(x4) sw x30, 120(x4) sw x31, 124(x4) - j write_tohost + j _exit illegal_instr_handler: csrr x4, mepc addi x4, x4, 4 @@ -18003,7 +17996,7 @@ store_fault_handler: csrrw x2, 0x340, x2 mret -pt_fault_handler: +pt_fault_handler: nop .align 12 diff --git a/cv32e40p/env/uvme/uvme_rv32isa_covg_trn.sv b/cv32e40p/env/uvme/uvme_rv32isa_covg_trn.sv index aa8cb04d5a..023255d155 100644 --- a/cv32e40p/env/uvme/uvme_rv32isa_covg_trn.sv +++ b/cv32e40p/env/uvme/uvme_rv32isa_covg_trn.sv @@ -1,12 +1,12 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -25,18 +25,17 @@ through UVM testbench */ class uvme_rv32isa_covg_trn_c extends uvml_trn_mon_trn_c; - + // Note, structs are not supported in the uvm field macros + `uvm_object_utils(uvme_rv32isa_covg_trn_c) + ins_t ins; - // Note, structs are not supported in the uvm field macros - `uvm_object_utils_begin(uvme_rv32isa_covg_trn_c) - `uvm_object_utils_end - + /** * Default constructor. */ extern function new(string name="uvme_rv32isa_covg_trn"); - + extern function void do_copy(uvm_object rhs); extern function void do_print(uvm_printer printer); @@ -46,9 +45,9 @@ endclass : uvme_rv32isa_covg_trn_c `pragma protect begin function uvme_rv32isa_covg_trn_c::new(string name="uvme_rv32isa_covg_trn"); - + super.new(name); - + endfunction : new function void uvme_rv32isa_covg_trn_c::do_copy(uvm_object rhs); @@ -57,7 +56,7 @@ function void uvme_rv32isa_covg_trn_c::do_copy(uvm_object rhs); super.do_copy(rhs); assert($cast(rhs_trn, rhs)); - this.ins.ins_str = rhs_trn.ins.ins_str; + this.ins.ins_str = rhs_trn.ins.ins_str; this.ins.asm = rhs_trn.ins.asm; foreach (this.ins.ops[i]) begin this.ins.ops[i].key = rhs_trn.ins.ops[i].key; diff --git a/docs/VerifStrat/source/test_programs.rst b/docs/VerifStrat/source/test_programs.rst index 9b83316197..67951bcfc3 100644 --- a/docs/VerifStrat/source/test_programs.rst +++ b/docs/VerifStrat/source/test_programs.rst @@ -1,18 +1,18 @@ .. Copyright (c) 2020 OpenHW Group - + Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at - + https://solderpad.org/licenses/ - + Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 @@ -42,7 +42,7 @@ The address range for I&D memory is 0x0..0x10_0000 (1Mbyte). The virtual peripherals start at address 0x1000_0000. The addresses and sizes of the I&D memory and virtual peripheral must be compatible with the Configuration inputs of the core -(see `Core Integration `__ +(see `Core Integration `__ in the CV32E40P User Manual. The core will start fetching instructions from the address provided on its **boot_addr_i** input. In addition, if debug_req_i is asserted, execution jumps to **dm_halt_addr_i**. @@ -121,15 +121,9 @@ new test programs developed for CORE-V is strongly discouraged. | Instruction Memory | 32’h1600_XXXX | Program a table that introduces “random” stalls on IMEM I/F. | | Interface Stall Control | | | +--------------------------+-----------------------+----------------------------------------------------------------+ -| Virtual Peripheral | 32’h2000_0000 | Assert test_passed if wdata==’d123456789 | +| Virtual Peripheral | 32’h2000_0000 | Program exit code using tohost procedure. | | Status Flags | | | -| | | Assert test_failed if wdata==’d1 | -| | | | -| | | **Note**: asserted for one clk cycle only. | -| +-----------------------+----------------------------------------------------------------+ -| | 32’h2000_0004 | Assert exit_valid; | -| | | | -| | | exit_value <= wdata; | +| | | Stored Value = [XLEN:1] Exit Code, [0:0] Valid Bit | | | | | | | | **Note**: asserted for one clk cycle only. | +--------------------------+-----------------------+----------------------------------------------------------------+ @@ -166,7 +160,7 @@ Note that the UVM verification environment will use the same test program enviro .. figure:: ../images/TestProgramEnvironment.png :name: Test_Program_Environment_Illustration :align: center - :alt: + :alt: Illustration 9: Board Support Package for "Core" testbench @@ -233,7 +227,7 @@ two contributions have been merged into a single script by Mike Thompson:: } } >dbg - MEM : + MEM : { . = 0x00000000; .vectors : { *(.vectors) } @@ -269,7 +263,7 @@ arguments is deliberately not supported**. Additional Information ...................... -Additional information on the Board Support Package can be found in its associated +Additional information on the Board Support Package can be found in its associated `README `__ in the `core-v-verif `__ GitHub repository. diff --git a/lib/corev-dv/corev_asm_program_gen.sv b/lib/corev-dv/corev_asm_program_gen.sv index 67a089064f..131f90adf3 100644 --- a/lib/corev-dv/corev_asm_program_gen.sv +++ b/lib/corev-dv/corev_asm_program_gen.sv @@ -112,9 +112,15 @@ class corev_asm_program_gen extends riscv_asm_program_gen; instr_stream.push_back($sformatf(" sw %s,0(%s)", td_nam[1].tolower(), td_nam[0].tolower())); instr_stream.push_back($sformatf("")); instr_stream.push_back($sformatf(" csrrwi x0,mie,0 /* clear mie so that final wfi never awakens */")); - instr_stream.push_back($sformatf(" wfi /* we are done */")); instr_stream.push_back($sformatf("#End: Extracted from riscv_compliance_tests/riscv_test.h")); instr_stream.push_back($sformatf("")); + instr_stream.push_back({indent, "li gp, 1"}); + if (cfg.bare_program_mode) begin + instr_stream.push_back({indent, "j write_tohost"}); + end else begin + instr_stream.push_back({indent, "addi a0,x0,48"}); // Shutdown syscall + instr_stream.push_back({indent, "ecall"}); + end endfunction : gen_test_done // Therefore to enable random ecalls in test, simply handle ecall as an exception with no special @@ -127,6 +133,11 @@ class corev_asm_program_gen extends riscv_asm_program_gen; $sformatf("csrw mepc, x%0d", cfg.gpr[0]) }; pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + + instr.push_back("li t0,48"); // Shutdown syscall + instr.push_back("bne a0,t0,1f"); + instr.push_back("j write_tohost"); + instr.push_back("1:"); instr.push_back("mret"); gen_section(get_label("ecall_handler", hart), instr); endfunction : gen_ecall_handler diff --git a/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_mon.sv b/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_mon.sv index dd217305b8..3f78c8ee45 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_mon.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_mon.sv @@ -129,7 +129,7 @@ function void uvma_obi_memory_mon_c::build_phase(uvm_phase phase); if (cntxt == null) begin `uvm_fatal("CNTXT", "Context handle is null") end - passive_mp = cntxt.vif.passive_mp; + passive_mp = cntxt.vif; ap = new("ap" , this); sequencer_ap = new("sequencer_ap", this); diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_virtual_printer_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_virtual_printer_seq.sv index 9b528214bc..17438304dc 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_virtual_printer_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_virtual_printer_seq.sv @@ -77,7 +77,7 @@ task uvma_obi_memory_vp_virtual_printer_seq_c::vp_body(uvma_obi_memory_mon_trn_c end else if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_READ) begin // If reading from virtual printer, simply return 0 - slv_rsp.rdata =0; + slv_rsp.rdata = 0; end add_r_fields(mon_trn, slv_rsp); diff --git a/lib/uvm_libs/uvml_sb/uvml_sb_cntxt.sv b/lib/uvm_libs/uvml_sb/uvml_sb_cntxt.sv index b1345dee84..8a5a3db175 100644 --- a/lib/uvm_libs/uvml_sb/uvml_sb_cntxt.sv +++ b/lib/uvm_libs/uvml_sb/uvml_sb_cntxt.sv @@ -1,19 +1,19 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// // Licensed under the Solderpad Hardware License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVML_SB_CNTXT_SV__ @@ -26,12 +26,12 @@ class uvml_sb_cntxt_c#( type T_TRN = uvml_trn_mon_trn_c ) extends uvm_object; - + // Transaction queues T_TRN act_q [$]; T_TRN exp_q [$]; realtime exp_time_q[$]; - + // Stats int unsigned act_observed = 0; int unsigned exp_observed = 0; @@ -51,12 +51,12 @@ class uvml_sb_cntxt_c#( realtime time_of_first_match = 0; realtime total_latency = 0; realtime avg_latency = 0; - + // Events - uvm_event#(T_TRN) exp_observed_e; - uvm_event#(T_TRN) act_observed_e; - - + uvm_event exp_observed_e; + uvm_event act_observed_e; + + `uvm_object_param_utils_begin(uvml_sb_cntxt_c#(T_TRN)) `uvm_field_int (act_observed , UVM_DEFAULT + UVM_DEC) `uvm_field_int (exp_observed , UVM_DEFAULT + UVM_DEC) @@ -76,41 +76,41 @@ class uvml_sb_cntxt_c#( `uvm_field_real(time_of_first_match , UVM_DEFAULT ) `uvm_field_real(total_latency , UVM_DEFAULT ) `uvm_field_real(avg_latency , UVM_DEFAULT ) - + `uvm_field_event(exp_observed_e, UVM_DEFAULT) `uvm_field_event(act_observed_e, UVM_DEFAULT) `uvm_object_utils_end - - + + /** * Default constructor */ extern function new(string name="uvml_sb_cntxt"); - + /** * Sets all state variables to 0's; */ extern function void reset(); - + endclass : uvml_sb_cntxt_c function uvml_sb_cntxt_c::new(string name="uvml_sb_cntxt"); - + super.new(name); - + exp_observed_e = new("exp_observed_e"); act_observed_e = new("act_observed_e"); - + endfunction : new function void uvml_sb_cntxt_c::reset(); - + act_q .delete(); exp_q .delete(); exp_time_q.delete(); - + act_observed = 0; exp_observed = 0; act_good_observed = 0; @@ -129,7 +129,7 @@ function void uvml_sb_cntxt_c::reset(); time_of_first_match = 0; total_latency = 0; avg_latency = 0; - + endfunction : reset diff --git a/mk/Common.mk b/mk/Common.mk index ea7e58b7e4..5736a95bc4 100644 --- a/mk/Common.mk +++ b/mk/Common.mk @@ -253,10 +253,10 @@ endif ifndef CV_SW_PREFIX ifdef TEST_CV_SW_PREFIX -CV_SW_PREFIX = $(TEST_CV_SW_PREFIX) +export CV_SW_PREFIX = $(TEST_CV_SW_PREFIX) else ifdef CFG_CV_SW_PREFIX -CV_SW_PREFIX = $(CFG_CV_SW_PREFIX) +export CV_SW_PREFIX = $(CFG_CV_SW_PREFIX) else $(error CV_SW_PREFIX not defined in either the shell environment, test.yaml or cfg.yaml) endif @@ -265,12 +265,12 @@ endif ifndef CV_SW_MARCH ifdef TEST_CV_SW_MARCH -CV_SW_MARCH = $(TEST_CV_SW_MARCH) +export CV_SW_MARCH = $(TEST_CV_SW_MARCH) else ifdef CFG_CV_SW_MARCH -CV_SW_MARCH = $(CFG_CV_SW_MARCH) +export CV_SW_MARCH = $(CFG_CV_SW_MARCH) else -CV_SW_MARCH = rv32imc +export CV_SW_MARCH = rv32imc $(warning CV_SW_MARCH not defined in either the shell environment, test.yaml or cfg.yaml) endif endif @@ -477,7 +477,7 @@ ifeq ($(TEST_FIXED_ELF),1) mkdir -p $(SIM_TEST_PROGRAM_RESULTS) cp $(TEST_TEST_DIR)/$(TEST).elf $@ else -%.elf: $(TEST_FILES) +%.elf: svlibs $(TEST_FILES) mkdir -p $(SIM_TEST_PROGRAM_RESULTS) make bsp @echo "$(BANNER)" @@ -525,6 +525,19 @@ clean_bsp: make -C $(BSP) clean rm -rf $(SIM_BSP_RESULTS) +# elfloader lib +VENDOR_ELFLOADER = $(CORE_V_VERIF)/vendor/elfloader +ELFLOADER_LIB = $(VENDOR_ELFLOADER)/elfloader.so + +elfloader_lib: + @echo "$(BANNER)" + @echo "* Compiling the elfloader" + @echo "$(BANNER)" + make -C $(VENDOR_ELFLOADER) \ + DPI_INCLUDE="$(DPI_INCLUDE)" \ + all + +svlibs: elfloader_lib # compile and dump RISCV_TESTS only #$(CV32_RISCV_TESTS_FIRMWARE)/cv32_riscv_tests_firmware.elf: $(CV32_RISCV_TESTS_FIRMWARE_OBJS) $(RISCV_TESTS_OBJS) \ diff --git a/mk/uvmt/vcs.mk b/mk/uvmt/vcs.mk index 6d7821aa2a..6fc9d7cd17 100644 --- a/mk/uvmt/vcs.mk +++ b/mk/uvmt/vcs.mk @@ -183,6 +183,8 @@ VCS_RUN_BASE_FLAGS ?= $(VCS_GUI) \ -assert nopostproc \ -sv_lib $(abspath $(VCS_SVLIB_LIB)) +VCS_RUN_BASE_FLAGS += -sv_lib $(basename $(ELFLOADER_LIB)) + # Simulate using latest elab VCS_RUN_FLAGS ?= VCS_RUN_FLAGS += $(VCS_RUN_BASE_FLAGS) @@ -452,4 +454,4 @@ clean_rtl: rm -rf $(CV_CORE_PKG) # All generated files plus the clone of the RTL -clean_all: clean clean_test clean_rtl clean_eclipse clean_riscv-dv clean_test_programs clean_bsp clean_compliance clean_embench clean_dpi_dasm_spike clean_svlib +clean_all: clean clean_test clean_rtl clean_eclipse clean_riscv-dv clean_test_programs clean_bsp clean_compliance clean_embench clean_dpi_dasm_spike clean_svlib diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk index a46e34d5c1..b29310e080 100644 --- a/mk/uvmt/vsim.mk +++ b/mk/uvmt/vsim.mk @@ -34,7 +34,7 @@ VCOVER = vcover VWORK = work VSIM_COV_MERGE_DIR = $(SIM_CFG_RESULTS)/$(CFG)/merged UVM_HOME ?= $(abspath $(shell which $(VLIB))/../../verilog_src/uvm-1.2/src) -DPI_INCLUDE ?= $(abspath $(shell which $(VLIB))/../../include) +DPI_INCLUDE ?= $(abspath $(shell dirname $(shell which $(VLIB)))/../include) USES_DPI = 1 # Default flags @@ -185,6 +185,7 @@ VSIM_FLAGS += +DISABLE_CSR_CHECK=$(TEST_DISABLE_CSR_CHECK) endif VSIM_FLAGS += -sv_lib $(basename $(DPI_DASM_LIB)) +VSIM_FLAGS += -sv_lib $(basename $(ELFLOADER_LIB)) VSIM_FLAGS += -sv_lib $(basename $(abspath $(SVLIB_LIB))) # Skip compile if requested (COMP=NO) @@ -399,7 +400,7 @@ gen_corev-dv: comp_corev-dv: $(RISCVDV_PKG) $(CV_CORE_PKG) vlog_corev-dv vopt_corev-dv -corev-dv: clean_riscv-dv clone_riscv-dv comp_corev-dv +corev-dv: clone_riscv-dv comp_corev-dv ############################################################################### # Run a single test-program from the RISC-V Compliance Test-suite. The parent diff --git a/vendor/elfloader/Makefile b/vendor/elfloader/Makefile new file mode 100644 index 0000000000..8b441b3aac --- /dev/null +++ b/vendor/elfloader/Makefile @@ -0,0 +1,45 @@ +# Copyright 2023 OpenHW Group +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Makefile for the elfloader vendor folder +SO_NAME = elfloader.so + +SRC = elfloader.cc +OBJ = elfloader.o + +SPIKE_ROOT ?= + +EDA_INCLUDES = -I$(VCS_HOME)/include -I/$(QUESTASIM_HOME)/include -I$(XCEL_HOME)/include + +CFLAGS ?= -Os -g -I/$(SPIKE_ROOT)/include/ $(EDA_INCLUDES) -std=c++17 +CFLAGS_SO ?= -fPIC -DSHARED + +LDFLAGS ?= -lstdc++ +LDFLAGS_SO ?= -shared + +CCX = g++ + +MIN_GCC_VERSION = "4.9" +GCC_VERSION := $(shell gcc -dumpversion) +IS_GCC_ABOVE_MIN_VERSION := $(shell expr "$(GCC_VERSION)" ">=" "$(MIN_GCC_VERSION)") +ifneq "$(IS_GCC_ABOVE_MIN_VERSION)" "1" + $(error ERROR: gcc version $(GCC_VERSION) is lower than $(MIN_GCC_VERSION), 'gcc' might fail) +endif + + +all: $(SO_NAME) + + +%.o : %.cc + $(CCX) $(CFLAGS) $(CFLAGS_SO) -c $< -o $@ + +%.so : $(OBJ) + $(CCX) $(CFLAGS) $(CFLAGS_SO) $(LDFLAGS) $(LDFLAGS_SO) $< -o $@ + +%.x : + $(CCX) $(LDFLAGS) $(CFLAGS) $(SRC) -o $@ + + +clean: + rm -f $(OBJ) $(SO_NAME) + diff --git a/vendor/elfloader/elfloader.cc b/vendor/elfloader/elfloader.cc new file mode 100644 index 0000000000..ab055fbee0 --- /dev/null +++ b/vendor/elfloader/elfloader.cc @@ -0,0 +1,149 @@ +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SHT_PROGBITS 0x1 +#define SHT_GROUP 0x11 + +using namespace std; + +// address and size +std::vector> sections; +std::map symbols; +// memory based address and content +std::map> mems; +reg_t entry; +int section_index = 0; + +void write (uint64_t address, uint64_t len, uint8_t* buf) { + uint64_t datum; + std::vector mem; + for (int i = 0; i < len; i++) { + mem.push_back(buf[i]); + } + mems.insert(std::make_pair(address, mem)); +} + +// Communicate the section address and len +// Returns: +// 0 if there are no more sections +// 1 if there are more sections to load +extern "C" char get_section (long long* address, long long* len) { + if (section_index < sections.size()) { + *address = sections[section_index].first; + *len = sections[section_index].second; + section_index++; + return 1; + } else return 0; +} + +extern "C" void read_section (long long address, const svOpenArrayHandle buffer) { + // get actual poitner + void* buf = svGetArrayPtr(buffer); + // check that the address points to a section + assert(mems.count(address) > 0); + // copy array + int i = 0; + for (auto &datum : mems.find(address)->second) { + *((char *) buf + i) = datum; + i++; + } +} + +extern "C" void read_elf(const char* filename) { + int fd = open(filename, O_RDONLY); + struct stat s; + assert(fd != -1); + if (fstat(fd, &s) < 0) + abort(); + size_t size = s.st_size; + + char* buf = (char*)mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd, 0); + assert(buf != MAP_FAILED); + close(fd); + + assert(size >= sizeof(Elf64_Ehdr)); + const Elf64_Ehdr* eh64 = (const Elf64_Ehdr*)buf; + assert(IS_ELF32(*eh64) || IS_ELF64(*eh64)); + + std::vector zeros; + + #define LOAD_ELF(ehdr_t, phdr_t, shdr_t, sym_t) do { \ + ehdr_t* eh = (ehdr_t*)buf; \ + phdr_t* ph = (phdr_t*)(buf + eh->e_phoff); \ + entry = eh->e_entry; \ + assert(size >= eh->e_phoff + eh->e_phnum*sizeof(*ph)); \ + for (unsigned i = 0; i < eh->e_phnum; i++) { \ + if(ph[i].p_type == PT_LOAD && ph[i].p_memsz) { \ + if (ph[i].p_filesz) { \ + assert(size >= ph[i].p_offset + ph[i].p_filesz); \ + sections.push_back(std::make_pair(ph[i].p_paddr, ph[i].p_memsz)); \ + write(ph[i].p_paddr, ph[i].p_filesz, (uint8_t*)buf + ph[i].p_offset); \ + } \ + if (size_t pad = (ph[i].p_memsz) - (ph[i].p_filesz)) { \ + zeros.resize(ph[i].p_memsz - ph[i].p_filesz); \ + write(ph[i].p_paddr + ph[i].p_filesz, pad, \ + zeros.data()); \ + } \ + } \ + } \ + shdr_t* sh = (shdr_t*)(buf + eh->e_shoff); \ + assert(size >= eh->e_shoff + eh->e_shnum*sizeof(*sh)); \ + assert(eh->e_shstrndx < eh->e_shnum); \ + assert(size >= sh[eh->e_shstrndx].sh_offset + \ + sh[eh->e_shstrndx].sh_size); \ + char *shstrtab = buf + sh[eh->e_shstrndx].sh_offset; \ + unsigned strtabidx = 0, symtabidx = 0; \ + for (unsigned i = 0; i < eh->e_shnum; i++) { \ + unsigned max_len = sh[eh->e_shstrndx].sh_size - sh[i].sh_name; \ + if ((sh[i].sh_type & SHT_GROUP) && strcmp(shstrtab + sh[i].sh_name, ".strtab") != 0 && strcmp(shstrtab + sh[i].sh_name, ".shstrtab") != 0) \ + assert(strnlen(shstrtab + sh[i].sh_name, max_len) < max_len); \ + if (sh[i].sh_type & SHT_NOBITS) continue; \ + if (strcmp(shstrtab + sh[i].sh_name, ".strtab") == 0) \ + strtabidx = i; \ + if (strcmp(shstrtab + sh[i].sh_name, ".symtab") == 0) \ + symtabidx = i; \ + } \ + if (strtabidx && symtabidx) { \ + char* strtab = buf + sh[strtabidx].sh_offset; \ + sym_t* sym = (sym_t*)(buf + sh[symtabidx].sh_offset); \ + for (unsigned i = 0; i < sh[symtabidx].sh_size/sizeof(sym_t); i++) { \ + unsigned max_len = sh[strtabidx].sh_size - sym[i].st_name; \ + assert(sym[i].st_name < sh[strtabidx]. sh_size); \ + assert(strnlen(strtab + sym[i].st_name, max_len) < max_len); \ + string s = (strtab + sym[i].st_name);\ + symbols[s] = sym[i].st_value; \ + } \ + } \ + } while(0) + + if (IS_ELF32(*eh64)) + LOAD_ELF(Elf32_Ehdr, Elf32_Phdr, Elf32_Shdr, Elf32_Sym); + else + LOAD_ELF(Elf64_Ehdr, Elf64_Phdr, Elf64_Shdr, Elf64_Sym); + + munmap(buf, size); +} + +extern "C" int64_t read_symbol(const char* symbol, uint64_t* address) { + auto it = symbols.find(symbol); + if (it != symbols.end()) { + *address = it->second; + return 0; + } + return 1; +}