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<!DOCTYPE html>
<html>
<head>
<meta name="generator" content="Hugo 0.118.2">
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1">
<title>Olivia Weng</title>
<link rel="stylesheet" href="/css/style.css">
</head>
<body>
<div class="nav">
<a href="/about">About</a>
<a href="/projects">Projects</a>
<a href="/">Home</a>
</div>
<div class="meta">
<h1>Olivia Weng</h1>
<h2>computer architect.</h2>
<h3><script type="text/javascript" src="date.js"></script> </h3>
<p>oweng at ucsd edu</p>
<a href="weng_cv.pdf">Curriculum vitae</a>
</div>
<h2 id="publications">Publications</h2>
<ol>
<li>
<p><strong>Olivia Weng</strong>, Marta Andronic, Danial Zuberi, Jiaqing Chen, Caleb Geniesse, George A. Constantinides, Nhan Tran, Nicholas Fraser, Javier Mauricio Duarte, Ryan Kastner. <a href="/">Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT</a>. In submission.</p>
</li>
<li>
<p>Colin Drewes, Tyler Sheaves, <strong>Olivia Weng</strong>, Keegan Ryan, William Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond. <a href="https://dl.acm.org/doi/pdf/10.1145/3666092">Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters</a>. In <em>ACM Transactions on Reconfigurable Technology and Systems (TRETS) 17, 3, Article 49</em>. September 2024.</p>
</li>
<li>
<p><strong>Olivia Weng</strong>, Andres Meza, Quinlan Bock, Benjamin Hawks, Javier Campos, Nhan Tran, Javier Duarte, Ryan Kastner. <a href="https://dl.acm.org/doi/pdf/10.1145/3665334">FKeras: A Sensitivity Analysis Tool for Edge Neural Networks</a>. In <em>ACM Journal on Autonomous Transportation Systems 1, 3, Article 15</em>. September 2024.</p>
</li>
<li>
<p>Colin Drewes, <strong>Olivia Weng</strong>, Andres Meza, Alric Althoff, Bill Hunter, David Kohlbrenner, Ryan Kastner, Dustin Richmond. <a href="https://dl.acm.org/doi/pdf/10.1145/3620665.3640355">Pentimento: Data Residue in Cloud FPGAs</a>. In <em>Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)</em>. San Diego, CA. April 2024.</p>
</li>
<li>
<p>Tommaso Baldi, Javi Campos, Ben Hawks, Jennifer Ngadiuba, Nhan Tran, Daniel Diaz, Javier Duarte, Ryan Kastner, Andres Meza, Melissa Quinnan, <strong>Olivia Weng</strong>, Caleb Geniesse, Amir Gholami, Michael W. Mahoney, Vladimir Loncar, Philip Harris, Joshua Agar, Shuyu Qin. <a href="https://ieeexplore.ieee.org/abstract/document/10538639">Reliable edge machine learning hardware for scientific applications</a>. In <em>IEEE 42nd VLSI Test Symposium (VTS)</em>. Tempe, AZ. April 2024.</p>
</li>
<li>
<p><strong>Olivia Weng</strong>, Gabriel Marcano, Vladimir Loncar, Alireza Khodamoradi, Abarajithan G, Nojan Sheybani, Andres Meza, Farinaz Koushanfar, Kristof Denolf, Javier Mauricio Duarte, Ryan Kastner. <a href="https://dl.acm.org/doi/pdf/10.1145/3624990">Tailor: Altering Skip Connections for Resource-Efficient Inference</a>. In <em>ACM Transactions on Reconfigurable Technology and Systems (TRETS) 17, 1, Article 11</em>. January 2024.</p>
</li>
<li>
<p><strong>Olivia Weng</strong>, Gabriel Marcano, Vladimir Loncar, Alireza Khodamoradi, Nojan Sheybani, Kristof Denolf, Farinaz Koushanfar, Javier Duarte, Ryan Kastner.
<a href="https://dl.acm.org/doi/10.1145/3543622.3573172">Adapting Skip Connections for Resource-Efficient FPGA Inference</a>. In <em>Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA)</em>. Monterey, CA. February 2023.</p>
</li>
<li>
<p>Colin Drewes, <strong>Olivia Weng</strong>, Keegan Ryan, William Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond. <a href="https://dl.acm.org/doi/pdf/10.1145/3543622.3573193">Turn on, Tune in, Listen up: Maximizing Channel Capacity in Time-to-Digital Converters</a>. In <em>Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA)</em>. Monterey, CA. February 2023. <strong>Nominated for Best Paper.</strong></p>
</li>
<li>
<p>Hendrik Borras, Giuseppe Di Guglielmo, Javier Duarte, Nicolò Ghielmetti, Ben Hawks, Scott Hauck, Shih-Chieh Hsu, Ryan Kastner, Jason Liang, Andres Meza, Jules Muhizi, Tai Nguyen, Rushil Roy, Nhan Tran, Yaman Umuroglu, <strong>Olivia Weng</strong>, Aidan Yokuda, Michaela Blott. <a href="https://arxiv.org/abs/2206.11791">Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark</a>. In <em>Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware (MLBench) at Conference on Machine Learning and Systems (MLSys)</em>. August 2022.</p>
</li>
<li>
<p><strong>Olivia Weng</strong>. <a href="https://arxiv.org/abs/2112.06126">Neural Network Quantization for Efficient Inference: A Survey</a>. <em>arXiv:2112.06126.</em> December 2021.</p>
</li>
<li>
<p>Colin Drewes, Steven Harris, Winnie Wang, Richard Appen, <strong>Olivia Weng</strong>, Ryan Kastner, William Hunter, Christopher McCarty, Dustin Richmond. <a href="https://ieeexplore.ieee.org/abstract/document/9444070">A Tunable Dual-Edge Time-to-Digital Converter</a>. In <em>IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)</em>. Virtual, May 2021.</p>
</li>
<li>
<p>Michael Barrow, <strong>Olivia Weng</strong>, and Ryan Kastner. <a href="/papers/recode2021.pdf">Design Space Exploration for Machine Learning Architectures</a>. In <em>Workshop on Reimagining Codesign hosted by US DOE, Office of Advanced Scientific Computing Research</em>. Virtual, March 2021.</p>
</li>
<li>
<p><strong>Olivia Weng</strong>, Alireza Khodamoradi, and Ryan Kastner. <a href="https://arxiv.org/abs/2102.01351">Hardware-efficient Residual Networks for FPGAs</a>. In <em>Proceedings of Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA) at Design, Automation and Test in Europe (DATE)</em>. <del>Grenoble, France</del> (Virtual), February 2021.</p>
</li>
<li>
<p><strong>Olivia Weng</strong> and Andrew A. Chien. <a href="/papers/accml_2020.pdf">Evaluating Achievable Latency and Cost: SSD Latency Predictors</a>. In <em>Workshop on Accelerated Machine Learning (AccML) at High Performance Embedded Architectures and Compilers (HiPEAC)</em>. Bologna, Italy, January 2020.</p>
</li>
</ol>
<div class="posts">
<h2>Blog</h2>
<a href=http://oliviaweng.github.io/blog/lunch-walks/>
<div class="post-summary">
<div class="title">On taking walks after lunch</div>
<div class="date">Nov 29, 2019</div>
<div class="description">In which I reflect on the joys of taking walks</div>
<div class="minutes">3 minute read</div>
</div>
</a>
</div>
</body>