diff --git a/arch/arm64/boot/dts/freescale/mt-connect.dts b/arch/arm64/boot/dts/freescale/mt-connect.dts
index 1bd54308b3b5..1216dbb979f2 100644
--- a/arch/arm64/boot/dts/freescale/mt-connect.dts
+++ b/arch/arm64/boot/dts/freescale/mt-connect.dts
@@ -128,7 +128,7 @@
 		#size-cells = <0>;
 
 		ethphy: ethernet-phy@1 {
-			compatible = "ethernet-phy-id0022.1642",
+			compatible = "ethernet-phy-id0022.1640",
 			"ethernet-phy-ieee802.3-c22";
 			pinctrl-0 = <&pinctrl_ethphy>;
 			pinctrl-names = "default";
@@ -137,7 +137,6 @@
 			reg = <1>;
 			reset-assert-us = <1000>;
 			reset-deassert-us = <1000>;
-			reset-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
 			status = "okay";
 		};
 	};
@@ -371,44 +370,44 @@
 
 	pinctrl_fec1: fec1grp {
 		fsl,pins =
-			<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
-			<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
-			<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
-			<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
-			<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
-			<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
-			<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
-			<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
-			<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f>,
-			<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f>,
-			<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f>,
-			<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f>,
-			<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f>,
-			<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f>;
+		<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
+		<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
+		<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
+		<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
+		<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
+		<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
+		<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
+		<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
+		<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f>,
+		<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f>,
+		<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f>,
+		<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f>,
+		<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f>,
+		<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f>;
 	};
 
 	pinctrl_fec1_sleep: fec1-sleepgrp {
 		fsl,pins =
-			<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
-			<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
-			<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
-			<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
-			<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
-			<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
-			<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
-			<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
-			<MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21		0x1f>,
-			<MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20		0x1f>,
-			<MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19		0x1f>,
-			<MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18		0x1f>,
-			<MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23		0x1f>,
-			<MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x1f>;
+		<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
+		<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
+		<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
+		<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
+		<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
+		<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
+		<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
+		<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
+		<MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21		0x1f>,
+		<MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20		0x1f>,
+		<MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19		0x1f>,
+		<MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18		0x1f>,
+		<MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23		0x1f>,
+		<MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x1f>;
 	};
 
 	pinctrl_ethphy: dhcom-ethphy-grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3			0x1c4
-			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4			0x1c4
+		MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3			0x1c4
+		MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4			0x1c4
 		>;
 	};