merge: add updates to refactor

.github/workflows/main.yml

@@ -15,9 +15,14 @@ jobs:
 
     steps:
       - uses: actions/checkout@v3
+      - run: rustup toolchain install stable --profile minimal
+      - uses: Swatinem/rust-cache@v2
+
       - name: Build
         run: cargo build --verbose
       - name: Clippy
         run: cargo clippy --verbose
       - name: Tests
         run: cargo test --verbose
+      - name: Fmt
+        run: cargo fmt -- --check

src/circom/input.rs

@@ -0,0 +1 @@
+

src/circuit.rs

@@ -34,23 +34,40 @@ pub enum AGateType {
     ANeq,
     ASub,
     AXor,
+    APow,
+    AIntDiv,
+    AMod,
+    AShiftL,
+    AShiftR,
+    ABoolOr,
+    ABoolAnd,
+    ABitOr,
+    ABitAnd,
 }
 
 impl From<&ExpressionInfixOpcode> for AGateType {
     fn from(opcode: &ExpressionInfixOpcode) -> Self {
         match opcode {
-            ExpressionInfixOpcode::Add => AGateType::AAdd,
+            ExpressionInfixOpcode::Mul => AGateType::AMul,
             ExpressionInfixOpcode::Div => AGateType::ADiv,
-            ExpressionInfixOpcode::Eq => AGateType::AEq,
-            ExpressionInfixOpcode::Greater => AGateType::AGt,
+            ExpressionInfixOpcode::Add => AGateType::AAdd,
+            ExpressionInfixOpcode::Sub => AGateType::ASub,
+            ExpressionInfixOpcode::Pow => AGateType::APow,
+            ExpressionInfixOpcode::IntDiv => AGateType::AIntDiv,
+            ExpressionInfixOpcode::Mod => AGateType::AMod,
+            ExpressionInfixOpcode::ShiftL => AGateType::AShiftL,
+            ExpressionInfixOpcode::ShiftR => AGateType::AShiftR,
+            ExpressionInfixOpcode::LesserEq => AGateType::ALEq,
             ExpressionInfixOpcode::GreaterEq => AGateType::AGEq,
             ExpressionInfixOpcode::Lesser => AGateType::ALt,
-            ExpressionInfixOpcode::LesserEq => AGateType::ALEq,
-            ExpressionInfixOpcode::Mul => AGateType::AMul,
+            ExpressionInfixOpcode::Greater => AGateType::AGt,
+            ExpressionInfixOpcode::Eq => AGateType::AEq,
             ExpressionInfixOpcode::NotEq => AGateType::ANeq,
-            ExpressionInfixOpcode::Sub => AGateType::ASub,
+            ExpressionInfixOpcode::BoolOr => AGateType::ABoolOr,
+            ExpressionInfixOpcode::BoolAnd => AGateType::ABoolAnd,
+            ExpressionInfixOpcode::BitOr => AGateType::ABitOr,
+            ExpressionInfixOpcode::BitAnd => AGateType::ABitAnd,
             ExpressionInfixOpcode::BitXor => AGateType::AXor,
-            _ => unimplemented!("Unsupported opcode"),
         }
     }
 }
@@ -69,6 +86,15 @@ impl From<&AGateType> for Operation {
             AGateType::AGt => Operation::GreaterThan,
             AGateType::AGEq => Operation::GreaterOrEqual,
             AGateType::AXor => Operation::XorBitwise,
+            AGateType::APow => Operation::Exponentiate,
+            AGateType::AIntDiv => Operation::IntegerDivide,
+            AGateType::AMod => Operation::Modulus,
+            AGateType::AShiftL => Operation::ShiftLeft,
+            AGateType::AShiftR => Operation::ShiftRight,
+            AGateType::ABoolOr => Operation::Or,
+            AGateType::ABoolAnd => Operation::And,
+            AGateType::ABitOr => Operation::OrBitwise,
+            AGateType::ABitAnd => Operation::AndBitwise,
         }
     }
 }

tests/circuits/infixOps.circom

@@ -0,0 +1,74 @@
+pragma circom 2.0.0;
+
+template infixOps() {
+    signal input x0;
+    signal input x1;
+    signal input x2;
+    signal input x3;
+    signal input x4;
+    signal input x5;
+
+    signal output mul_2_3;
+    signal output div_4_3;
+    signal output idiv_4_3;
+    signal output add_3_4;
+    signal output sub_4_1;
+    signal output pow_2_4;
+    signal output mod_5_3;
+    signal output shl_5_1;
+    signal output shr_5_1;
+    signal output leq_2_3;
+    signal output leq_3_3;
+    signal output leq_4_3;
+    signal output geq_2_3;
+    signal output geq_3_3;
+    signal output geq_4_3;
+    signal output lt_2_3;
+    signal output lt_3_3;
+    signal output lt_4_3;
+    signal output gt_2_3;
+    signal output gt_3_3;
+    signal output gt_4_3;
+    signal output eq_2_3;
+    signal output eq_3_3;
+    signal output neq_2_3;
+    signal output neq_3_3;
+    signal output or_0_1;
+    signal output and_0_1;
+    signal output bit_or_1_3;
+    signal output bit_and_1_3;
+    signal output bit_xor_1_3;
+
+    mul_2_3 <== x2 * x3;
+    div_4_3 <== x4 / x3;
+    idiv_4_3 <== x4 \ x3;
+    add_3_4 <== x3 + x4;
+    sub_4_1 <== x4 - x1;
+    pow_2_4 <== x2 ** x4;
+    mod_5_3 <== x5 % x3;
+    shl_5_1 <== x5 << x1;
+    shr_5_1 <== x5 >> x1;
+    leq_2_3 <== x2 <= x3;
+    leq_3_3 <== x3 <= x3;
+    leq_4_3 <== x4 <= x3;
+    geq_2_3 <== x2 >= x3;
+    geq_3_3 <== x3 >= x3;
+    geq_4_3 <== x4 >= x3;
+    lt_2_3 <== x2 < x3;
+    lt_3_3 <== x3 < x3;
+    lt_4_3 <== x4 < x3;
+    gt_2_3 <== x2 > x3;
+    gt_3_3 <== x3 > x3;
+    gt_4_3 <== x4 > x3;
+    eq_2_3 <== x2 == x3;
+    eq_3_3 <== x3 == x3;
+    neq_2_3 <== x2 != x3;
+    neq_3_3 <== x3 != x3;
+    or_0_1 <== x0 || x1;
+    and_0_1 <== x0 && x1;
+    bit_or_1_3 <== x1 | x3;
+    bit_and_1_3 <== x1 & x3;
+    bit_xor_1_3 <== x1 ^ x3;
+}
+
+component main = infixOps();

tests/circuits/underConstrained.circom

@@ -0,0 +1,7 @@
+pragma circom 2.0.0;
+
+template underConstrained() {
+    signal output x;
+}
+
+component main = underConstrained();

tests/circuits/xEqX.circom

@@ -0,0 +1,10 @@
+pragma circom 2.0.0;
+
+template xEqX() {
+    signal input x;
+    signal output out;
+
+    out <== x == x;
+}
+
+component main = xEqX();

tests/infix_ops.rs

@@ -0,0 +1,50 @@
+use circom_2_arithc::{program::build_circuit, Args};
+
+const TEST_FILE_PATH: &str = "./tests/circuits/infixOps.circom";
+
+#[test]
+fn test_infix_ops() {
+    let input = Args::new(TEST_FILE_PATH.into(), "./".into());
+    let circuit = build_circuit(&input).unwrap();
+    let sim_circuit = circuit.build_sim_circuit().unwrap();
+
+    let circuit_input = vec![0, 1, 2, 3, 4, 5];
+
+    let res = sim_circuit.execute(&circuit_input).unwrap();
+
+    assert_eq!(
+        res,
+        vec![
+            6,  // 2  * 3
+            1,  // 4  / 3 // TODO: Should this behave differently? (finite field division)
+            1,  // 4  \ 3 // (This one is definitely int division)
+            7,  // 3  + 4
+            3,  // 4  - 1
+            16, // 2 ** 4
+            2,  // 5  % 3
+            10, // 5 << 1
+            2,  // 5 >> 1
+            1,  // 2 <= 3
+            1,  // 3 <= 3
+            0,  // 4 <= 3
+            0,  // 2 >= 3
+            1,  // 3 >= 3
+            1,  // 4 >= 3
+            1,  // 2  < 3
+            0,  // 3  < 3
+            0,  // 4  < 3
+            0,  // 2  > 3
+            0,  // 3  > 3
+            1,  // 4  > 3
+            0,  // 2 == 3
+            1,  // 3 == 3
+            1,  // 2 != 3
+            0,  // 3 != 3
+            1,  // 0 || 1
+            0,  // 0 && 1
+            3,  // 1  | 3
+            1,  // 1  & 3
+            2,  // 1  ^ 3
+        ]
+    );
+}

tests/under_constrained.rs

@@ -0,0 +1,17 @@
+use circom_2_arithc::{program::build_circuit, Args};
+
+const TEST_FILE_PATH: &str = "./tests/circuits/underConstrained.circom";
+
+#[test]
+fn test_under_constrained() {
+    let input = Args::new(TEST_FILE_PATH.into(), "./".into());
+
+    // TODO: Should this be an error because the circuit is under-constrained?
+    let circuit = build_circuit(&input).unwrap();
+
+    let sim_circuit = circuit.build_sim_circuit().unwrap();
+
+    let res = sim_circuit.execute(&[]).unwrap();
+
+    assert_eq!(res, Vec::<u32>::new());
+}

tests/x_eq_x.rs

@@ -0,0 +1,14 @@
+use circom_2_arithc::{program::build_circuit, Args};
+
+const TEST_FILE_PATH: &str = "./tests/circuits/xEqX.circom";
+
+#[test]
+fn test_x_eq_x() {
+    let input = Args::new(TEST_FILE_PATH.into(), "./".into());
+    let circuit = build_circuit(&input).unwrap();
+    let sim_circuit = circuit.build_sim_circuit().unwrap();
+
+    let circuit_input = vec![1];
+    let res = sim_circuit.execute(&circuit_input).unwrap();
+    assert_eq!(res, vec![1]);
+}