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``When someone says, 'I want a programming language in which I need only say what I wish done', give him a lollipop.'' -Alan Perlis
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This book focuses on the use of algorithmic high-level synthesis (HLS) to build application-specific FPGA systems.  Our goal is to give the reader an appreciation of the process of creating an optimized hardware design using HLS. Although the details are, of necessity, different from parallel programming for multicore processors or GPUs, many of the fundamental concepts are similar.  For example, designers must understand memory hierarchy and bandwidth, spatial and temporal locality of reference, parallelism, and tradeoffs between computation and storage.

This book is a practical guide for anyone interested in building FPGA systems.  In a university environment, it is appropriate for advanced undergraduate and graduate courses.  At the same time, it is also useful for practicing system designers and embedded programmers.  The book assumes the reader has a working knowledge of C/C++ and includes a significant amount of sample code. In addition, we assume familiarity with basic computer architecture concepts (pipelining, speedup, Amdahl's Law, etc.).  A knowledge of the RTL-based FPGA design flow is helpful, although not required.

The book includes several features that make it particularly valuable in a classroom environment.  It includes questions within each chapter that will challenge the reader to solidify their understanding of the material.  There are associated projects and labs that were developed and used in the HLS class taught at UCSD (CSE 237C) that are available at Read the Docs (\url{https://pp4fpgas.readthedocs.io/}). The projects teach concepts in HLS using examples in the domain of digital signal processing with a focus on developing wireless communication systems.  Each project is more or less associated with one chapter in the book. The labs aim to help understand how to integrate HLS designs into an FPGA system on chip. The projects and labs have reference designs targeting FPGA boards distributed through the Xilinx University Program (\url{http://www.xilinx.com/support/university.html}).   The FPGA boards are available for commercial purchase.  Any reader of the book is encouraged to request an evaluation license of \VHLS at \url{http://www.xilinx.com}.

This book is {\em not} primarily about HLS algorithms.  There are many excellent resources that provide details about the HLS process including algorithms for scheduling, resource allocation, and binding \cite{micheli1994synthesis, gupta2004spark, coussy2010high, gajski2012high}.  This book is valuable in a course that focuses on these concepts as supplementary material, giving students an idea of how the algorithms fit together in a coherent form, and providing concrete use cases of applications developed in a HLS language.  This book is also {\em not} primarily about the intricacies of FPGA architectures or RTL design techniques.  However, again it may be valuable as supplementary material for those looking to understand more about the system-level context.

This book focuses on using Xilinx tools for implementing designs, in particular \VHLS to perform the translation from C-like code to RTL.  C programming examples are given that are specific to the syntax used in \VHLS.  In general, the book explains not only \VHLS specifics, but also the underlying generic HLS concepts that are often found in other tools.  We encourage readers with access to other tools to understand how these concepts are interpreted in any HLS tool they may be using.

Good luck and happy programming!