From 974f4e65aa4d33d20ded9b01e48eedb8334bb281 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 28 Apr 2020 16:09:23 -0700 Subject: [PATCH] Add 'riscv32' as an alias for riscv All of the RISC-V support runs on either 32- or 64- bit architectures, but sometimes users will specific riscv32 or riscv64 explicitly. Allow this by mapping riscv32 to riscv sources (as is already done for riscv64). Signed-off-by: Keith Packard --- newlib/libc/meson.build | 1 + newlib/libc/picolib/meson.build | 1 + newlib/libm/meson.build | 1 + picocrt/meson.build | 1 + semihost/meson.build | 1 + test-riscv32.ld | 5 +++++ test-riscv64.ld | 5 +++++ 7 files changed, 15 insertions(+) create mode 100644 test-riscv32.ld create mode 100644 test-riscv64.ld diff --git a/newlib/libc/meson.build b/newlib/libc/meson.build index d210de641e..2da3ca2bf1 100644 --- a/newlib/libc/meson.build +++ b/newlib/libc/meson.build @@ -83,6 +83,7 @@ machine_dirs = { 'or1knd': 'or1k', 'powerpc': 'powerpc', 'riscv': 'riscv', + 'riscv32': 'riscv', 'riscv64': 'riscv', 'rl78': 'rl78', 'rx': 'rx', diff --git a/newlib/libc/picolib/meson.build b/newlib/libc/picolib/meson.build index 09ed2104f3..14a104b56b 100644 --- a/newlib/libc/picolib/meson.build +++ b/newlib/libc/picolib/meson.build @@ -34,6 +34,7 @@ # srcs_machine_tls = { 'riscv' : ['machine/riscv/tls.c'], + 'riscv32' : ['machine/riscv/tls.c'], 'riscv64' : ['machine/riscv/tls.c'], 'arm' : ['machine/arm/tls.c'] } diff --git a/newlib/libm/meson.build b/newlib/libm/meson.build index 3eb7b17699..154ebde525 100644 --- a/newlib/libm/meson.build +++ b/newlib/libm/meson.build @@ -41,6 +41,7 @@ libm_machine_dirs = { 'i686' : 'i386', 'nds32' : 'nds32', 'riscv' : 'riscv', + 'riscv32' : 'riscv', 'riscv64' : 'riscv', 'spu' : 'spu', 'xtensa': 'xtensa', diff --git a/picocrt/meson.build b/picocrt/meson.build index 66db020571..798af01d55 100644 --- a/picocrt/meson.build +++ b/picocrt/meson.build @@ -34,6 +34,7 @@ # src_picocrt_machine = { 'riscv' : 'riscv/crt0.c', + 'riscv32' : 'riscv/crt0.c', 'riscv64' : 'riscv/crt0.c', 'arm' : 'arm/crt0.c' } diff --git a/semihost/meson.build b/semihost/meson.build index 6e9e4f37bb..141e4838a6 100644 --- a/semihost/meson.build +++ b/semihost/meson.build @@ -34,6 +34,7 @@ # src_semihost_machine = { 'riscv' : 'riscv/semihost-riscv.s', + 'riscv32' : 'riscv/semihost-riscv.s', 'riscv64' : 'riscv/semihost-riscv.s', 'arm' : 'arm/semihost-arm.c' } diff --git a/test-riscv32.ld b/test-riscv32.ld new file mode 100644 index 0000000000..b9a5b8163e --- /dev/null +++ b/test-riscv32.ld @@ -0,0 +1,5 @@ +__flash = 0x80000000; +__flash_size = 0x00200000; +__ram = 0x80200000; +__ram_size = 0x200000; +__stack_size = 1k; diff --git a/test-riscv64.ld b/test-riscv64.ld new file mode 100644 index 0000000000..b9a5b8163e --- /dev/null +++ b/test-riscv64.ld @@ -0,0 +1,5 @@ +__flash = 0x80000000; +__flash_size = 0x00200000; +__ram = 0x80200000; +__ram_size = 0x200000; +__stack_size = 1k;