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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>datasheet for qsys</title>
<style type="text/css">
body { font-family:arial ;}
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a:hover { text-decoration:underline ; color:0030f0 ;}
td { padding : 5px ;}
table.topTitle { width:100% ;}
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
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table.blueBar { width : 100% ; border-spacing : 0px ;}
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
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.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
.flowbox { display:inline-block ;}
.parametersbox table { font-size:10px ;}
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</head>
<body>
<table class="topTitle">
<tr>
<td class="l">qsys</td>
<td class="r">
<br/>
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
<td class="l">2013.03.15.10:33:40</td>
<td class="r">Datasheet</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Overview</div>
<div class="greydiv">
<div style="display:inline-block ; text-align:left">
<table class="connectionboxes">
<tr>
<td class="lefthandwire">  clk_50 </td>
<td class="main" rowspan="6">qsys</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td></td>
<td class="righthandlabel">  
<a href="#module_uart"><b>uart</b>
</a>
</td>
</tr>
<tr>
<td></td>
<td class="righthandwire"> rxd  </td>
</tr>
<tr>
<td></td>
<td class="righthandwire"> txd  </td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
</table>
</div><span style="display:inline-block ; width:28px"> </span>
<div style="display:inline-block ; text-align:left"><span>Processor
<br/>  
<a href="#module_cpu"><b>cpu</b>
</a> Nios II 12.1
<br/>All Components
<br/>  
<a href="#module_cpu"><b>cpu</b>
</a> altera_nios2_qsys 12.1
<br/>  
<a href="#module_ram_mmu"><b>ram_mmu</b>
</a> altera_avalon_onchip_memory2 12.1
<br/>  
<a href="#module_sdram"><b>sdram</b>
</a> altera_avalon_new_sdram_controller 12.1
<br/>  
<a href="#module_jtag"><b>jtag</b>
</a> altera_avalon_jtag_uart 12.1
<br/>  
<a href="#module_timer"><b>timer</b>
</a> altera_avalon_timer 12.1
<br/>  
<a href="#module_uart"><b>uart</b>
</a> altera_avalon_uart 12.1</span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
<div class="label">Memory Map</div>
<table class="mmap">
<tr>
<td class="empty" rowspan="2"></td>
<td class="mastermodule" colspan="2">
<a href="#module_cpu"><b>cpu</b>
</a>
</td>
</tr>
<tr>
<td class="masterl"> data_master</td>
<td class="masterr"> instruction_master</td>
</tr>
<tr>
<td class="slavemodule"> 
<a href="#module_cpu"><b>cpu</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">jtag_debug_module </td>
<td class="addr"><span style="color:#989898">0x</span>08000800</td>
<td class="addr"><span style="color:#989898">0x</span>08000800</td>
</tr>
<tr>
<td class="slavemodule"> 
<a href="#module_ram_mmu"><b>ram_mmu</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slavem">s1 </td>
<td class="addr"><span style="color:#989898">0x</span>08001000</td>
<td class="empty"></td>
</tr>
<tr>
<td class="slavem">s2 </td>
<td class="empty"></td>
<td class="addr"><span style="color:#989898">0x</span>08001000</td>
</tr>
<tr>
<td class="slavemodule"> 
<a href="#module_sdram"><b>sdram</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">s1 </td>
<td class="addr"><span style="color:#989898">0x</span>00000000</td>
<td class="addr"><span style="color:#989898">0x</span>00000000</td>
</tr>
<tr>
<td class="slavemodule"> 
<a href="#module_jtag"><b>jtag</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">avalon_jtag_slave </td>
<td class="addr"><span style="color:#989898">0x</span>08001440</td>
<td class="empty"></td>
</tr>
<tr>
<td class="slavemodule"> 
<a href="#module_timer"><b>timer</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">s1 </td>
<td class="addr"><span style="color:#989898">0x</span>08001420</td>
<td class="empty"></td>
</tr>
<tr>
<td class="slavemodule"> 
<a href="#module_uart"><b>uart</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">s1 </td>
<td class="addr"><span style="color:#989898">0x</span>08001400</td>
<td class="empty"></td>
</tr>
</table>
<a name="module_clk_50"> </a>
<div>
<hr/>
<h2>clk_50</h2>clock_source v12.1
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">clockFrequency</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">clockFrequencyKnown</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">inputClockFrequency</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">resetSynchronousEdges</td>
<td class="parametervalue">NONE</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>  
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<a name="module_cpu"> </a>
<div>
<hr/>
<h2>cpu</h2>altera_nios2_qsys v12.1
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="4">
<a href="#module_clk_50">clk_50</a>
</td>
<td class="from">clk  </td>
<td class="main" rowspan="40">cpu</td>
</tr>
<tr>
<td class="to">  clk</td>
</tr>
<tr>
<td class="from">clk_reset  </td>
</tr>
<tr>
<td class="to">  reset_n</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master  </td>
<td class="neighbor" rowspan="8">
<a href="#module_ram_mmu">ram_mmu</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  s1</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">instruction_master  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  s2</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">jtag_debug_module_reset  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  reset1</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">jtag_debug_module_reset  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  reset2</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master  </td>
<td class="neighbor" rowspan="6">
<a href="#module_sdram">sdram</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  s1</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">jtag_debug_module_reset  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  reset</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">instruction_master  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  s1</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master  </td>
<td class="neighbor" rowspan="6">
<a href="#module_jtag">jtag</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  avalon_jtag_slave</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">d_irq  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  irq</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">jtag_debug_module_reset  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  reset</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">d_irq  </td>
<td class="neighbor" rowspan="6">
<a href="#module_timer">timer</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  irq</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  s1</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">jtag_debug_module_reset  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  reset</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master  </td>
<td class="neighbor" rowspan="6">
<a href="#module_uart">uart</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  s1</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">d_irq  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  irq</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">jtag_debug_module_reset  </td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">  reset</td>
</tr>
</table>
</div>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">setting_showUnpublishedSettings</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_showInternalSettings</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_preciseSlaveAccessErrorException</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_preciseIllegalMemAccessException</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_preciseDivisionErrorException</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_performanceCounter</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_illegalMemAccessDetection</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_illegalInstructionsTrap</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_fullWaveformSignals</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_extraExceptionInfo</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_exportPCB</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_debugSimGen</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_clearXBitsLDNonBypass</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_bit31BypassDCache</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_bigEndian</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_export_large_RAMs</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_asic_enabled</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_asic_synopsys_translate_on_off</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_oci_export_jtag_signals</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_bhtIndexPcOnly</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_avalonDebugPortPresent</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_alwaysEncrypt</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_allowFullAddressRange</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_activateTrace</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_activateTestEndChecker</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_activateMonitors</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_activateModelChecker</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_HDLSimCachesCleared</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_HBreakTest</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">muldiv_divider</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">mpu_useLimit</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">mpu_enabled</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">mmu_enabled</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">mmu_autoAssignTlbPtrSz</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">manuallyAssignCpuID</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">debug_triggerArming</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">debug_embeddedPLL</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">debug_debugReqSignals</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">debug_assignJtagInstanceID</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">dcache_omitDataMaster</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">cpuReset</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">is_hardcopy_compatible</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_shadowRegisterSets</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">mpu_numOfInstRegion</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">mpu_numOfDataRegion</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">mmu_TLBMissExcOffset</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">debug_jtagInstanceID</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">resetOffset</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">exceptionOffset</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">cpuID</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">cpuID_stored</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">breakOffset</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">userDefinedSettings</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">resetSlave</td>
<td class="parametervalue">sdram.s1</td>
</tr>
<tr>
<td class="parametername">mmu_TLBMissExcSlave</td>
<td class="parametervalue">ram_mmu.s2</td>
</tr>
<tr>
<td class="parametername">exceptionSlave</td>
<td class="parametervalue">sdram.s1</td>
</tr>
<tr>
<td class="parametername">breakSlave</td>
<td class="parametervalue">cpu.jtag_debug_module</td>
</tr>
<tr>
<td class="parametername">setting_perfCounterWidth</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">setting_interruptControllerType</td>
<td class="parametervalue">Internal</td>
</tr>
<tr>
<td class="parametername">setting_branchPredictionType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">setting_bhtPtrSz</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">muldiv_multiplierType</td>
<td class="parametervalue">EmbeddedMulFast</td>
</tr>
<tr>
<td class="parametername">mpu_minInstRegionSize</td>
<td class="parametervalue">12</td>
</tr>
<tr>
<td class="parametername">mpu_minDataRegionSize</td>
<td class="parametervalue">12</td>
</tr>
<tr>
<td class="parametername">mmu_uitlbNumEntries</td>
<td class="parametervalue">4</td>
</tr>
<tr>
<td class="parametername">mmu_udtlbNumEntries</td>
<td class="parametervalue">6</td>
</tr>
<tr>
<td class="parametername">mmu_tlbPtrSz</td>
<td class="parametervalue">7</td>
</tr>
<tr>
<td class="parametername">mmu_tlbNumWays</td>
<td class="parametervalue">16</td>
</tr>
<tr>
<td class="parametername">mmu_processIDNumBits</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">impl</td>
<td class="parametervalue">Fast</td>
</tr>
<tr>
<td class="parametername">icache_size</td>
<td class="parametervalue">4096</td>
</tr>
<tr>
<td class="parametername">icache_ramBlockType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">icache_numTCIM</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">icache_burstType</td>
<td class="parametervalue">None</td>
</tr>
<tr>
<td class="parametername">dcache_bursts</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">debug_level</td>
<td class="parametervalue">Level1</td>
</tr>
<tr>
<td class="parametername">debug_OCIOnchipTrace</td>
<td class="parametervalue">_128</td>
</tr>
<tr>
<td class="parametername">dcache_size</td>
<td class="parametervalue">2048</td>
</tr>
<tr>
<td class="parametername">dcache_ramBlockType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">dcache_numTCDM</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">dcache_lineSize</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">resetAbsoluteAddr</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">exceptionAbsoluteAddr</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">breakAbsoluteAddr</td>
<td class="parametervalue">134219808</td>
</tr>
<tr>
<td class="parametername">mmu_TLBMissExcAbsAddr</td>
<td class="parametervalue">134221824</td>
</tr>
<tr>
<td class="parametername">translate_on</td>
<td class="parametervalue"> "synthesis translate_on" </td>
</tr>
<tr>
<td class="parametername">translate_off</td>
<td class="parametervalue"> "synthesis translate_off" </td>
</tr>
<tr>
<td class="parametername">instAddrWidth</td>
<td class="parametervalue">28</td>
</tr>
<tr>
<td class="parametername">dataAddrWidth</td>
<td class="parametervalue">28</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster1AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster2AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster3AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster0AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster1AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster2AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster3AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">instSlaveMapParam</td>
<td class="parametervalue"><address-map><slave name='sdram.s1' start='0x0' end='0x8000000' /><slave name='cpu.jtag_debug_module' start='0x8000800' end='0x8001000' /><slave name='ram_mmu.s2' start='0x8001000' end='0x8001400' /></address-map></td>
</tr>
<tr>
<td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue"><address-map><slave name='sdram.s1' start='0x0' end='0x8000000' /><slave name='cpu.jtag_debug_module' start='0x8000800' end='0x8001000' /><slave name='ram_mmu.s1' start='0x8001000' end='0x8001400' /><slave name='uart.s1' start='0x8001400' end='0x8001420' /><slave name='timer.s1' start='0x8001420' end='0x8001440' /><slave name='jtag.avalon_jtag_slave' start='0x8001440' end='0x8001448' /></address-map></td>
</tr>
<tr>
<td class="parametername">clockFrequency</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">deviceFamilyName</td>
<td class="parametervalue">CYCLONEIVE</td>
</tr>
<tr>
<td class="parametername">internalIrqMaskSystemInfo</td>
<td class="parametervalue">7</td>
</tr>
<tr>
<td class="parametername">customInstSlavesSystemInfo</td>
<td class="parametervalue"><info/></td>
</tr>
<tr>
<td class="parametername">deviceFeaturesSystemInfo</td>
<td class="parametervalue">NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster1MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster2MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster3MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster0MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster1MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster2MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster3MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>  
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>
<table>
<tr>
<td class="parametername">BIG_ENDIAN</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">BREAK_ADDR</td>
<td class="parametervalue">0xc8000820</td>
</tr>
<tr>
<td class="parametername">CPU_FREQ</td>
<td class="parametervalue">50000000u</td>
</tr>
<tr>
<td class="parametername">CPU_ID_SIZE</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">CPU_ID_VALUE</td>
<td class="parametervalue">0x00000000</td>
</tr>
<tr>
<td class="parametername">CPU_IMPLEMENTATION</td>
<td class="parametervalue">"fast"</td>
</tr>
<tr>
<td class="parametername">DATA_ADDR_WIDTH</td>
<td class="parametervalue">28</td>
</tr>
<tr>
<td class="parametername">DCACHE_LINE_SIZE</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">DCACHE_LINE_SIZE_LOG2</td>
<td class="parametervalue">5</td>
</tr>
<tr>
<td class="parametername">DCACHE_SIZE</td>
<td class="parametervalue">2048</td>
</tr>
<tr>