Research RVV Load and Store and its implementation in NRV <-> Vaquita

[shahzaibk23]

To Research about the Load Store RVV Instructions using the RVV Spec v1.0 and Other Sources. Post all the understandings and discussion here to keep track of things happening.

[Myrausman]

VECTOR STORE INSTRUCTIONS

For store instructions there are 3 types of operations based on addressing modes (mop) :

1. Unit Stride has further 3 types of instructions based on sumop
   a. Unitstride store:
   b. Unit-stride whole register store:
   c. Unit stride , mask store:
2. Strided
3. Indexed unordered
4. Indexed ordered

Unit-Stride Instructions:

In unit-stride instructions, elements are written contiguously in memory starting from the base effective address.
Example: Suppose rs1 contains the value 0x100, and you want to perform a unit-stride store operation to store a vector of integers into memory. The vector elements will be stored in memory addresses 0x100, 0x101, 0x102, and so on.

Vector unit stride difference:

1. Unitstride store: Unit stride store operations involve storing data in memory with a specified element width (eew), which can be 8, 16, 32, or 64 bits. The effective lmul (emul) determines how many registers are grouped together for this operation. Additionally, the operation can be performed with vector masking (vm), allowing elements to be either enabled or disabled.

2. Unit-stride whole register store: masked disabled unit stride store where eew= 8 .

3. Unit stride , mask store:masked enable unit stride store where eew = 8..

[Myrausman]

Vector strided:

Vector strided instructions are a type of vector load and store instructions that allow data to be loaded or stored from memory with a specified stride. The stride is specified as a byte offset between consecutive elements in memory .

The vector strided store instructions are named vsse and are available in 8-bit, 16-bit, 32-bit, and 64-bit versions . The format of the instructions is similar to that of the vector unit-stride load and store instructions, but with an additional operand that specifies the byte stride

Assembly:

#vs3 store data, rs1 base address, rs2 byte stride
vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store
vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store
vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store
vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store