diff --git a/hw/azadi/ip/xbar/tl_main_pkg.sv b/hw/azadi/ip/xbar/tl_main_pkg.sv
new file mode 100644
index 00000000..1ffcf20f
--- /dev/null
+++ b/hw/azadi/ip/xbar/tl_main_pkg.sv
@@ -0,0 +1,46 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tl_main package generated by `tlgen.py` tool
+
+package tl_main_pkg;
+
+  localparam logic [31:0] ADDR_SPACE_ICCM       = 32'h 20000000;
+  localparam logic [31:0] ADDR_SPACE_DCCM       = 32'h 10000000;
+  localparam logic [31:0] ADDR_SPACE_TIMER0     = 32'h 40000000;
+  localparam logic [31:0] ADDR_SPACE_UART0      = 32'h 40060000;
+  localparam logic [31:0] ADDR_SPACE_SPI0       = 32'h 40080000;
+  localparam logic [31:0] ADDR_SPACE_PWM        = 32'h 400b0000; 
+  localparam logic [31:0] ADDR_SPACE_GPIO       = 32'h 400c0000;
+  localparam logic [31:0] ADDR_SPACE_PLIC       = 32'h 40050000;
+
+  localparam logic [31:0] ADDR_MASK_ICCM       = 32'h 0000ffff;
+  localparam logic [31:0] ADDR_MASK_DCCM       = 32'h 0000ffff;
+  localparam logic [31:0] ADDR_MASK_TIMER0     = 32'h 0000ffff;
+  localparam logic [31:0] ADDR_MASK_UART0      = 32'h 0000ffff;
+  localparam logic [31:0] ADDR_MASK_SPI0       = 32'h 0000ffff;
+  localparam logic [31:0] ADDR_MASK_PWM        = 32'h 0000ffff;
+  localparam logic [31:0] ADDR_MASK_GPIO       = 32'h 0000ffff;
+  localparam logic [31:0] ADDR_MASK_PLIC       = 32'h 0000ffff;
+
+  localparam int N_HOST   = 2;
+  localparam int N_DEVICE = 8;
+
+  typedef enum int {
+    TlIccm = 0,
+    TlDccm = 1,
+    TlTimer0 = 2,
+    TlUart0 = 3,
+    TlSpi0 = 4,
+    TlPwm = 5,
+    TlGpio = 6,
+    TlPlic = 7
+  } tl_device_e;
+
+  typedef enum int {
+    TlBrqif = 0,
+    TlBrqlsu = 1
+  } tl_host_e;
+
+endpackage
diff --git a/hw/azadi/ip/xbar/tl_xbar_main.sv b/hw/azadi/ip/xbar/tl_xbar_main.sv
new file mode 100644
index 00000000..8a7e95ad
--- /dev/null
+++ b/hw/azadi/ip/xbar/tl_xbar_main.sv
@@ -0,0 +1,118 @@
+
+// main XBAR 
+
+module tl_xbar_main (
+
+  input logic clk_i,
+  input logic rst_ni,
+
+
+  // Host interfaces
+  input  tlul_pkg::tl_h2d_t tl_brqif_i,
+  output tlul_pkg::tl_d2h_t tl_brqif_o,
+  input  tlul_pkg::tl_h2d_t tl_brqlsu_i,
+  output tlul_pkg::tl_d2h_t tl_brqlsu_o,
+
+  // Device interfaces
+  output tlul_pkg::tl_h2d_t tl_iccm_o,
+  input  tlul_pkg::tl_d2h_t tl_iccm_i,
+  output tlul_pkg::tl_h2d_t tl_dccm_o,
+  input  tlul_pkg::tl_d2h_t tl_dccm_i,
+  output tlul_pkg::tl_h2d_t tl_timer0_o,
+  input  tlul_pkg::tl_d2h_t tl_timer0_i,
+  output tlul_pkg::tl_h2d_t tl_uart_o,
+  input  tlul_pkg::tl_d2h_t tl_uart_i,
+  output tlul_pkg::tl_h2d_t tl_spi_o,
+  input  tlul_pkg::tl_d2h_t tl_spi_i,
+  output tlul_pkg::tl_h2d_t tl_pwm_o,
+  input  tlul_pkg::tl_d2h_t tl_pwm_i,
+  output tlul_pkg::tl_h2d_t tl_gpio_o,
+  input  tlul_pkg::tl_d2h_t tl_gpio_i,
+  output tlul_pkg::tl_h2d_t tl_plic_o,
+  input  tlul_pkg::tl_d2h_t tl_plic_i
+
+
+);
+
+  import tlul_pkg::*;
+  import tl_main_pkg::*;
+
+// host LSU
+  tlul_pkg::tl_h2d_t brqlsu_to_s1n;
+  tlul_pkg::tl_d2h_t s1n_to_brqlsu;
+  logic [2:0] device_sel;
+
+  tlul_pkg::tl_h2d_t  h_dv_o[7];
+  tlul_pkg::tl_d2h_t  h_dv_i[7];
+
+  assign brqlsu_to_s1n = tl_brqlsu_i;
+  assign tl_brqlsu_o   = s1n_to_brqlsu;
+// Dveice connections
+
+  assign tl_iccm_o  = tl_brqif_i;
+  assign tl_brqif_o = tl_iccm_i;
+
+  assign tl_dccm_o = h_dv_o[0];
+  assign h_dv_i[0] = tl_dccm_i;
+
+  assign tl_timer0_o = h_dv_o[1];
+  assign h_dv_i[1]   = tl_timer0_i;
+
+  assign tl_uart_o   = h_dv_o[2];
+  assign h_dv_i[2]   = tl_uart_i;
+
+  assign tl_spi_o    = h_dv_o[3];
+  assign h_dv_i[3]   = tl_spi_i;
+
+  assign tl_pwm_o    = h_dv_o[4];
+  assign h_dv_i[4]   = tl_pwm_i;
+
+  assign tl_gpio_o   = h_dv_o[5];
+  assign h_dv_i[5]   = tl_gpio_i;
+
+  assign tl_plic_o   = h_dv_o[6];
+  assign h_dv_i[6]   = tl_plic_i; 
+
+
+
+// host  socket
+  always_comb begin 
+     device_sel = 3'd7;
+    if ((brqlsu_to_s1n.a_address & ~(ADDR_MASK_DCCM)) == ADDR_SPACE_DCCM) begin
+     device_sel = 3'd0; 
+    end else if ((brqlsu_to_s1n.a_address & ~(ADDR_MASK_TIMER0))    == ADDR_SPACE_TIMER0) begin
+      device_sel = 3'd1;
+    end else if ((brqlsu_to_s1n.a_address & ~(ADDR_MASK_UART0))     == ADDR_SPACE_UART0) begin
+      device_sel = 3'd2;
+    end else if ((brqlsu_to_s1n.a_address & ~(ADDR_MASK_SPI0))      == ADDR_SPACE_SPI0) begin
+      device_sel = 3'd3;
+    end else if ((brqlsu_to_s1n.a_address & ~(ADDR_MASK_PWM))       == ADDR_SPACE_PWM) begin
+      device_sel = 3'd4;
+    end else if ((brqlsu_to_s1n.a_address & ~(ADDR_MASK_GPIO))      == ADDR_SPACE_GPIO) begin
+      device_sel = 3'd5;
+    end else if ((brqlsu_to_s1n.a_address & ~(ADDR_MASK_PLIC))      == ADDR_SPACE_PLIC) begin
+      device_sel = 3'd6;
+    end 
+  end
+
+// host 2 socket
+
+  tlul_socket_1n #(
+    .HReqDepth (4'h0),
+    .HRspDepth (4'h0),
+    .DReqDepth (36'h0),
+    .DRspDepth (36'h0),
+    .N         (7)
+  ) host_lsu (
+    .clk_i        (clk_i),
+    .rst_ni       (rst_ni),
+    .tl_h_i       (brqlsu_to_s1n),
+    .tl_h_o       (s1n_to_brqlsu),
+    .tl_d_o       (h_dv_o),
+    .tl_d_i       (h_dv_i),
+    .dev_select_i (device_sel)
+  );
+
+
+
+endmodule
diff --git a/hw/azadi/rtl/azadi_soc_top.sv b/hw/azadi/rtl/azadi_soc_top.sv
old mode 100755
new mode 100644
index 00917b40..0f816163
--- a/hw/azadi/rtl/azadi_soc_top.sv
+++ b/hw/azadi/rtl/azadi_soc_top.sv
@@ -1,59 +1,70 @@
-module azadi_soc_top #(
-  parameter logic [31:0] JTAG_ID = 32'h 0000_0001,
-  parameter logic DirectDmiTap = 1'b1
-)(
-  input logic clock,
-  input logic reset_ni,
-  input logic uart_rx_i,
-
-  input  logic [19:0] gpio_i,
-  output logic [19:0] gpio_o,
-  // output logic [19:0] gpio_oe
-
-  // jtag interface 
-  input  logic  jtag_tck_i,
-  input  logic  jtag_tms_i,
-  input  logic  jtag_trst_ni,
-  input  logic  jtag_tdi_i,
-  output logic  jtag_tdo_o,
+
+module azadi_soc_top (
+`ifdef USE_POWER_PINS
+   inout vccd1,
+   inout vssd1,
+`endif
+  input logic clk_i,
+  input logic rst_ni,
+  input wire prog,
+  //output system_rst_ni,
+ // output prog_rst_ni,
+  input  logic [15:0] clks_per_bit, 
+  input  logic [31:0] gpio_i,
+  output logic [31:0] gpio_o,
+  output logic [31:0] gpio_oe,
 
   // uart-periph interface
-  output logic  uart_tx,
-  input  logic  uart_rx,
-  
-  // i2c0-periph interface
-  input  logic i2c0_scl_in,
-  output logic i2c0_scl_out,
-  input  logic i2c0_sda_in, 
-  output logic i2c0_sda_out,
+  output logic       uart_tx,
+  input  logic       uart_rx,
 
   // PWM interface  
-
-  //pwm
-  output              pwm_o,
-  output              pwm_o_2,
-
-  // spi host
-  output          [`SPI_SS_NB-1:0] ss_o,        
-  output                           sclk_o,      
-  output                           sd_o,       
-  input                            sd_i
+  output logic       pwm_o,
+  output logic       pwm_o_2,
+  output logic       pwm1_oe,
+  output logic       pwm2_oe,
+
+  // SPI interface
+  output logic    [`SPI_SS_NB-1:0] ss_o,        
+  output logic                     sclk_o,      
+  output logic                     sd_o,
+  output logic                     sd_oe,       
+  input  logic                     sd_i
 );
 
-  logic RESET;
-  assign RESET = reset_ni;
-  
+  logic prog_rst_n;
   logic system_rst_ni;
-  
-  wire [19:0] gpio_in;
-  wire [19:0] gpio_out;
+  logic [31:0] gpio_in;
+  logic [31:0] gpio_out;
   
   assign gpio_in = gpio_i;
-  assign gpio_o = gpio_out;
+  assign gpio_o  = gpio_out; 
+
+  logic         instr_valid;
+  logic [11:0]  tlul_addr;
+  logic         req_i;
+  logic [31:0]  tlul_data;
+
+ // instruction sram interface 
+  logic        instr_csb;
+  logic [11:0] instr_addr;
+  logic [31:0] instr_wdata;
+  logic [3:0]  instr_wmask;
+  logic        instr_we;
+  logic [31:0] instr_rdata;
+  
+   // data sram interface
+  logic        data_csb;
+  logic [11:0] data_addr;
+  logic [31:0] data_wdata;
+  logic [3:0]  data_wmask;
+  logic        data_we;
+  logic [31:0] data_rdata;
+  
+  logic [31:0] iccm_ctrl_data;
+  logic        iccm_ctrl_we;
+  logic [11:0] iccm_ctrl_addr_o;
 
-  logic i2c0_scl_en; 
-  logic i2c0_sda_en;
-        
   tlul_pkg::tl_h2d_t ifu_to_xbar;
   tlul_pkg::tl_d2h_t xbar_to_ifu;
   tlul_pkg::tl_h2d_t xbar_to_iccm;
@@ -65,26 +76,14 @@ module azadi_soc_top #(
   tlul_pkg::tl_h2d_t xbar_to_dccm;
   tlul_pkg::tl_d2h_t dccm_to_xbar;
 
-  tlul_pkg::tl_h2d_t xbarm_to_xbarp;
-  tlul_pkg::tl_d2h_t xbarp_to_xbarm;
-
   tlul_pkg::tl_h2d_t xbarp_to_gpio;
   tlul_pkg::tl_d2h_t gpio_to_xbarp;
 
-  tlul_pkg::tl_h2d_t dm_to_xbar;
-  tlul_pkg::tl_d2h_t xbar_to_dm;
-
-  tlul_pkg::tl_h2d_t dbgrom_to_xbar;
-  tlul_pkg::tl_d2h_t xbar_to_dbgrom;
-
   tlul_pkg::tl_h2d_t plic_req;
   tlul_pkg::tl_d2h_t plic_resp;
 
-  tlul_pkg::tl_h2d_t xbarp_to_uart;
-  tlul_pkg::tl_d2h_t uart_to_xbarp;
- 
-  tlul_pkg::tl_h2d_t xbarp_to_i2c;
-  tlul_pkg::tl_d2h_t i2c_to_xbarp;  
+  tlul_pkg::tl_h2d_t xbar_to_uart;
+  tlul_pkg::tl_d2h_t uart_to_xbar;
 
   tlul_pkg::tl_h2d_t xbar_to_timer;
   tlul_pkg::tl_d2h_t timer_to_xbar;
@@ -96,138 +95,56 @@ module azadi_soc_top #(
   tlul_pkg::tl_d2h_t spi_to_xbar;
 
   // interrupt vector
-  logic [56:0] intr_vector;
+  logic [35:0] intr_vector;
 
   // Interrupt source list 
   logic [31:0] intr_gpio;
-
-  //uart interrupts
-  logic intr_uart0_tx_watermark;
-  logic intr_uart0_rx_watermark;
-  logic intr_uart0_tx_empty;
-  logic intr_uart0_rx_overflow;
-  logic intr_uart0_rx_frame_err;
-  logic intr_uart0_rx_break_err;
-  logic intr_uart0_rx_timeout;
-  logic intr_uart0_rx_parity_err;
-
-  // i2c interrupts
-  logic intr_fmt_watermark;
-  logic intr_rx_watermark;
-  logic intr_fmt_overflow;
-  logic intr_rx_overflow;
-  logic intr_nak;
-  logic intr_scl_interference;
-  logic intr_sda_interference;
-  logic intr_stretch_timeout;
-  logic intr_sda_unstable;
-  logic intr_trans_complete;
-  logic intr_tx_empty;
-  logic intr_tx_nonempty;
-  logic intr_tx_overflow;
-  logic intr_acq_overflow;
-  logic intr_ack_stop;
-  logic intr_host_timeout; 
-  logic intr_timer;
-  logic intr_srx;
-  logic intr_stx;
-
-  logic intr_req;
-
-  assign intr_vector = {  
-      // gpio
-      intr_gpio,
-      //spi
-
+  logic        intr_uart0_tx_watermark;
+  logic        intr_uart0_rx_watermark;
+  logic        intr_uart0_tx_empty;
+  logic        intr_uart0_rx_overflow;
+  logic        intr_uart0_rx_frame_err;
+  logic        intr_uart0_rx_break_err;
+  logic        intr_uart0_rx_timeout;
+  logic        intr_uart0_rx_parity_err;
+  logic        intr_req;
+  logic        intr_srx;
+  logic        intr_stx;
+  logic        intr_timer;
+  logic        intr_u_tx;
+
+  assign intr_vector = { 
       intr_srx,
       intr_stx,
-      // i2c0
-      intr_fmt_watermark,
-      intr_rx_watermark,
-      intr_fmt_overflow,
-      intr_rx_overflow,
-      intr_nak,
-      intr_scl_interference,
-      intr_sda_interference,
-      intr_stretch_timeout,
-      intr_sda_unstable,
-      intr_trans_complete,
-      intr_tx_empty,
-      intr_tx_nonempty,
-      intr_tx_overflow,
-      intr_acq_overflow,
-      intr_ack_stop,
-      intr_host_timeout,
-      
-      //uart0
-      intr_uart0_rx_parity_err,
-      intr_uart0_rx_timeout,
-      intr_uart0_rx_break_err,
-      intr_uart0_rx_frame_err,
-      intr_uart0_rx_overflow,
-      intr_uart0_tx_empty,
-      intr_uart0_rx_watermark,
-      intr_uart0_tx_watermark,
-      //intr_spi,
+      intr_u_tx,
+      intr_gpio,
       1'b0
   };
 
-  logic       rx_dv_i;
-  logic [7:0] rx_byte_i;
-
-
-  logic instr_valid;
-  logic [11:0] tlul_addr;
-  logic req_i;
-  logic [31:0] tlul_data;
-
-  logic iccm_cntrl_reset;
-  logic [11:0] iccm_cntrl_addr;
-  logic [31:0] iccm_cntrl_data;
-  logic iccm_cntrl_we;
-
-  // jtag interface 
-  jtag_pkg::jtag_req_t jtag_req;
-  jtag_pkg::jtag_rsp_t jtag_rsp;
-  logic unused_jtag_tdo_oe_o;
-
-  assign jtag_req.tck    = jtag_tck_i;
-  assign jtag_req.tms    = jtag_tms_i;
-  assign jtag_req.trst_n = jtag_trst_ni;
-  assign jtag_req.tdi    = jtag_tdi_i;
-  assign jtag_tdo_o      = jtag_rsp.tdo;
-  assign unused_jtag_tdo_oe_o = jtag_rsp.tdo_oe;
-
-  logic dbg_req;
-  logic dbg_rst;
-//wire 
-
-  //tlul_pkg::tl_h2d_t core_to_gpio;
-  //tlul_pkg::tl_d2h_t gpio_to_core;
 
 brq_core_top #(
     .PMPEnable        (1'b0),
     .PMPGranularity   (0), 
-    .PMPNumRegions    (0), 
+    .PMPNumRegions    (4), 
     .MHPMCounterNum   (0), 
     .MHPMCounterWidth (40), 
     .RV32E            (1'b0), 
     .RV32M            (brq_pkg::RV32MSlow), 
     .RV32B            (brq_pkg::RV32BNone), 
     .RegFile          (brq_pkg::RegFileFF), 
-    .BranchTargetALU  (1'b0), 
+    .BranchTargetALU  (1'b1), 
     .WritebackStage   (1'b1), 
     .ICache           (1'b0), 
     .ICacheECC        (1'b0), 
     .BranchPredictor  (1'b0), 
     .DbgTriggerEn     (1'b1), 
-    .DbgHwBreakNum    (2), 
+    .DbgHwBreakNum    (1), 
     .Securebrq        (1'b0),
-    .DmHaltAddr       (tl_main_pkg::ADDR_SPACE_DEBUG_ROM + 32'h 800), 
-    .DmExceptionAddr  (tl_main_pkg::ADDR_SPACE_DEBUG_ROM + dm::ExceptionAddress) 
+    .DmHaltAddr       ('0), 
+    .DmExceptionAddr  ('0) 
 ) u_top (
-    .clock (clock),
-    .reset (system_rst_ni),
+    .clk_i (clk_i),
+    .rst_ni (system_rst_ni),
 
   // instruction memory interface 
     .tl_i_i (xbar_to_ifu),
@@ -237,7 +154,7 @@ brq_core_top #(
     .tl_d_i (xbar_to_lsu),
     .tl_d_o (lsu_to_xbar),
 
-    .test_en_i   (1'b0),     // enable all clock gates for testing
+    //.test_en_i   (1'b0),     // enable all clk_i gates for testing
 
     .hart_id_i   (32'b0), 
     .boot_addr_i (32'h20000000),
@@ -246,12 +163,12 @@ brq_core_top #(
     .irq_software_i (1'b0),
     .irq_timer_i    (intr_timer),
     .irq_external_i (intr_req),
-    .irq_fast_i     (1'b0),
+    .irq_fast_i     ('0),
     .irq_nm_i       (1'b0),       // non-maskeable interrupt
 
     // Debug Interface
-    .debug_req_i    (dbg_req),
-        // CPU Control Signals
+    .debug_req_i    ('0),
+    // CPU Control Signals
     .fetch_enable_i (1'b1),
     .alert_minor_o  (),
     .alert_major_o  (),
@@ -259,331 +176,227 @@ brq_core_top #(
 );
 
 
-  // Debug module
-  rv_dm #(
-    .NrHarts(1),
-    .IdcodeValue(JTAG_ID),
-    .DirectDmiTap (DirectDmiTap)
-    ) debug_module (
-    .clk_i(clock),       // clock
-    .rst_ni(reset_ni),      // asynchronous reset active low, connect PoR
-                                            // here, not the system reset
-    .testmode_i(),
-    .ndmreset_o(dbg_rst),  // non-debug module reset
-    .dmactive_o(),  // debug module is active
-    .debug_req_o(dbg_req), // async debug request
-    .unavailable_i(1'b0), // communicate whether the hart is unavailable
-                                              // (e.g.: power down)
-
-    // bus device with debug memory, for an execution based technique
-    .tl_d_i(dbgrom_to_xbar),
-    .tl_d_o(xbar_to_dbgrom),
-
-    // bus host, for system bus accesses
-    .tl_h_o(dm_to_xbar),
-    .tl_h_i(xbar_to_dm),
-
-    .jtag_req_i(jtag_req),
-    .jtag_rsp_o(jtag_rsp)
-  );
-
-  // main xbar module
+// main xbar module
   tl_xbar_main main_swith (
-    .clk_main_i         (clock),
-    .rst_main_ni        (system_rst_ni),
-
-    // Host interfaces
-    .tl_brqif_i         (ifu_to_xbar),
-    .tl_brqif_o         (xbar_to_ifu),
-    .tl_brqlsu_i        (lsu_to_xbar),
-    .tl_brqlsu_o        (xbar_to_lsu),
-    .tl_dm_sba_i        (dm_to_xbar),
-    .tl_dm_sba_o        (xbar_to_dm),
-
-    // Device interfaces
-    .tl_iccm_o          (xbar_to_iccm),
-    .tl_iccm_i          (iccm_to_xbar),
-    .tl_debug_rom_o     (dbgrom_to_xbar),
-    .tl_debug_rom_i     (xbar_to_dbgrom),
-    .tl_dccm_o          (xbar_to_dccm),
-    .tl_dccm_i          (dccm_to_xbar),
-    .tl_flash_ctrl_o    (),
-    .tl_flash_ctrl_i    (),
-    .tl_timer0_o        (xbar_to_timer),
-    .tl_timer0_i        (timer_to_xbar),
-    .tl_timer1_o        (),
-    .tl_timer1_i        (),
-    .tl_timer2_o        (),
-    .tl_timer2_i        (),
-    .tl_timer3_o        (),
-    .tl_timer3_i        (),
-    .tl_timer4_o        (),
-    .tl_timer4_i        (),
-    .tl_plic_o          (plic_req),
-    .tl_plic_i          (plic_resp),
-    .tl_xbar_peri_o     (xbarm_to_xbarp),
-    .tl_xbar_peri_i     (xbarp_to_xbarm),
-
-    .scanmode_i         ()
-  );
-
-  // dummy data memory
-
-  data_mem dccm(
-    .clk_i    (clock),
-    .rst_ni   (system_rst_ni),
-
-    // tl-ul insterface
-    .tl_d_i   (xbar_to_dccm),
-    .tl_d_o   (dccm_to_xbar)
-  );
-
-  rv_timer timer0(
-    .clk_i  (clock),
-    .rst_ni (system_rst_ni),
+  .clk_i         (clk_i),
+  .rst_ni        (system_rst_ni),
+
+  // Host interfaces
+  .tl_brqif_i         (ifu_to_xbar),
+  .tl_brqif_o         (xbar_to_ifu),
+  .tl_brqlsu_i        (lsu_to_xbar),
+  .tl_brqlsu_o        (xbar_to_lsu),
+
+  // Device interfaces
+  .tl_iccm_o          (xbar_to_iccm),
+  .tl_iccm_i          (iccm_to_xbar),
+  .tl_dccm_o          (xbar_to_dccm),
+  .tl_dccm_i          (dccm_to_xbar),
+  .tl_timer0_o        (xbar_to_timer),
+  .tl_timer0_i        (timer_to_xbar),
+  .tl_uart_o          (xbar_to_uart),
+  .tl_uart_i          (uart_to_xbar),
+  .tl_spi_o           (xbar_to_spi),
+  .tl_spi_i           (spi_to_xbar),
+  .tl_pwm_o           (xbar_to_pwm),
+  .tl_pwm_i           (pwm_to_xbar),
+  .tl_gpio_o          (xbarp_to_gpio),
+  .tl_gpio_i          (gpio_to_xbarp),
+  .tl_plic_o          (plic_req),
+  .tl_plic_i          (plic_resp)
+);
+
+
+// timer
+rv_timer timer0( 
+  .clk_i  (clk_i),
+  .rst_ni (system_rst_ni),
+
+  .tl_i   (xbar_to_timer),
+  .tl_o   (timer_to_xbar),
+
+  .intr_timer_expired_0_0_o (intr_timer)
+);
+
+// PWM module
+pwm_top u_pwm(
+
+  .clk_i   (clk_i),
+  .rst_ni  (system_rst_ni),
+  .tl_i    (xbar_to_pwm),
+  .tl_o    (pwm_to_xbar),
+  .pwm_o   (pwm_o),
+  .pwm_o_2 (pwm_o_2),
+  .pwm1_oe (pwm1_oe),
+  .pwm2_oe (pwm2_oe)
+);
 
-    .tl_i   (xbar_to_timer),
-    .tl_o   (timer_to_xbar),
-
-    .intr_timer_expired_0_0_o (intr_timer)
-  );
-
-
-  //peripheral xbar
-
-  xbar_periph periph_switch (
-    .clk_peri_i         (clock),
-    .rst_peri_ni        (system_rst_ni),
-
-    // Host interfaces
-    .tl_xbar_main_i     (xbarm_to_xbarp),
-    .tl_xbar_main_o     (xbarp_to_xbarm),
-
-    // Device interfaces
-    .tl_uart0_o         (xbarp_to_uart),
-    .tl_uart0_i         (uart_to_xbarp),
-    .tl_uart1_o         (),
-    .tl_uart1_i         (),
-    .tl_spi0_o          (xbar_to_spi),
-    .tl_spi0_i          (spi_to_xbar),
-    .tl_spi1_o          (),
-    .tl_spi1_i          (),
-    .tl_spi2_o          (),
-    .tl_spi2_i          (),
-    .tl_pwm_o           (xbar_to_pwm),
-    .tl_pwm_i           (pwm_to_xbar),
-    .tl_gpio_o          (xbarp_to_gpio),
-    .tl_gpio_i          (gpio_to_xbarp),
-    .tl_i2c0_o          (xbarp_to_i2c ),
-    .tl_i2c0_i          (i2c_to_xbarp ),
-    .tl_i2c1_o          (),
-    .tl_i2c1_i          (),
-    .tl_can0_o          (),
-    .tl_can0_i          (),
-    .tl_can1_o          (),
-    .tl_can1_i          (),
-    .tl_adc_o           (),
-    .tl_adc_i           (),
-    .tl_qspi_o          (),
-    .tl_qspi_i          (),
-
-    .scanmode_i         ()
-  );
-
-  //GPIO module
-  gpio GPIO (
-    .clk_i          (clock),
-    .rst_ni         (system_rst_ni),
-
-    // Below Regster interface can be changed
-    .tl_i           (xbarp_to_gpio),
-    .tl_o           (gpio_to_xbarp),
-
-    .cio_gpio_i     ({12'b0,gpio_in}),
-    .cio_gpio_o     (gpio_out),
-    .cio_gpio_en_o  (),
-
-    .intr_gpio_o    (intr_gpio )  
-  );
-
-  spi_top u_spi_host(
-
-  .clk_i       (clock),
+// spi module 
+spi_top u_spi_host(
+
+  .clk_i       (clk_i),
   .rst_ni      (system_rst_ni),
 
   .tl_i        (xbar_to_spi),
   .tl_o        (spi_to_xbar),
-
   // SPI signals                  
   .intr_rx_o   (intr_srx),
-  .intr_tx_o   (intr_stx),                    
+  .intr_tx_o   (intr_stx),                   
   .ss_o        (ss_o),         
   .sclk_o      (sclk_o),       
-  .sd_o        (sd_o),       
+  .sd_o        (sd_o),
+  .sd_oe       (sd_oe),       
   .sd_i        (sd_i)
 );
 
-  pwm_top u_pwm(
-
-    .clk_i   (clock),
-    .rst_ni  (system_rst_ni),
-
-    .tl_i    (xbar_to_pwm),
-    .tl_o    (pwm_to_xbar),
-
-
-    .pwm_o   (pwm_o),
-    .pwm_o_2 (pwm_o_2)
-  );
-
-  iccm_controller u_dut(
-  	.clk_i       (clock),
-  	.rst_ni      (RESET),
-  	.rx_dv_i     (rx_dv_i),
-  	.rx_byte_i   (rx_byte_i),
-  	.we_o        (iccm_cntrl_we),
-  	.addr_o      (iccm_cntrl_addr),
-  	.wdata_o     (iccm_cntrl_data),
-  	.reset_o     (iccm_cntrl_reset)
-  );
-
-  uart_receiver programmer (
-   .i_Clock       (clock),
-   .rst_ni        (RESET),
-   .i_Rx_Serial   (uart_rx_i),
-   .CLKS_PER_BIT  (15'd87),
-   .o_Rx_DV       (rx_dv_i),
-   .o_Rx_Byte     (rx_byte_i)
-  );
-
-  // logic [31:0] instr_wdata;
-  // logic        instr_we;
-  // logic [3:0]  instr_be;
-// 
-// import tlul_pkg::*;
-  // assign instr_wdata = dm_to_xbar.a_data;
-  // assign instr_be    = dm_to_xbar.a_mask;
-  // assign instr_we    = dm_to_xbar.a_valid & logic'(dm_to_xbar.a_opcode inside {PutFullData, PutPartialData});
-
-  instr_mem_top iccm (
-    .clk_i      (clock),
-    .rst_ni     (system_rst_ni),
-
-    .req        (req_i),
-    .addr       (tlul_addr),
-    .wdata      (),
-    .rdata      (tlul_data),
-    .rvalid     (instr_valid),
-    .we         ('0)
-  );
-
-  tlul_sram_adapter #(
-    .SramAw       (12),
-    .SramDw       (32), 
-    .Outstanding  (2),  
-    .ByteAccess   (1),
-    .ErrOnWrite   (0),  // 1: Writes not allowed, automatically error
-    .ErrOnRead    (0)   // 1: Reads not allowed, automatically error  
-
-  ) inst_mem (
-      .clk_i     (clock),
-      .rst_ni    (system_rst_ni),
-      .tl_i      (xbar_to_iccm),
-      .tl_o      (iccm_to_xbar), 
-      .req_o     (req_i),
-      .gnt_i     (1'b1),
-      .we_o      (),
-      .addr_o    (tlul_addr),
-      .wdata_o   (),
-      .wmask_o   (),
-      .rdata_i   ((reset_ni) ? tlul_data: '0),
-      .rvalid_i  (instr_valid),
-      .rerror_i  (2'b0)
-  );
-
-  rstmgr reset_manager(
-    .clk_i(clock),
-    .rst_ni(reset_ni),
-    .ndmreset (dbg_rst),
-    .sys_rst_ni(system_rst_ni)
-  );
-
-
-  rv_plic intr_controller (
-    .clk_i(clock),
-    .rst_ni(system_rst_ni),
-
-    // Bus Interface (device)
-    .tl_i (plic_req),
-    .tl_o (plic_resp),
-
-    // Interrupt Sources
-    .intr_src_i (intr_vector),
-
-    // Interrupt notification to targets
-    .irq_o (intr_req),
-    .irq_id_o(),
-
-    .msip_o()
-  );
-
-  uart u_uart0(
-    .clk_i                   (clock        ),
-    .rst_ni                  (system_rst_ni),
-
-    // Bus Interface
-    .tl_i                    (xbarp_to_uart),
-    .tl_o                    (uart_to_xbarp),
-
-    // Generic IO
-    .cio_rx_i                (uart_rx),
-    .cio_tx_o                (uart_tx),
-    .cio_tx_en_o             (),
-
-    // Interrupts
-    .intr_tx_watermark_o     (intr_uart0_tx_watermark ),
-    .intr_rx_watermark_o     (intr_uart0_rx_watermark ),
-    .intr_tx_empty_o         (intr_uart0_tx_empty     ),
-    .intr_rx_overflow_o      (intr_uart0_rx_overflow  ),
-    .intr_rx_frame_err_o     (intr_uart0_rx_frame_err ),
-    .intr_rx_break_err_o     (intr_uart0_rx_break_err ),
-    .intr_rx_timeout_o       (intr_uart0_rx_timeout   ),
-    .intr_rx_parity_err_o    (intr_uart0_rx_parity_err) 
-  );
-
-  i2c i2c0(
-    .clk_i  (clock),
+
+//GPIO module
+gpio GPIO (
+  .clk_i          (clk_i),
+  .rst_ni         (system_rst_ni),
+
+  // Below Regster interface can be changed
+  .tl_i           (xbarp_to_gpio),
+  .tl_o           (gpio_to_xbarp),
+  .cio_gpio_i     (gpio_in),
+  .cio_gpio_o     (gpio_out),
+  .cio_gpio_en_o  (gpio_oe),
+
+  .intr_gpio_o    (intr_gpio )  
+);
+
+
+rstmgr reset_manager(
+  .clk_i  (clk_i),
+  .rst_ni (rst_ni),
+  //.prog_i (prog),
+  .prog_rst_ni(prog_rst_ni),
+  .sys_rst_ni(system_rst_ni)
+);
+
+rv_plic intr_controller (
+  .clk_i(clk_i),
+  .rst_ni(system_rst_ni),
+  // Bus Interface (device)
+  .tl_i (plic_req),
+  .tl_o (plic_resp),
+  // Interrupt Sources
+  .intr_src_i (intr_vector),
+  // Interrupt notification to targets
+  .irq_o (intr_req),
+  .msip_o()
+);
+
+ uart_top  u_uart(
+
+    .clk_i  (clk_i),
     .rst_ni (system_rst_ni),
+    .tl_i   (xbar_to_uart),
+    .tl_o   (uart_to_xbar),
+    .tx_o   (uart_tx),
+    .rx_i   (uart_rx),
+    
+    .intr_tx (intr_u_tx)
+);
+
+logic rx_dv_i;
+logic [7:0] rx_byte_i;
+	
+iccm_controller u_dut(
+    .clk_i      (clk_i),
+	.rst_ni     (rst_ni),
+	.prog_i     (prog),
+	.rx_dv_i    (rx_dv_i),
+	.rx_byte_i  (rx_byte_i),
+	.we_o       (iccm_ctrl_we),
+	.addr_o     (iccm_ctrl_addr_o),
+	.wdata_o    (iccm_ctrl_data),
+	.reset_o    (prog_rst_ni)
+);
+	
+uart_rx_prog u_uart_rx_prog(
+	.clk_i         (clk_i),
+	.rst_ni        (rst_ni),
+	.i_Rx_Serial   (uart_rx),
+	.CLKS_PER_BIT  (clks_per_bit),
+	.o_Rx_DV       (rx_dv_i),
+	.o_Rx_Byte     (rx_byte_i)
+);
+
+
+// dummy instruction memory
+instr_mem_top iccm_adapter(
+  .clk_i            (clk_i),
+  .rst_ni           (system_rst_ni),
+  
+  .tl_i             (xbar_to_iccm),
+  .tl_o             (iccm_to_xbar),
+// iccm controller interface 
+  .iccm_ctrl_addr   (iccm_ctrl_addr_o),
+  .iccm_ctrl_wdata  (iccm_ctrl_data),
+  .iccm_ctrl_we     (iccm_ctrl_we),
+  .prog_rst_ni      (prog_rst_ni),
+  
+// instruction sram interface 
+  .csb              (instr_csb),
+  .addr_o           (instr_addr),
+  .wdata_o          (instr_wdata),
+  .wmask_o          (instr_wmask),
+  .we_o             (instr_we),
+  .rdata_i          (instr_rdata)
+);
+
+
 
-    // Bus Interface
-    .tl_i (xbarp_to_i2c),
-    .tl_o (i2c_to_xbarp),
-
-    // Generic IO
-    .cio_scl_i     (i2c0_scl_in  ), 
-    .cio_scl_o     (i2c0_scl_out ),
-    .cio_scl_en_o  (i2c0_scl_en  ), 
-    .cio_sda_i     (i2c0_sda_in  ), 
-    .cio_sda_o     (i2c0_sda_out ),
-    .cio_sda_en_o  (i2c0_sda_en  ),
-
-    // Interrupts
-    .intr_fmt_watermark_o    (intr_fmt_watermark   ),
-    .intr_rx_watermark_o     (intr_rx_watermark    ),
-    .intr_fmt_overflow_o     (intr_fmt_overflow    ),
-    .intr_rx_overflow_o      (intr_rx_overflow     ),
-    .intr_nak_o              (intr_nak             ),
-    .intr_scl_interference_o (intr_scl_interference),
-    .intr_sda_interference_o (intr_sda_interference),
-    .intr_stretch_timeout_o  (intr_stretch_timeout ),
-    .intr_sda_unstable_o     (intr_sda_unstable    ),
-    .intr_trans_complete_o   (intr_trans_complete  ),
-    .intr_tx_empty_o         (intr_tx_empty        ),
-    .intr_tx_nonempty_o      (intr_tx_nonempty     ),
-    .intr_tx_overflow_o      (intr_tx_overflow     ),
-    .intr_acq_overflow_o     (intr_acq_overflow    ),
-    .intr_ack_stop_o         (intr_ack_stop        ),
-    .intr_host_timeout_o     (intr_host_timeout    )
-  );
+DFFRAM #(
+  .USE_LATCH(0),
+  .WSIZE(4)
+) u_iccm(
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),
+  .vssd1(vssd1),
+`endif
+  .CLK(clk_i),
+  .WE (instr_we? instr_wmask: '0),
+  .EN(instr_csb),
+  .Di(instr_wdata),
+  .Do(instr_rdata),
+  .A(instr_addr[9:0])
+);
+
+
+// dummy data memory
+data_mem_top dccm_adapter(
+  .clk_i    (clk_i),
+  .rst_ni    (system_rst_ni),
+
+// tl-ul insterface
+  .tl_d_i   (xbar_to_dccm),
+  .tl_d_o   (dccm_to_xbar),
+  
+  // sram interface
+   .csb     (data_csb),
+   .addr_o  (data_addr),
+   .wdata_o (data_wdata),
+   .wmask_o (data_wmask),
+   .we_o    (data_we),
+   .rdata_i (data_rdata)
+);
 
+
+DFFRAM #(
+  .USE_LATCH(0),
+  .WSIZE(4)
+) u_dccm(
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),
+  .vssd1(vssd1),
+`endif
+  .CLK (clk_i),
+  .WE  (data_we? data_wmask: '0),
+  .EN  (data_csb),
+  .Di  (data_wdata),
+  .Do  (data_rdata),
+  .A   (data_addr[9:0])
+);
 endmodule
diff --git a/hw/azadi/rtl/rstmgr.sv b/hw/azadi/rtl/rstmgr.sv
old mode 100755
new mode 100644
index 6a66f09b..47379db8
--- a/hw/azadi/rtl/rstmgr.sv
+++ b/hw/azadi/rtl/rstmgr.sv
@@ -5,38 +5,44 @@ module rstmgr(
 
     input clk_i, //system clock
     input rst_ni, // system reset
-
-    input logic iccm_rst_i,
-    input  logic  ndmreset, // non-debug module reset
+    input prog_rst_ni,
+   // input wire prog_i,
     output logic  sys_rst_ni // reset for system except debug module
 );
 
   logic rst_d, rst_q;
   logic rst_fd, rst_fq; // follower flip flop
+  //logic prog_reg;
   
   always_comb begin
     if(!rst_ni) begin
       rst_d = 1'b0;
-    end else 
-    if (!iccm_rst_i) begin
-      rst_d = 1'b0;
-    end else
-    if(ndmreset) begin
-      rst_d = 1'b0;
     end else begin
-      rst_d = 1'b1;
+      if(!prog_rst_ni) begin
+        rst_d = 1'b0;
+      end else begin
+        rst_d = 1'b1;
+      end 
     end
   end
-  
-  always_ff @(posedge clk_i ) begin
-    rst_q <= rst_d;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+	  if(!rst_ni) begin
+	    rst_q <= 1'b0;
+	  end else begin
+	    rst_q <= rst_d;
+	  end 
   end
 
   assign rst_fd = rst_q;
-  always_ff @(posedge clk_i ) begin
-    rst_fq <= rst_fd;
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if(!rst_ni) begin
+	    rst_fq <= 1'b0;
+	  end else begin
+	    rst_fq <= rst_fd;
+  	end
   end
 
   assign sys_rst_ni = rst_fq;
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/hw/azadi/rtl/uart_receiver.v b/hw/azadi/rtl/uart_receiver.v
deleted file mode 100755
index b313ba79..00000000
--- a/hw/azadi/rtl/uart_receiver.v
+++ /dev/null
@@ -1,174 +0,0 @@
-
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 01/20/2021 12:32:12 PM
-// Design Name: 
-// Module Name: uart_rx
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//////////////////////////////////////////////////////////////////////////////////
-
-//////////////////////////////////////////////////////////////////////
-// This file contains the UART Receiver.  This receiver is able to
-// receive 8 bits of serial data, one start bit, one stop bit,
-// and no parity bit.  When receive is complete o_rx_dv will be
-// driven high for one clock cycle.
-// 
-// Set Parameter CLKS_PER_BIT as follows:
-// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
-// Example: 10 MHz Clock, 115200 baud UART
-// (10000000)/(115200) = 87
-   
-module uart_receiver (
- input         i_Clock,
- input         rst_ni,
- input         i_Rx_Serial,
- input  [15:0] CLKS_PER_BIT,
- output        o_Rx_DV,
- output  [7:0] o_Rx_Byte
- );
-  
-parameter s_IDLE         = 3'b000;
-parameter s_RX_START_BIT = 3'b001;
-parameter s_RX_DATA_BITS = 3'b010;
-parameter s_RX_STOP_BIT  = 3'b011;
-parameter s_CLEANUP      = 3'b100;
- 
-reg           r_Rx_Data_R = 1'b1;
-reg           r_Rx_Data   = 1'b1;
- 
-reg [15:0]     r_Clock_Count = 0;
-reg [2:0]     r_Bit_Index   = 0; //8 bits total
-reg [7:0]     r_Rx_Byte     = 0;
-reg           r_Rx_DV       = 0;
-reg [2:0]     r_SM_Main     = 0;
- 
-// Purpose: Double-register the incoming data.
-// This allows it to be used in the UART RX Clock Domain.
-// (It removes problems caused by metastability)
-always @(posedge i_Clock)
-  begin
-    r_Rx_Data_R <= i_Rx_Serial;
-    r_Rx_Data   <= r_Rx_Data_R;
-  end
- 
- 
-// Purpose: Control RX state machine
-always @(posedge i_Clock or negedge rst_ni)
-  begin
-    if (!rst_ni) begin
-      r_SM_Main <= s_IDLE;
-      r_Rx_DV       <= 1'b0;
-      r_Clock_Count <= 0;
-      r_Bit_Index   <= 0;
-    end else begin       
-    case (r_SM_Main)
-      s_IDLE :
-        begin
-          r_Rx_DV       <= 1'b0;
-          r_Clock_Count <= 0;
-          r_Bit_Index   <= 0;
-           
-          if (r_Rx_Data == 1'b0)          // Start bit detected
-            r_SM_Main <= s_RX_START_BIT;
-          else
-            r_SM_Main <= s_IDLE;
-        end
-       
-      // Check middle of start bit to make sure it's still low
-      s_RX_START_BIT :
-        begin
-          if (r_Clock_Count == ((CLKS_PER_BIT-1)>>1))
-            begin
-              if (r_Rx_Data == 1'b0)
-                begin
-                  r_Clock_Count <= 0;  // reset counter, found the middle
-                  r_SM_Main     <= s_RX_DATA_BITS;
-                end
-              else
-                r_SM_Main <= s_IDLE;
-            end
-          else
-            begin
-              r_Clock_Count <= r_Clock_Count + 1;
-              r_SM_Main     <= s_RX_START_BIT;
-            end
-        end // case: s_RX_START_BIT
-       
-       
-      // Wait CLKS_PER_BIT-1 clock cycles to sample serial data
-      s_RX_DATA_BITS :
-        begin
-          if (r_Clock_Count < CLKS_PER_BIT-1)
-            begin
-              r_Clock_Count <= r_Clock_Count + 1;
-              r_SM_Main     <= s_RX_DATA_BITS;
-            end
-          else
-            begin
-              r_Clock_Count          <= 0;
-              r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
-               
-              // Check if we have received all bits
-              if (r_Bit_Index < 7)
-                begin
-                  r_Bit_Index <= r_Bit_Index + 1;
-                  r_SM_Main   <= s_RX_DATA_BITS;
-                end
-              else
-                begin
-                  r_Bit_Index <= 0;
-                  r_SM_Main   <= s_RX_STOP_BIT;
-                end
-            end
-        end // case: s_RX_DATA_BITS
-   
-   
-      // Receive Stop bit.  Stop bit = 1
-      s_RX_STOP_BIT :
-        begin
-          // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
-          if (r_Clock_Count < CLKS_PER_BIT-1)
-            begin
-              r_Clock_Count <= r_Clock_Count + 1;
-              r_SM_Main     <= s_RX_STOP_BIT;
-            end
-          else
-            begin
-              r_Rx_DV       <= 1'b1;
-              r_Clock_Count <= 0;
-              r_SM_Main     <= s_CLEANUP;
-            end
-        end // case: s_RX_STOP_BIT
-   
-       
-      // Stay here 1 clock
-      s_CLEANUP :
-        begin
-          r_SM_Main <= s_IDLE;
-          r_Rx_DV   <= 1'b0;
-        end
-       
-       
-      default :
-        r_SM_Main <= s_IDLE;
-       
-    endcase
-    end
-  end   
- 
-assign o_Rx_DV   = r_Rx_DV;
-assign o_Rx_Byte = r_Rx_Byte;
- 
-endmodule // uart_rx
\ No newline at end of file
diff --git a/hw/azadi/rtl/uart_rx_prog.v b/hw/azadi/rtl/uart_rx_prog.v
new file mode 100644
index 00000000..36c4a4da
--- /dev/null
+++ b/hw/azadi/rtl/uart_rx_prog.v
@@ -0,0 +1,155 @@
+`timescale 1ns / 1ps
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Set Parameter CLKS_PER_BIT as follows:
+// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
+// Example: 10 MHz Clock, 115200 baud UART
+// (10000000)/(115200) = 87
+  
+module uart_rx_prog (
+   input  wire       clk_i,
+   input  wire       rst_ni,
+   input  wire       i_Rx_Serial,
+   input  wire [15:0] CLKS_PER_BIT,
+   output wire        o_Rx_DV,
+   output wire  [7:0] o_Rx_Byte
+   );
+    
+  parameter s_IDLE         = 3'b000;
+  parameter s_RX_START_BIT = 3'b001;
+  parameter s_RX_DATA_BITS = 3'b010;
+  parameter s_RX_STOP_BIT  = 3'b011;
+  parameter s_CLEANUP      = 3'b100;
+   
+  reg           r_Rx_Data_R ;
+  reg           r_Rx_Data   ;
+   
+  reg [15:0]     r_Clock_Count ;
+  reg [2:0]     r_Bit_Index  ; //8 bits total
+  reg [7:0]     r_Rx_Byte   ;
+  reg           r_Rx_DV     ;
+  reg [2:0]     r_SM_Main   ;
+   
+  // Purpose: Double-register the incoming data.
+  // This allows it to be used in the UART RX Clock Domain.
+  // (It removes problems caused by metastability)
+  always @(posedge clk_i)
+  begin
+    if (~rst_ni) begin
+      r_Rx_Data_R <= 1'b1;
+      r_Rx_Data   <= 1'b1;
+    end else begin
+      r_Rx_Data_R <= i_Rx_Serial;
+      r_Rx_Data   <= r_Rx_Data_R;
+    end
+  end
+   
+   
+  // Purpose: Control RX state machine
+  always @(posedge clk_i or negedge rst_ni)
+  begin
+    if (~rst_ni) begin
+      r_SM_Main <= s_IDLE;
+      r_Rx_DV       <= 1'b0;
+      r_Clock_Count <= 16'b0;
+      r_Bit_Index   <= 3'b0;
+	    r_Rx_Byte     <= 8'b0;
+    end else begin       
+      case (r_SM_Main)
+        s_IDLE :
+        begin
+          r_Rx_DV       <= 1'b0;
+          r_Clock_Count <= 16'b0;
+          r_Bit_Index   <= 3'b0;
+          r_Rx_Byte     <= 8'b0; 
+          if (r_Rx_Data == 1'b0)          // Start bit detected
+            r_SM_Main <= s_RX_START_BIT;
+          else
+            r_SM_Main <= s_IDLE;
+        end
+         
+        // Check middle of start bit to make sure it's still low
+        s_RX_START_BIT :
+        begin
+          if (r_Clock_Count == ((CLKS_PER_BIT-1)>>1))
+          begin
+            if (r_Rx_Data == 1'b0)
+              begin
+                r_Clock_Count <= 16'b0;  // reset counter, found the middle
+                r_SM_Main     <= s_RX_DATA_BITS;
+              end else
+                r_SM_Main <= s_IDLE;
+              end
+            else begin
+              r_Clock_Count <= r_Clock_Count + 16'b1;
+              r_SM_Main     <= s_RX_START_BIT;
+          end
+        end // case: s_RX_START_BIT
+         
+         
+        // Wait CLKS_PER_BIT-1 clock cycles to sample serial data
+        s_RX_DATA_BITS :
+        begin
+          if (r_Clock_Count < CLKS_PER_BIT-1)
+          begin
+            r_Clock_Count <= r_Clock_Count + 16'b1;
+            r_SM_Main     <= s_RX_DATA_BITS;
+          end
+          else
+          begin
+            r_Clock_Count          <= 16'b0;
+            r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
+                 
+                // Check if we have received all bits
+            if (r_Bit_Index < 7)
+            begin
+              r_Bit_Index <= r_Bit_Index + 3'b1;
+              r_SM_Main   <= s_RX_DATA_BITS;
+            end
+              else
+              begin
+                r_Bit_Index <= 3'b0;
+                r_SM_Main   <= s_RX_STOP_BIT;
+              end
+            end
+          end // case: s_RX_DATA_BITS
+     
+     
+        // Receive Stop bit.  Stop bit = 1
+        s_RX_STOP_BIT :
+        begin
+            // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
+          if (r_Clock_Count < CLKS_PER_BIT-1)
+          begin
+            r_Clock_Count <= r_Clock_Count + 16'b1;
+            r_SM_Main     <= s_RX_STOP_BIT;
+          end
+          else
+          begin
+            r_Rx_DV       <= 1'b1;
+            r_Clock_Count <= 16'b0;
+            r_SM_Main     <= s_CLEANUP;
+          end
+        end // case: s_RX_STOP_BIT
+     
+         
+        // Stay here 1 clock
+        s_CLEANUP :
+        begin
+          r_SM_Main <= s_IDLE;
+          r_Rx_DV   <= 1'b0;
+        end
+         
+         
+        default :
+          r_SM_Main <= s_IDLE;
+         
+      endcase
+    end
+  end   
+   
+  assign o_Rx_DV   = r_Rx_DV;
+  assign o_Rx_Byte = r_Rx_Byte;
+   
+endmodule // uart_rx
diff --git a/hw/ip/pwm/rtl/pwm_channel.v b/hw/ip/pwm/rtl/pwm_channel.v
new file mode 100644
index 00000000..074d6405
--- /dev/null
+++ b/hw/ip/pwm/rtl/pwm_channel.v
@@ -0,0 +1,64 @@
+
+module pwm_channel(
+
+input wire clock_1,
+input wire clock_2,
+input wire rst_ni,
+input wire ctrl1,
+input wire ctrl2,
+input wire pwm_1,
+input wire pwm_2,
+input wire [15:0] period,
+input wire [15:0] period_2,
+input wire [15:0] DC_1,
+input wire [15:0] DC_2,
+output reg oe_pwm1,
+output reg oe_pwm2,
+output reg pts,
+output reg pts_2
+);
+
+reg [15:0] period_counter1;
+reg [15:0] period_counter2;
+always @(posedge clock_1 or negedge rst_ni)
+	if (!rst_ni) begin
+		pts <= 1'b0;
+		oe_pwm1 <= 1'b0;
+		period_counter1 <= 16'b0000000000000000;
+	end
+	else if (ctrl1) begin
+		if (pwm_1) begin
+			oe_pwm1 <= 1'b1;
+			if (period_counter1 >= period)
+				period_counter1 <= 16'b0000000000000000;
+			else
+				period_counter1 <= period_counter1 + 16'b0000000000000001;
+			if (period_counter1 < DC_1)
+				pts <= 1'b1;
+			else
+				pts <= 1'b0;
+		end
+	end
+
+	always @(posedge clock_2 or negedge rst_ni)
+	if (!rst_ni) begin
+		pts_2 <= 1'b0;
+		oe_pwm2 <= 1'b0;
+		period_counter2 <= 16'b0000000000000000;
+	end
+	else if (ctrl2) begin
+		if (pwm_2) begin
+			oe_pwm2 <= 1'b1;
+			if (period_counter2 >= period_2)
+				period_counter2 <= 16'b0000000000000000;
+			else
+				period_counter2 <= period_counter2 + 16'b0000000000000001;
+			if (period_counter2 < DC_2)
+				pts_2 <= 1'b1;
+			else
+				pts_2 <= 1'b0;
+		end
+	end
+
+endmodule 
+
diff --git a/hw/ip/pwm/rtl/pwm_clock.v b/hw/ip/pwm/rtl/pwm_clock.v
new file mode 100644
index 00000000..afe9570f
--- /dev/null
+++ b/hw/ip/pwm/rtl/pwm_clock.v
@@ -0,0 +1,37 @@
+
+module pwm_clock(
+input wire clk_i,
+input wire rst_ni,
+input wire pwm_1,
+input wire pwm_2,
+input wire [15:0] divisor,
+input wire [15:0] divisor_2,
+output reg clock_p1,
+output reg clock_p2
+);
+ reg [15:0] counter_p1;
+ reg [15:0] counter_p2;
+ always @(posedge clk_i or negedge rst_ni)
+ if (~rst_ni) begin
+		clock_p1 <= 1'b0;
+		clock_p2 <= 1'b0;
+		counter_p1 <= 16'b0000000000000000;
+		counter_p2 <= 16'b0000000000000000;
+	end
+	else begin
+		if (pwm_1) begin
+			counter_p1 <= counter_p1 + 16'b0000000000000001;
+			if (counter_p1 == (divisor - 1)) begin
+				counter_p1 <= 16'b0000000000000000;
+				clock_p1 <= ~clock_p1;
+			end
+		end
+		if (pwm_2) begin
+			counter_p2 <= counter_p2 + 16'b0000000000000001;
+			if (counter_p2 == (divisor_2 - 1)) begin
+				counter_p2 <= 16'b0000000000000000;
+				clock_p2 <= ~clock_p2;
+			end
+		end
+	end
+endmodule 
diff --git a/hw/ip/pwm/rtl/pwm_core.v b/hw/ip/pwm/rtl/pwm_core.v
new file mode 100644
index 00000000..2ec663ea
--- /dev/null
+++ b/hw/ip/pwm/rtl/pwm_core.v
@@ -0,0 +1,107 @@
+
+module	pwm_core(
+//tlul interface
+input wire clk_i,												
+input wire rst_ni,												
+input wire re_i,											
+input wire we_i,											
+input wire  [7:0]    addr_i,											
+input wire [31:0]   wdata_i,											
+input wire [3:0]	be_i,										
+output wire [31:0]rdata_o, 																						output wire         o_pwm,
+output wire         o_pwm_2,
+output  wire     oe_pwm1,
+output  wire     oe_pwm2
+
+);
+
+////////////////////control logic////////////////////////////
+parameter  adr_ctrl_1	=	0,
+		   adr_divisor_1=	4,
+		   adr_period_1	=	8,
+		   adr_DC_1		=	12;
+
+parameter  adr_ctrl_2	=	16,
+		   adr_divisor_2=	20,
+		   adr_period_2	=	24,
+		   adr_DC_2		=	28;
+
+
+
+	reg [2:0] ctrl;
+	reg [15:0] period;
+	reg [15:0] DC_1;
+	reg [15:0] divisor;
+	reg [2:0] ctrl_2;
+	reg [15:0] period_2;
+	reg [15:0] DC_2;
+	reg [15:0] divisor_2;
+	wire write;
+	assign write = we_i & ~re_i;
+	always @(posedge clk_i) begin
+		if (!rst_ni) begin
+			ctrl <= 3'b000;
+			DC_1 <= 16'b0000000000000000;
+			period <= 16'b0000000000000000;
+			divisor <= 16'b0000000000000000;
+			ctrl_2 <= 3'b000;
+			DC_2 <= 16'b0000000000000000;
+			period_2 <= 16'b0000000000000000;
+			divisor_2 <= 16'b0000000000000000;
+		end
+		else if (write) begin
+			case (addr_i)
+				adr_ctrl_1: ctrl <= wdata_i[2:0];
+				adr_ctrl_2: ctrl_2 <= wdata_i[2:0];
+				adr_divisor_1: divisor <= wdata_i[15:0];
+				adr_period_1: period <= wdata_i[15:0];
+				adr_DC_1: DC_1 <= wdata_i[15:0];
+				adr_divisor_2: divisor_2 <= wdata_i[15:0];
+				adr_period_2: period_2 <= wdata_i[15:0];
+				adr_DC_2: DC_2 <= wdata_i[15:0];
+			endcase
+		end
+	end
+	wire pwm_1;
+	assign pwm_1 = ctrl[1];
+	wire pwm_2;
+	assign pwm_2 = ctrl_2[1];
+	wire clock1;
+	wire clock2;
+	wire pts;
+	wire pts_2;
+pwm_clock pwm_clk(
+.clk_i 	    (clk_i),
+.rst_ni	    (rst_ni),
+.pwm_1	    (pwm_1),
+.pwm_2	    (pwm_2),
+.divisor    (divisor),
+.divisor_2  (divisor_2),
+.clock_p1   (clock1),
+.clock_p2   (clock2)
+);
+
+pwm_channel pwm_chnl(
+
+.clock_1	(clock1),
+.clock_2	(clock2),
+.rst_ni		(rst_ni),
+.ctrl1		(ctrl[0]),
+.ctrl2		(ctrl_2[0]),
+.pwm_1		(pwm_1),
+.pwm_2		(pwm_2),
+.period		(period),
+.period_2	(period_2),
+.DC_1		(DC_1),
+.DC_2		(DC_2),
+.oe_pwm1	(oe_pwm1),
+.oe_pwm2	(oe_pwm2),
+.pts		(pts),
+.pts_2		(pts_2)
+);
+
+	assign o_pwm = (ctrl[2] ? pts : 1'b0);
+	assign o_pwm_2 = (ctrl_2[2] ? pts_2 : 1'b0);
+	assign rdata_o = (addr_i == adr_ctrl_1 ? {13'h0, ctrl} : (addr_i == adr_divisor_1 ? divisor : (addr_i == adr_period_1 ? period : (addr_i == adr_DC_1 ? DC_1 : (addr_i == adr_DC_2 ? DC_2 : (addr_i == adr_period_2 ? period_2 : (addr_i == adr_divisor_2 ? divisor_2 : (addr_i == adr_ctrl_2 ? {13'h0, ctrl_2} : 32'b00000000000000000000000000000000))))))));
+endmodule
+
diff --git a/hw/ip/pwm/src/rtl/pwm_top.sv b/hw/ip/pwm/rtl/pwm_top.sv
similarity index 73%
rename from hw/ip/pwm/src/rtl/pwm_top.sv
rename to hw/ip/pwm/rtl/pwm_top.sv
index 92560db4..6573254c 100644
--- a/hw/ip/pwm/src/rtl/pwm_top.sv
+++ b/hw/ip/pwm/rtl/pwm_top.sv
@@ -1,15 +1,17 @@
 
 module pwm_top (
 
-  input clk_i,
-  input rst_ni,
+  input logic clk_i,
+  input logic rst_ni,
 
   input  tlul_pkg::tl_h2d_t tl_i,
   output tlul_pkg::tl_d2h_t tl_o,
 
 
-  output        pwm_o,
-  output        pwm_o_2
+  output  logic      pwm_o,
+  output  logic      pwm_o_2,
+  output  logic      pwm1_oe,
+  output  logic      pwm2_oe
 
 );
 
@@ -28,7 +30,7 @@ logic         err;
 
 //assign err = '0;
 
-PWM pwm_core(
+pwm pwm_core(
 
 .clk_i      (clk_i),												
 .rst_ni     (rst_ni),												
@@ -39,13 +41,11 @@ PWM pwm_core(
 .wdata_i    (wdata),												
 .be_i       (be),										    
 .rdata_o    (rdata),												
-.error_o    (err),												
-
-.i_extclk   ('0),
-.i_DC       ('0),
-.i_valid_DC ('0),
+//.error_o    (err),												
 .o_pwm      (pwm_o),
-.o_pwm_2    (pwm_o_2)
+.o_pwm_2    (pwm_o_2),
+.oe_pwm1    (pwm1_oe),
+.oe_pwm2    (pwm2_oe)
 
 );
 
@@ -65,7 +65,7 @@ tlul_adapter_reg #(
   .wdata_o (wdata),
   .be_o    (be),
   .rdata_i (rdata),
-  .error_i (err)
+  .error_i (1'b0)
 );
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/hw/ip/pwm/src/rtl/PWM.v b/hw/ip/pwm/src/rtl/PWM.v
deleted file mode 100644
index 4040886b..00000000
--- a/hw/ip/pwm/src/rtl/PWM.v
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
-control register [7:0]ctrl:
-bit 0:	When set, external clock is chosen for PWM/timer. When cleared, wb clock is used for PWM/timer.
-bit 1:	When set,  PWM is enabled. When cleared,  timer is enabled.
-bit 2:	When set,  PWM/timer starts. When cleared, PWM/timer stops.
-bit 3:	When set, timer runs continuously. When cleared, timer runs one time.
-bit 4:	When set, o_pwm enabled.
-bit 5:	timer interrupt bit	When it is written with 0, interrupt request is cleared. 
-bit 6:	When set, a 16-bit external signal i_DC is used as duty cycle. When cleared, register DC is used.
-bit 7:	When set, counter reset for PWM/timer, it's output and bit 5 will also be cleared. When changing from PWM mode to timer mode reset is needed before timer starts.
-*/
-module	PWM(
-//tlul interface
-	input 					clk_i,												
-	input 					rst_ni,												
-
-	input 					re_i,											
-	input 					we_i,											
-	input  [7:0]    addr_i,											
-	input  [31:0]   wdata_i,											
-	input  [3:0]		be_i,										
-	output [31:0]   rdata_o,												
-	output          error_o,												
-
-	input						i_extclk,
-	input	 [15:0]		i_DC,
-	input						i_valid_DC,
-	output					o_pwm,
-	output          o_pwm_2
-
-);
-
-////////////////////control logic////////////////////////////
-parameter	 adr_ctrl_1			=	0,
-					 adr_divisor_1	=	4,
-					 adr_period_1		=	8,
-					 adr_DC_1				=	12;
-
-parameter  adr_ctrl_2		=	16,
-					 adr_divisor_2=	20,
-					 adr_period_2	=	24,
-					 adr_DC_2			=	28;
-
-
-
-					 
-reg	[7:0]  ctrl;
-reg	[15:0] period;		
-reg	[15:0] DC;		
-reg	[15:0] divisor;	
-
-reg	[7:0]  ctrl_2;
-reg	[15:0] period_2;		
-reg	[15:0] DC_2;		
-reg	[15:0] divisor_2;	
-
-wire	     write;
-
-assign	   write = we_i & ~re_i;
-
-always@(posedge clk_i)
-	if(~rst_ni)begin
-		ctrl[4:2]	<=	0;
-		ctrl[0]  	<=	0;
-		ctrl[7:6]	<=	0;
-		DC				<=	0;
-		period		<=	0;
-		divisor		<=	0;
-
-		
-		ctrl_2[4:2]	<=	0;
-		ctrl_2[0]  	<=	0;
-		ctrl_2[7:6]	<=	0;
-		DC_2				<=	0;
-		period_2		<=	0;
-		divisor_2		<=	0;
-	end
-	else if(write)begin
-		case(addr_i)
-			adr_ctrl_1:begin
-				ctrl[0]	<=	wdata_i[0];
-				ctrl[4:2]	<=	wdata_i[4:2];
-				ctrl[7:6]	<=	wdata_i[7:6];
-			end
-
-			adr_ctrl_2:begin
-				ctrl_2[0]	<=	wdata_i[0];
-				ctrl_2[4:2]	<=	wdata_i[4:2];
-				ctrl_2[7:6]	<=	wdata_i[7:6];
-			end
-
-			adr_divisor_1	:  divisor	<=	wdata_i[15:0];
-			adr_period_1	:  period		<=	wdata_i[15:0];
-			adr_DC_1			:  DC				<=	wdata_i[15:0];
-
-			adr_divisor_2	:  divisor_2	<=	wdata_i[15:0];
-			adr_period_2	:  period_2		<=	wdata_i[15:0];
-			adr_DC_2			:  DC_2				<=	wdata_i[15:0];
-		endcase
-	end
-
-
-
-wire		  pwm;
-always @(posedge clk_i) begin
-  	ctrl[1] <= 1'b1;
-end
-
-
-assign		pwm 	  = ctrl[1];
-
-wire		  pwm_1;
-always @(posedge clk_i) begin
-    ctrl_2[1]   <= 1'b1;
-end
-
-assign		pwm_1 	  = ctrl_2[1];
-wire	    eclk_2,oclk_2;
-///////////////////////////////////////////////////////////
-
-//////down clocking for pwm///////////////////
-wire	  clk_source;
-wire	  eclk,oclk;
-assign	clk_source = clk_i;
-down_clocking_even	clock_div_ev(
-	.i_clk			(clk_source) ,
-	.i_rst			(rst_ni),
-	.i_divisor	({1'b0,divisor[15:1]}),
-	.o_clk			(eclk)
-);
-down_clocking_odd	clock_div_od(
-	.i_clk			(clk_source),
-	.i_rst			(rst_ni),
-	.i_divisor	({1'b0,divisor[15:1]}),
-	.o_clk			(oclk)
-);
-wire	  clk;
-assign	clk = divisor[0]? oclk: eclk;
-
-
-
-
-down_clocking_even	clock_div_ev_2(
-	.i_clk			(clk_source) ,
-	.i_rst			(rst_ni),
-	.i_divisor	({1'b0,divisor_2[15:1]}),
-	.o_clk			(eclk_2)
-);
-down_clocking_odd	clock_div_od_2(
-	.i_clk			(clk_source),
-	.i_rst			(rst_ni),
-	.i_divisor	({1'b0,divisor_2[15:1]}),
-	.o_clk			(oclk_2)
-);
-wire	  clk_2;
-assign	clk_2 = divisor_2[0]? oclk_2: eclk_2;
-
-///////////////////////////////////////////////////////
-
-/////////////////main counter //////////////////////////
-reg		[15:0]   		ct;
-reg								pts;	//PWM signal 
-reg		[15:0]			extDC;
-wire	[15:0]			DC_1;
-assign						DC_1 =	ctrl[6]?	extDC:	DC;	//external or internal duty cycle toggle
-wire	[15:0]			period_1;
-assign						period_1	=	(period==0)?	0:	(period-1);
-
-wire							rst_ct;
-assign						rst_ct	=	~rst_ni|ctrl[7];
-
-
-reg		[15:0]   		ct_2;
-reg								pts_2;	//PWM signal 
-reg		[15:0]			extDC_2;
-wire	[15:0]			DCw_2;
-assign						DCw_2 =	ctrl_2[6]?	extDC_2:	DC_2;	//external or internal duty cycle toggle
-wire	[15:0]			period_P2;
-assign						period_P2	=	(period_2==0)?	0:	(period_2-1);
-
-wire							rst_ct_2;
-assign						rst_ct_2	=	~rst_ni|ctrl_2[7];
-
-always@(posedge clk )
-	if(rst_ct)begin
-		pts<=0;
-		ct<=0;
-		extDC<=0;
-	end
-	else begin
-	if(i_valid_DC)	extDC	<=	i_DC;
-	if(ctrl[2])begin
-		if(pwm) begin
-			if(ct	>=	period_1) ct	<=	0;
-			else ct	<=	ct+1;
-
-			if(ct	<	DC_1)	pts	<=	1;
-			else pts	<=	0;
-		end
-	end
-	else begin
-			pts	<=	0;
-			ct	<=	0;
-	end
-end
-
-
-
-always@(posedge clk_2 )
-	if(rst_ct_2)begin
-		pts_2		<=	0;
-		ct_2	<=	0;
-		extDC_2	<=	0;
-	end
-	else begin
-	if(i_valid_DC)	extDC_2	<=	i_DC;
-	if(ctrl_2[2])begin
-		if(pwm_1) begin
-			if(ct_2	>=	period_P2) ct_2	<=	0;
-			else ct_2	<=	ct_2+1;
-
-			if(ct_2	<	DCw_2)	pts_2	<=	1;
-			else pts_2	<=	0;
-		end
-	end
-	else begin
-			pts_2	<=	0;
-			ct_2	<=	0;
-	end
-end
-//////////////////////////////////////////////////////////
-
-assign	o_pwm = ctrl[4]? pts: 0;
-assign	o_pwm_2 = ctrl_2[4]? pts_2: 0;
-assign	rdata_o =	 (addr_i == adr_ctrl_1)		? {8'h0,ctrl}		:
-			  					 (addr_i == adr_divisor_1)? divisor		 		:
-			  					 (addr_i == adr_period_1)	? period		 		:
-			  					 (addr_i == adr_DC_1)			? DC				 		: 
-									 (addr_i == adr_DC_2)			? DC_2			 		:
-									 (addr_i == adr_period_2) ? period_2	 		:
-									 (addr_i == adr_divisor_2)? divisor_2  		:
-									 (addr_i == adr_ctrl_2)   ? {8'h0,ctrl_2} :0;
-
-
-endmodule
\ No newline at end of file
diff --git a/hw/ip/pwm/src/rtl/down_clocking_even.v b/hw/ip/pwm/src/rtl/down_clocking_even.v
deleted file mode 100644
index 8d006ce9..00000000
--- a/hw/ip/pwm/src/rtl/down_clocking_even.v
+++ /dev/null
@@ -1,37 +0,0 @@
-/*Down clocking module
-Output clock frequency is the original frequency divided by an even number
-*/
-module	down_clocking_even(
-input	i_clk,
-input	i_rst,
-input	[15:0]i_divisor,
-output	o_clk
-);
-
-wire	[15:0]divisor;
-wire	borrow;
-
-minus_one	minus_one_0(
-.i_operand(i_divisor),
-.o_result(divisor),
-.o_borrow(borrow)
-);
-
-wire	go;
-assign	go=((i_divisor!=0)&&i_rst);
-reg	[15:0]ct;
-reg	clk;
-always@(posedge i_clk )
-	if(!i_rst)begin
-		ct<=0;
-		clk<=0;
-	end
-	else if(go)begin
-		if(ct>=divisor)begin
-			ct<=0;
-			clk<=~clk;
-		end
-		else ct<=ct+1;
-	end
-assign	o_clk=go?clk:i_clk;
-endmodule
\ No newline at end of file
diff --git a/hw/ip/pwm/src/rtl/down_clocking_odd.v b/hw/ip/pwm/src/rtl/down_clocking_odd.v
deleted file mode 100644
index 7f6cc832..00000000
--- a/hw/ip/pwm/src/rtl/down_clocking_odd.v
+++ /dev/null
@@ -1,69 +0,0 @@
-/*Author: Zhuxu
-	m99a1@yahoo.cn
-Down clocking module
-Output clock frequency is the original frequency divided by an odd number
-*/
-module down_clocking_odd(
-input	i_clk,
-input	i_rst,
-input	[15:0]i_divisor,
-output	o_clk
-);
-
-reg	a,b;
-wire	c;
-
-assign	c=(~a)&(~b);
-wire	[15:0]divisor;
-wire	borrow;
-minus_one	minus_one_0(
-.i_operand(i_divisor),
-.o_result(divisor),
-.o_borrow(borrow)
-);
-
-wire	go;
-assign	go=((i_divisor!=0)&&i_rst);
-reg	[15:0]ct_0;
-always@(posedge i_clk )
-	if(!i_rst)begin
-		a<=0;
-		ct_0<=0;	
-	end
-	else if(go)begin
-		if(a)begin
-			if(ct_0>=divisor)begin
-				ct_0<=0;
-				a<=0;
-			end
-			else ct_0<=ct_0+1;
-		end
-		else if(c)a<=c;
-	end
-
-
-reg	[15:0]ct_1;
-always@(negedge i_clk )
-	if(!i_rst)begin
-		b<=0;
-		ct_1<=0;	
-	end
-	else if(go)begin
-		if(b)begin
-			if(ct_1>=divisor)begin
-				ct_1<=0;
-				b<=0;
-			end
-			else ct_1<=ct_1+1;
-		end
-		else if(c)b<=c;
-	end
-
-reg	clk;
-always@(posedge c)
-	if(!i_rst)clk<=0;
-	else	clk<=~clk;
-
-assign	o_clk=go?clk:i_clk;
-
-endmodule
\ No newline at end of file
diff --git a/hw/ip/pwm/src/rtl/minus_one.v b/hw/ip/pwm/src/rtl/minus_one.v
deleted file mode 100644
index f3575c94..00000000
--- a/hw/ip/pwm/src/rtl/minus_one.v
+++ /dev/null
@@ -1,122 +0,0 @@
-/*Author: Zhuxu
-	m99a1@yahoo.cn
-Use parallel prefix tree structure to reduce a 16-bit number by one.
-
-stage 0:	number of genration=16;	number of logic operation=16;	G_0[xx]=~i_operand[xx];
-stage 1:	NOG=16;			NOO=8;				G_1[2n-1]=G_0[2n-1]&&G_0[2n-2];	n=8:1
-stage 2:	NOG=16;			NOO=7;				G_2[2n-1]=G_1[2n-1]&&G_1[2n-3];	n=8:2
-stage 3:	NOG=16;			NOO=6;				G_3[2n-1]=G_2[2n-1]&&G_2[2n-5];	n=8:3	
-stage 4:	NOG=16;			NOO=4;				G_4[2n-1]=G_3[2n-1]&&G_3[2n-9];	n=8:5	
-stage 5:	NOG=16;			NOO=7;				G_5[2n]=G_4[2n]&&G_4[2n-1];	n=7:1
-
-*/
-module minus_one(
-input	[15:0]i_operand,
-output	[15:0]o_result,
-output	o_borrow
-);
-//stage 0
-wire	[15:0]G_0;
-assign	G_0=~i_operand;
-
-//stage 1
-wire	[15:0]G_1;
-assign	G_1[1]=G_0[1]&G_0[0];
-assign	G_1[3]=G_0[3]&G_0[2];
-assign	G_1[5]=G_0[5]&G_0[4];
-assign	G_1[7]=G_0[7]&G_0[6];
-assign	G_1[9]=G_0[9]&G_0[8];
-assign	G_1[11]=G_0[11]&G_0[10];
-assign	G_1[13]=G_0[13]&G_0[12];
-assign	G_1[15]=G_0[15]&G_0[14];
-assign	G_1[0]=G_0[0];
-assign	G_1[2]=G_0[2];
-assign	G_1[4]=G_0[4];
-assign	G_1[6]=G_0[6];
-assign	G_1[8]=G_0[8];
-assign	G_1[10]=G_0[10];
-assign	G_1[12]=G_0[12];
-assign	G_1[14]=G_0[14];
-
-//stage 2
-wire	[15:0]G_2;
-assign	G_2[3]=G_1[3]&G_1[1];
-assign	G_2[5]=G_1[5]&G_1[3];
-assign	G_2[7]=G_1[7]&G_1[5];
-assign	G_2[9]=G_1[9]&G_1[7];
-assign	G_2[11]=G_1[11]&G_1[9];
-assign	G_2[13]=G_1[13]&G_1[11];
-assign	G_2[15]=G_1[15]&G_1[13];
-assign	G_2[0]=G_1[0];
-assign	G_2[2]=G_1[2];
-assign	G_2[1]=G_1[1];
-assign	G_2[4]=G_1[4];
-assign	G_2[6]=G_1[6];
-assign	G_2[8]=G_1[8];
-assign	G_2[10]=G_1[10];
-assign	G_2[12]=G_1[12];
-assign	G_2[14]=G_1[14];
-
-//stage 3
-wire	[15:0]G_3;
-assign	G_3[5]=G_2[5]&G_2[1];
-assign	G_3[7]=G_2[7]&G_2[3];
-assign	G_3[9]=G_2[9]&G_2[5];
-assign	G_3[11]=G_2[11]&G_2[7];
-assign	G_3[13]=G_2[13]&G_2[9];
-assign	G_3[15]=G_2[15]&G_2[11];
-assign	G_3[0]=G_2[0];
-assign	G_3[2]=G_2[2];
-assign	G_3[1]=G_2[1];
-assign	G_3[4]=G_2[4];
-assign	G_3[3]=G_2[3];
-assign	G_3[6]=G_2[6];
-assign	G_3[8]=G_2[8];
-assign	G_3[10]=G_2[10];
-assign	G_3[12]=G_2[12];
-assign	G_3[14]=G_2[14];
-
-//stage 4
-wire	[15:0]G_4;
-assign	G_4[9]=G_3[9]&G_3[1];
-assign	G_4[11]=G_3[11]&G_3[3];
-assign	G_4[13]=G_3[13]&G_3[5];
-assign	G_4[15]=G_3[15]&G_3[7];
-assign	G_4[0]=G_3[0];
-assign	G_4[2]=G_3[2];
-assign	G_4[1]=G_3[1];
-assign	G_4[4]=G_3[4];
-assign	G_4[3]=G_3[3];
-assign	G_4[6]=G_3[6];
-assign	G_4[5]=G_3[5];
-assign	G_4[8]=G_3[8];
-assign	G_4[7]=G_3[7];
-assign	G_4[10]=G_3[10];
-assign	G_4[12]=G_3[12];
-assign	G_4[14]=G_3[14];
-
-//stage 5
-wire	[15:0]G_5;
-assign	G_5[2]=G_4[2]&G_4[1];
-assign	G_5[4]=G_4[4]&G_4[3];
-assign	G_5[6]=G_4[6]&G_4[5];
-assign	G_5[8]=G_4[8]&G_4[7];
-assign	G_5[10]=G_4[10]&G_4[9];
-assign	G_5[12]=G_4[12]&G_4[11];
-assign	G_5[14]=G_4[14]&G_4[13];
-assign	G_5[1]=G_4[1];
-assign	G_5[3]=G_4[3];
-assign	G_5[5]=G_4[5];
-assign	G_5[7]=G_4[7];
-assign	G_5[9]=G_4[9];
-assign	G_5[11]=G_4[11];
-assign	G_5[13]=G_4[13];
-assign	G_5[15]=G_4[15];
-assign	G_5[0]=G_4[0];
-
-//stage 6
-assign	o_result[0]=~i_operand[0];
-assign	o_result[15:1]=(G_5[14:0]&(~i_operand[15:1]))|((~G_5[14:0])&i_operand[15:1]);
-assign	o_borrow=G_5[15];
-
-endmodule
\ No newline at end of file
diff --git a/hw/ip/rv_plic/rtl/rv_plic.sv b/hw/ip/rv_plic/rtl/rv_plic.sv
index 34729417..4d0d3aa7 100644
--- a/hw/ip/rv_plic/rtl/rv_plic.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic.sv
@@ -18,19 +18,18 @@ module rv_plic import rv_plic_reg_pkg::*; #(
   // derived parameter
   localparam int SRCW    = $clog2(NumSrc)
 ) (
-  input     clk_i,
-  input     rst_ni,
+  input logic     clk_i,
+  input logic     rst_ni,
 
   // Bus Interface (device)
   input  tlul_pkg::tl_h2d_t tl_i,
   output tlul_pkg::tl_d2h_t tl_o,
 
   // Interrupt Sources
-  input  [NumSrc-1:0] intr_src_i,
+  input  logic [NumSrc-1:0] intr_src_i,
 
   // Interrupt notification to targets
-  output [NumTarget-1:0] irq_o,
-  output [SRCW-1:0]      irq_id_o [NumTarget],
+  output logic [NumTarget-1:0] irq_o,
 
   output logic [NumTarget-1:0] msip_o
 );
@@ -38,9 +37,11 @@ module rv_plic import rv_plic_reg_pkg::*; #(
   rv_plic_reg2hw_t reg2hw;
   rv_plic_hw2reg_t hw2reg;
 
-  localparam int MAX_PRIO    = 7;
+  localparam int MAX_PRIO    = 3;
   localparam int PRIOW = $clog2(MAX_PRIO+1);
 
+  logic [SRCW:0]      irq_id_o [NumTarget];
+
   logic [NumSrc-1:0] le; // 0:level 1:edge
   logic [NumSrc-1:0] ip;
 
@@ -54,7 +55,7 @@ module rv_plic import rv_plic_reg_pkg::*; #(
   logic [SRCW-1:0]      complete_id [NumTarget];
   logic [NumSrc-1:0]    complete; // Converted from complete_re/complete_id
 
-  logic [SRCW-1:0]      cc_id [NumTarget]; // Write ID
+  logic [SRCW:0]      cc_id [NumTarget]; // Write ID
 
   logic [PRIOW-1:0] prio [NumSrc];
 
@@ -66,13 +67,17 @@ module rv_plic import rv_plic_reg_pkg::*; #(
   always_comb begin
     claim = '0;
     for (int i = 0 ; i < NumTarget ; i++) begin
-      if (claim_re[i]) claim[claim_id[i]] = 1'b1;
-    end
+      if (claim_re[i]) begin 
+         claim[claim_id[i]] = 1'b1;
+     end
+  end
   end
   always_comb begin
     complete = '0;
     for (int i = 0 ; i < NumTarget ; i++) begin
-      if (complete_we[i]) complete[complete_id[i]] = 1'b1;
+      if (complete_we[i]) begin 
+         complete[complete_id[i]] = 1'b1;
+      end 
     end
   end
 
@@ -116,11 +121,14 @@ module rv_plic import rv_plic_reg_pkg::*; #(
   assign prio[29] = reg2hw.prio29.q;
   assign prio[30] = reg2hw.prio30.q;
   assign prio[31] = reg2hw.prio31.q;
-
+  assign prio[32] = reg2hw.prio32.q;
+  assign prio[33] = reg2hw.prio33.q;
+  assign prio[34] = reg2hw.prio34.q;
+  assign prio[35] = reg2hw.prio35.q;
   //////////////////////
   // Interrupt Enable //
   //////////////////////
-  for (genvar s = 0; s < 32; s++) begin : gen_ie0
+  for (genvar s = 0; s < 36; s++) begin : gen_ie0
     assign ie[0][s] = reg2hw.ie0[s].q;
   end
 
@@ -146,7 +154,7 @@ module rv_plic import rv_plic_reg_pkg::*; #(
   ////////
   // IP //
   ////////
-  for (genvar s = 0; s < 32; s++) begin : gen_ip
+  for (genvar s = 0; s < 36; s++) begin : gen_ip
     assign hw2reg.ip[s].de = 1'b1; // Always write
     assign hw2reg.ip[s].d  = ip[s];
   end
@@ -154,7 +162,7 @@ module rv_plic import rv_plic_reg_pkg::*; #(
   ///////////////////////////////////
   // Detection:: 0: Level, 1: Edge //
   ///////////////////////////////////
-  for (genvar s = 0; s < 32; s++) begin : gen_le
+  for (genvar s = 0; s < 36; s++) begin : gen_le
     assign le[s] = reg2hw.le[s].q;
   end
 
@@ -217,17 +225,7 @@ module rv_plic import rv_plic_reg_pkg::*; #(
     .devmode_i  (1'b1)
   );
 
-  // Assertions
-//  `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
-//  `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
-//  `ASSERT_KNOWN(IrqKnownO_A, irq_o)
-//  `ASSERT_KNOWN(MsipKnownO_A, msip_o)
-//  for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known
-//    `ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o[k])
-//  end
-
-//  // Assume
-//  `ASSUME(Irq0Tied_A, intr_src_i[0] == 1'b0)
+
 
 endmodule
 
diff --git a/hw/ip/rv_plic/rtl/rv_plic_gateway.sv b/hw/ip/rv_plic/rtl/rv_plic_gateway.sv
index c81810b2..e3f3f64f 100644
--- a/hw/ip/rv_plic/rtl/rv_plic_gateway.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic_gateway.sv
@@ -7,14 +7,14 @@
 module rv_plic_gateway #(
   parameter int N_SOURCE = 32
 ) (
-  input clk_i,
-  input rst_ni,
+  input logic clk_i,
+  input logic rst_ni,
 
-  input [N_SOURCE-1:0] src_i,
-  input [N_SOURCE-1:0] le_i,      // Level0 Edge1
+  input logic [N_SOURCE-1:0] src_i,
+  input logic [N_SOURCE-1:0] le_i,      // Level0 Edge1
 
-  input [N_SOURCE-1:0] claim_i, // $onehot0(claim_i)
-  input [N_SOURCE-1:0] complete_i, // $onehot0(complete_i)
+  input logic [N_SOURCE-1:0] claim_i, // $onehot0(claim_i)
+  input logic [N_SOURCE-1:0] complete_i, // $onehot0(complete_i)
 
   output logic [N_SOURCE-1:0] ip_o
 );
diff --git a/hw/ip/rv_plic/rtl/rv_plic_reg_pkg.sv b/hw/ip/rv_plic/rtl/rv_plic_reg_pkg.sv
index 9b0451d5..7e5408c1 100644
--- a/hw/ip/rv_plic/rtl/rv_plic_reg_pkg.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic_reg_pkg.sv
@@ -7,11 +7,12 @@
 package rv_plic_reg_pkg;
 
   // Param list
-  parameter int NumSrc = 32;
+  parameter int NumSrc = 36;
   parameter int NumTarget = 1;
+  parameter int PrioWidth = 2;
 
   // Address width within the block
-  parameter int BlockAw = 9;
+  parameter int BlockAw = 10;
 
   ////////////////////////////
   // Typedefs for registers //
@@ -21,139 +22,155 @@ package rv_plic_reg_pkg;
   } rv_plic_reg2hw_le_mreg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio0_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio1_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio2_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio3_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio4_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio5_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio6_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio7_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio8_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio9_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio10_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio11_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio12_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio13_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio14_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio15_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio16_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio17_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio18_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio19_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio20_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio21_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio22_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio23_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio24_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio25_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio26_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio27_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio28_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio29_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio30_reg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_prio31_reg_t;
 
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio32_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio33_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio34_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio35_reg_t;
+
   typedef struct packed {
     logic        q;
   } rv_plic_reg2hw_ie0_mreg_t;
 
   typedef struct packed {
-    logic [2:0]  q;
+    logic [1:0]  q;
   } rv_plic_reg2hw_threshold0_reg_t;
 
   typedef struct packed {
@@ -181,42 +198,46 @@ package rv_plic_reg_pkg;
   // Register to internal design logic //
   ///////////////////////////////////////
   typedef struct packed {
-    rv_plic_reg2hw_le_mreg_t [31:0] le; // [171:140]
-    rv_plic_reg2hw_prio0_reg_t prio0; // [139:137]
-    rv_plic_reg2hw_prio1_reg_t prio1; // [136:134]
-    rv_plic_reg2hw_prio2_reg_t prio2; // [133:131]
-    rv_plic_reg2hw_prio3_reg_t prio3; // [130:128]
-    rv_plic_reg2hw_prio4_reg_t prio4; // [127:125]
-    rv_plic_reg2hw_prio5_reg_t prio5; // [124:122]
-    rv_plic_reg2hw_prio6_reg_t prio6; // [121:119]
-    rv_plic_reg2hw_prio7_reg_t prio7; // [118:116]
-    rv_plic_reg2hw_prio8_reg_t prio8; // [115:113]
-    rv_plic_reg2hw_prio9_reg_t prio9; // [112:110]
-    rv_plic_reg2hw_prio10_reg_t prio10; // [109:107]
-    rv_plic_reg2hw_prio11_reg_t prio11; // [106:104]
-    rv_plic_reg2hw_prio12_reg_t prio12; // [103:101]
-    rv_plic_reg2hw_prio13_reg_t prio13; // [100:98]
-    rv_plic_reg2hw_prio14_reg_t prio14; // [97:95]
-    rv_plic_reg2hw_prio15_reg_t prio15; // [94:92]
-    rv_plic_reg2hw_prio16_reg_t prio16; // [91:89]
-    rv_plic_reg2hw_prio17_reg_t prio17; // [88:86]
-    rv_plic_reg2hw_prio18_reg_t prio18; // [85:83]
-    rv_plic_reg2hw_prio19_reg_t prio19; // [82:80]
-    rv_plic_reg2hw_prio20_reg_t prio20; // [79:77]
-    rv_plic_reg2hw_prio21_reg_t prio21; // [76:74]
-    rv_plic_reg2hw_prio22_reg_t prio22; // [73:71]
-    rv_plic_reg2hw_prio23_reg_t prio23; // [70:68]
-    rv_plic_reg2hw_prio24_reg_t prio24; // [67:65]
-    rv_plic_reg2hw_prio25_reg_t prio25; // [64:62]
-    rv_plic_reg2hw_prio26_reg_t prio26; // [61:59]
-    rv_plic_reg2hw_prio27_reg_t prio27; // [58:56]
-    rv_plic_reg2hw_prio28_reg_t prio28; // [55:53]
-    rv_plic_reg2hw_prio29_reg_t prio29; // [52:50]
-    rv_plic_reg2hw_prio30_reg_t prio30; // [49:47]
-    rv_plic_reg2hw_prio31_reg_t prio31; // [46:44]
-    rv_plic_reg2hw_ie0_mreg_t [31:0] ie0; // [43:12]
-    rv_plic_reg2hw_threshold0_reg_t threshold0; // [11:9]
-    rv_plic_reg2hw_cc0_reg_t cc0; // [8:1]
+    rv_plic_reg2hw_le_mreg_t [35:0] le; // [700:529]
+    rv_plic_reg2hw_prio0_reg_t prio0; // [528:527]
+    rv_plic_reg2hw_prio1_reg_t prio1; // [526:525]
+    rv_plic_reg2hw_prio2_reg_t prio2; // [524:523]
+    rv_plic_reg2hw_prio3_reg_t prio3; // [522:521]
+    rv_plic_reg2hw_prio4_reg_t prio4; // [520:519]
+    rv_plic_reg2hw_prio5_reg_t prio5; // [518:517]
+    rv_plic_reg2hw_prio6_reg_t prio6; // [516:515]
+    rv_plic_reg2hw_prio7_reg_t prio7; // [514:513]
+    rv_plic_reg2hw_prio8_reg_t prio8; // [512:511]
+    rv_plic_reg2hw_prio9_reg_t prio9; // [510:509]
+    rv_plic_reg2hw_prio10_reg_t prio10; // [508:507]
+    rv_plic_reg2hw_prio11_reg_t prio11; // [506:505]
+    rv_plic_reg2hw_prio12_reg_t prio12; // [504:503]
+    rv_plic_reg2hw_prio13_reg_t prio13; // [502:501]
+    rv_plic_reg2hw_prio14_reg_t prio14; // [500:499]
+    rv_plic_reg2hw_prio15_reg_t prio15; // [498:497]
+    rv_plic_reg2hw_prio16_reg_t prio16; // [496:495]
+    rv_plic_reg2hw_prio17_reg_t prio17; // [494:493]
+    rv_plic_reg2hw_prio18_reg_t prio18; // [492:491]
+    rv_plic_reg2hw_prio19_reg_t prio19; // [490:489]
+    rv_plic_reg2hw_prio20_reg_t prio20; // [488:487]
+    rv_plic_reg2hw_prio21_reg_t prio21; // [486:485]
+    rv_plic_reg2hw_prio22_reg_t prio22; // [484:483]
+    rv_plic_reg2hw_prio23_reg_t prio23; // [482:481]
+    rv_plic_reg2hw_prio24_reg_t prio24; // [480:479]
+    rv_plic_reg2hw_prio25_reg_t prio25; // [478:477]
+    rv_plic_reg2hw_prio26_reg_t prio26; // [476:475]
+    rv_plic_reg2hw_prio27_reg_t prio27; // [474:473]
+    rv_plic_reg2hw_prio28_reg_t prio28; // [472:471]
+    rv_plic_reg2hw_prio29_reg_t prio29; // [470:469]
+    rv_plic_reg2hw_prio30_reg_t prio30; // [468:467]
+    rv_plic_reg2hw_prio31_reg_t prio31; // [466:465]
+    rv_plic_reg2hw_prio32_reg_t prio32; // [464:463]
+    rv_plic_reg2hw_prio33_reg_t prio33; // [462:461]
+    rv_plic_reg2hw_prio34_reg_t prio34; // [460:459]
+    rv_plic_reg2hw_prio35_reg_t prio35; // [458:457]
+    rv_plic_reg2hw_ie0_mreg_t [35:0] ie0; // [184:13]
+    rv_plic_reg2hw_threshold0_reg_t threshold0; // [12:11]
+    rv_plic_reg2hw_cc0_reg_t cc0; // [10:1]
     rv_plic_reg2hw_msip0_reg_t msip0; // [0:0]
   } rv_plic_reg2hw_t;
 
@@ -224,55 +245,64 @@ package rv_plic_reg_pkg;
   // Internal design logic to register //
   ///////////////////////////////////////
   typedef struct packed {
-    rv_plic_hw2reg_ip_mreg_t [31:0] ip; // [69:6]
-    rv_plic_hw2reg_cc0_reg_t cc0; // [5:0]
+    rv_plic_hw2reg_ip_mreg_t [35:0] ip; // [351:8]
+    rv_plic_hw2reg_cc0_reg_t cc0; // [7:0]
   } rv_plic_hw2reg_t;
 
   // Register Address
-  parameter logic [BlockAw-1:0] RV_PLIC_IP_OFFSET = 9'h 0;
-  parameter logic [BlockAw-1:0] RV_PLIC_LE_OFFSET = 9'h 4;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO0_OFFSET = 9'h 8;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO1_OFFSET = 9'h c;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO2_OFFSET = 9'h 10;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO3_OFFSET = 9'h 14;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO4_OFFSET = 9'h 18;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO5_OFFSET = 9'h 1c;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO6_OFFSET = 9'h 20;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO7_OFFSET = 9'h 24;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO8_OFFSET = 9'h 28;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO9_OFFSET = 9'h 2c;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO10_OFFSET = 9'h 30;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO11_OFFSET = 9'h 34;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO12_OFFSET = 9'h 38;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO13_OFFSET = 9'h 3c;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO14_OFFSET = 9'h 40;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO15_OFFSET = 9'h 44;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO16_OFFSET = 9'h 48;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO17_OFFSET = 9'h 4c;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO18_OFFSET = 9'h 50;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO19_OFFSET = 9'h 54;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO20_OFFSET = 9'h 58;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO21_OFFSET = 9'h 5c;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO22_OFFSET = 9'h 60;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO23_OFFSET = 9'h 64;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO24_OFFSET = 9'h 68;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO25_OFFSET = 9'h 6c;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO26_OFFSET = 9'h 70;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO27_OFFSET = 9'h 74;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO28_OFFSET = 9'h 78;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO29_OFFSET = 9'h 7c;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO30_OFFSET = 9'h 80;
-  parameter logic [BlockAw-1:0] RV_PLIC_PRIO31_OFFSET = 9'h 84;
-  parameter logic [BlockAw-1:0] RV_PLIC_IE0_OFFSET = 9'h 100;
-  parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 9'h 104;
-  parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 9'h 108;
-  parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 9'h 10c;
+  parameter logic [BlockAw-1:0] RV_PLIC_IP_0_OFFSET = 10'h 0;
+  parameter logic [BlockAw-1:0] RV_PLIC_IP_1_OFFSET = 10'h 4;
+  parameter logic [BlockAw-1:0] RV_PLIC_LE_0_OFFSET = 10'h 8;
+  parameter logic [BlockAw-1:0] RV_PLIC_LE_1_OFFSET = 10'h c;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO0_OFFSET = 10'h 10;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO1_OFFSET = 10'h 14;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO2_OFFSET = 10'h 18;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO3_OFFSET = 10'h 1c;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO4_OFFSET = 10'h 20;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO5_OFFSET = 10'h 24;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO6_OFFSET = 10'h 28;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO7_OFFSET = 10'h 2c;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO8_OFFSET = 10'h 30;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO9_OFFSET = 10'h 34;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO10_OFFSET = 10'h 38;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO11_OFFSET = 10'h 3c;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO12_OFFSET = 10'h 40;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO13_OFFSET = 10'h 44;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO14_OFFSET = 10'h 48;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO15_OFFSET = 10'h 4c;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO16_OFFSET = 10'h 50;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO17_OFFSET = 10'h 54;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO18_OFFSET = 10'h 58;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO19_OFFSET = 10'h 5c;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO20_OFFSET = 10'h 60;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO21_OFFSET = 10'h 64;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO22_OFFSET = 10'h 68;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO23_OFFSET = 10'h 6c;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO24_OFFSET = 10'h 70;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO25_OFFSET = 10'h 74;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO26_OFFSET = 10'h 78;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO27_OFFSET = 10'h 7c;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO28_OFFSET = 10'h 80;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO29_OFFSET = 10'h 84;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO30_OFFSET = 10'h 88;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO31_OFFSET = 10'h 8c;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO32_OFFSET = 10'h 90;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO33_OFFSET = 10'h 94;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO34_OFFSET = 10'h 98;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO35_OFFSET = 10'h 9c;
+  parameter logic [BlockAw-1:0] RV_PLIC_IE0_0_OFFSET  = 10'h a0;
+  parameter logic [BlockAw-1:0] RV_PLIC_IE0_1_OFFSET  = 10'h a4;
+  parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 10'h a8;
+  parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 10'h ac;
+  parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 10'h b0;
 
 
   // Register Index
   typedef enum int {
-    RV_PLIC_IP,
-    RV_PLIC_LE,
+    RV_PLIC_IP_0,
+    RV_PLIC_IP_1,
+    RV_PLIC_LE_0,
+    RV_PLIC_LE_1,
     RV_PLIC_PRIO0,
     RV_PLIC_PRIO1,
     RV_PLIC_PRIO2,
@@ -305,52 +335,64 @@ package rv_plic_reg_pkg;
     RV_PLIC_PRIO29,
     RV_PLIC_PRIO30,
     RV_PLIC_PRIO31,
-    RV_PLIC_IE0,
+    RV_PLIC_PRIO32,
+    RV_PLIC_PRIO33,
+    RV_PLIC_PRIO34,
+    RV_PLIC_PRIO35,
+    RV_PLIC_IE0_0,
+    RV_PLIC_IE0_1,
     RV_PLIC_THRESHOLD0,
     RV_PLIC_CC0,
     RV_PLIC_MSIP0
   } rv_plic_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] RV_PLIC_PERMIT [38] = '{
-    4'b 1111, // index[ 0] RV_PLIC_IP
-    4'b 1111, // index[ 1] RV_PLIC_LE
-    4'b 0001, // index[ 2] RV_PLIC_PRIO0
-    4'b 0001, // index[ 3] RV_PLIC_PRIO1
-    4'b 0001, // index[ 4] RV_PLIC_PRIO2
-    4'b 0001, // index[ 5] RV_PLIC_PRIO3
-    4'b 0001, // index[ 6] RV_PLIC_PRIO4
-    4'b 0001, // index[ 7] RV_PLIC_PRIO5
-    4'b 0001, // index[ 8] RV_PLIC_PRIO6
-    4'b 0001, // index[ 9] RV_PLIC_PRIO7
-    4'b 0001, // index[10] RV_PLIC_PRIO8
-    4'b 0001, // index[11] RV_PLIC_PRIO9
-    4'b 0001, // index[12] RV_PLIC_PRIO10
-    4'b 0001, // index[13] RV_PLIC_PRIO11
-    4'b 0001, // index[14] RV_PLIC_PRIO12
-    4'b 0001, // index[15] RV_PLIC_PRIO13
-    4'b 0001, // index[16] RV_PLIC_PRIO14
-    4'b 0001, // index[17] RV_PLIC_PRIO15
-    4'b 0001, // index[18] RV_PLIC_PRIO16
-    4'b 0001, // index[19] RV_PLIC_PRIO17
-    4'b 0001, // index[20] RV_PLIC_PRIO18
-    4'b 0001, // index[21] RV_PLIC_PRIO19
-    4'b 0001, // index[22] RV_PLIC_PRIO20
-    4'b 0001, // index[23] RV_PLIC_PRIO21
-    4'b 0001, // index[24] RV_PLIC_PRIO22
-    4'b 0001, // index[25] RV_PLIC_PRIO23
-    4'b 0001, // index[26] RV_PLIC_PRIO24
-    4'b 0001, // index[27] RV_PLIC_PRIO25
-    4'b 0001, // index[28] RV_PLIC_PRIO26
-    4'b 0001, // index[29] RV_PLIC_PRIO27
-    4'b 0001, // index[30] RV_PLIC_PRIO28
-    4'b 0001, // index[31] RV_PLIC_PRIO29
-    4'b 0001, // index[32] RV_PLIC_PRIO30
-    4'b 0001, // index[33] RV_PLIC_PRIO31
-    4'b 1111, // index[34] RV_PLIC_IE0
-    4'b 0001, // index[35] RV_PLIC_THRESHOLD0
-    4'b 0001, // index[36] RV_PLIC_CC0
-    4'b 0001  // index[37] RV_PLIC_MSIP0
+  parameter logic [3:0] RV_PLIC_PERMIT [45] = '{
+    4'b 1111, // index[  0] RV_PLIC_IP_0
+    4'b 1111, // index[  1] RV_PLIC_IP_1
+    4'b 1111, // index[  6] RV_PLIC_LE_0
+    4'b 1111, // index[  7] RV_PLIC_LE_1
+    4'b 0001, // index[ 12] RV_PLIC_PRIO0
+    4'b 0001, // index[ 13] RV_PLIC_PRIO1
+    4'b 0001, // index[ 14] RV_PLIC_PRIO2
+    4'b 0001, // index[ 15] RV_PLIC_PRIO3
+    4'b 0001, // index[ 16] RV_PLIC_PRIO4
+    4'b 0001, // index[ 17] RV_PLIC_PRIO5
+    4'b 0001, // index[ 18] RV_PLIC_PRIO6
+    4'b 0001, // index[ 19] RV_PLIC_PRIO7
+    4'b 0001, // index[ 20] RV_PLIC_PRIO8
+    4'b 0001, // index[ 21] RV_PLIC_PRIO9
+    4'b 0001, // index[ 22] RV_PLIC_PRIO10
+    4'b 0001, // index[ 23] RV_PLIC_PRIO11
+    4'b 0001, // index[ 24] RV_PLIC_PRIO12
+    4'b 0001, // index[ 25] RV_PLIC_PRIO13
+    4'b 0001, // index[ 26] RV_PLIC_PRIO14
+    4'b 0001, // index[ 27] RV_PLIC_PRIO15
+    4'b 0001, // index[ 28] RV_PLIC_PRIO16
+    4'b 0001, // index[ 29] RV_PLIC_PRIO17
+    4'b 0001, // index[ 30] RV_PLIC_PRIO18
+    4'b 0001, // index[ 31] RV_PLIC_PRIO19
+    4'b 0001, // index[ 32] RV_PLIC_PRIO20
+    4'b 0001, // index[ 33] RV_PLIC_PRIO21
+    4'b 0001, // index[ 34] RV_PLIC_PRIO22
+    4'b 0001, // index[ 35] RV_PLIC_PRIO23
+    4'b 0001, // index[ 36] RV_PLIC_PRIO24
+    4'b 0001, // index[ 37] RV_PLIC_PRIO25
+    4'b 0001, // index[ 38] RV_PLIC_PRIO26
+    4'b 0001, // index[ 39] RV_PLIC_PRIO27
+    4'b 0001, // index[ 40] RV_PLIC_PRIO28
+    4'b 0001, // index[ 41] RV_PLIC_PRIO29
+    4'b 0001, // index[ 42] RV_PLIC_PRIO30
+    4'b 0001, // index[ 43] RV_PLIC_PRIO31
+    4'b 0001, // index[ 44] RV_PLIC_PRIO32
+    4'b 0001, // index[ 45] RV_PLIC_PRIO33
+    4'b 0001, // index[ 46] RV_PLIC_PRIO34
+    4'b 0001, // index[ 47] RV_PLIC_PRIO35
+    4'b 1111, // index[184] RV_PLIC_IE0_0
+    4'b 1111, // index[185] RV_PLIC_IE0_1
+    4'b 0001, // index[190] RV_PLIC_THRESHOLD0
+    4'b 0001, // index[191] RV_PLIC_CC0
+    4'b 0001  // index[192] RV_PLIC_MSIP0
   };
 endpackage
 
diff --git a/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv b/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
index 6d3da698..2a741fca 100644
--- a/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
@@ -4,9 +4,10 @@
 //
 // Register Top module auto-generated by `reggen`
 
+
 module rv_plic_reg_top (
-  input clk_i,
-  input rst_ni,
+  input logic clk_i,
+  input logic rst_ni,
 
   // Below Regster interface can be changed
   input  tlul_pkg::tl_h2d_t tl_i,
@@ -21,7 +22,7 @@ module rv_plic_reg_top (
 
   import rv_plic_reg_pkg::* ;
 
-  localparam int AW = 9;
+  localparam int AW = 10;
   localparam int DW = 32;
   localparam int DBW = DW/8;                    // Byte Width
 
@@ -69,328 +70,376 @@ module rv_plic_reg_top (
   // Define SW related signals
   // Format: <reg>_<field>_{wd|we|qs}
   //        or <reg>_{wd|we|qs} if field == 1 or 0
-  logic ip_p_0_qs;
-  logic ip_p_1_qs;
-  logic ip_p_2_qs;
-  logic ip_p_3_qs;
-  logic ip_p_4_qs;
-  logic ip_p_5_qs;
-  logic ip_p_6_qs;
-  logic ip_p_7_qs;
-  logic ip_p_8_qs;
-  logic ip_p_9_qs;
-  logic ip_p_10_qs;
-  logic ip_p_11_qs;
-  logic ip_p_12_qs;
-  logic ip_p_13_qs;
-  logic ip_p_14_qs;
-  logic ip_p_15_qs;
-  logic ip_p_16_qs;
-  logic ip_p_17_qs;
-  logic ip_p_18_qs;
-  logic ip_p_19_qs;
-  logic ip_p_20_qs;
-  logic ip_p_21_qs;
-  logic ip_p_22_qs;
-  logic ip_p_23_qs;
-  logic ip_p_24_qs;
-  logic ip_p_25_qs;
-  logic ip_p_26_qs;
-  logic ip_p_27_qs;
-  logic ip_p_28_qs;
-  logic ip_p_29_qs;
-  logic ip_p_30_qs;
-  logic ip_p_31_qs;
-  logic le_le_0_qs;
-  logic le_le_0_wd;
-  logic le_le_0_we;
-  logic le_le_1_qs;
-  logic le_le_1_wd;
-  logic le_le_1_we;
-  logic le_le_2_qs;
-  logic le_le_2_wd;
-  logic le_le_2_we;
-  logic le_le_3_qs;
-  logic le_le_3_wd;
-  logic le_le_3_we;
-  logic le_le_4_qs;
-  logic le_le_4_wd;
-  logic le_le_4_we;
-  logic le_le_5_qs;
-  logic le_le_5_wd;
-  logic le_le_5_we;
-  logic le_le_6_qs;
-  logic le_le_6_wd;
-  logic le_le_6_we;
-  logic le_le_7_qs;
-  logic le_le_7_wd;
-  logic le_le_7_we;
-  logic le_le_8_qs;
-  logic le_le_8_wd;
-  logic le_le_8_we;
-  logic le_le_9_qs;
-  logic le_le_9_wd;
-  logic le_le_9_we;
-  logic le_le_10_qs;
-  logic le_le_10_wd;
-  logic le_le_10_we;
-  logic le_le_11_qs;
-  logic le_le_11_wd;
-  logic le_le_11_we;
-  logic le_le_12_qs;
-  logic le_le_12_wd;
-  logic le_le_12_we;
-  logic le_le_13_qs;
-  logic le_le_13_wd;
-  logic le_le_13_we;
-  logic le_le_14_qs;
-  logic le_le_14_wd;
-  logic le_le_14_we;
-  logic le_le_15_qs;
-  logic le_le_15_wd;
-  logic le_le_15_we;
-  logic le_le_16_qs;
-  logic le_le_16_wd;
-  logic le_le_16_we;
-  logic le_le_17_qs;
-  logic le_le_17_wd;
-  logic le_le_17_we;
-  logic le_le_18_qs;
-  logic le_le_18_wd;
-  logic le_le_18_we;
-  logic le_le_19_qs;
-  logic le_le_19_wd;
-  logic le_le_19_we;
-  logic le_le_20_qs;
-  logic le_le_20_wd;
-  logic le_le_20_we;
-  logic le_le_21_qs;
-  logic le_le_21_wd;
-  logic le_le_21_we;
-  logic le_le_22_qs;
-  logic le_le_22_wd;
-  logic le_le_22_we;
-  logic le_le_23_qs;
-  logic le_le_23_wd;
-  logic le_le_23_we;
-  logic le_le_24_qs;
-  logic le_le_24_wd;
-  logic le_le_24_we;
-  logic le_le_25_qs;
-  logic le_le_25_wd;
-  logic le_le_25_we;
-  logic le_le_26_qs;
-  logic le_le_26_wd;
-  logic le_le_26_we;
-  logic le_le_27_qs;
-  logic le_le_27_wd;
-  logic le_le_27_we;
-  logic le_le_28_qs;
-  logic le_le_28_wd;
-  logic le_le_28_we;
-  logic le_le_29_qs;
-  logic le_le_29_wd;
-  logic le_le_29_we;
-  logic le_le_30_qs;
-  logic le_le_30_wd;
-  logic le_le_30_we;
-  logic le_le_31_qs;
-  logic le_le_31_wd;
-  logic le_le_31_we;
-  logic [2:0] prio0_qs;
-  logic [2:0] prio0_wd;
+  logic ip_0_p_0_qs;
+  logic ip_0_p_1_qs;
+  logic ip_0_p_2_qs;
+  logic ip_0_p_3_qs;
+  logic ip_0_p_4_qs;
+  logic ip_0_p_5_qs;
+  logic ip_0_p_6_qs;
+  logic ip_0_p_7_qs;
+  logic ip_0_p_8_qs;
+  logic ip_0_p_9_qs;
+  logic ip_0_p_10_qs;
+  logic ip_0_p_11_qs;
+  logic ip_0_p_12_qs;
+  logic ip_0_p_13_qs;
+  logic ip_0_p_14_qs;
+  logic ip_0_p_15_qs;
+  logic ip_0_p_16_qs;
+  logic ip_0_p_17_qs;
+  logic ip_0_p_18_qs;
+  logic ip_0_p_19_qs;
+  logic ip_0_p_20_qs;
+  logic ip_0_p_21_qs;
+  logic ip_0_p_22_qs;
+  logic ip_0_p_23_qs;
+  logic ip_0_p_24_qs;
+  logic ip_0_p_25_qs;
+  logic ip_0_p_26_qs;
+  logic ip_0_p_27_qs;
+  logic ip_0_p_28_qs;
+  logic ip_0_p_29_qs;
+  logic ip_0_p_30_qs;
+  logic ip_0_p_31_qs;
+  logic ip_1_p_32_qs;
+  logic ip_1_p_33_qs;
+  logic ip_1_p_34_qs;
+  logic ip_1_p_35_qs;
+  logic ip_1_p_36_qs;
+  logic ip_1_p_37_qs;
+  logic ip_1_p_38_qs;
+  logic ip_1_p_39_qs;
+  logic ip_1_p_40_qs;
+  logic ip_1_p_41_qs;
+  logic ip_1_p_42_qs;
+  logic ip_1_p_43_qs;
+  logic le_0_le_0_qs;
+  logic le_0_le_0_wd;
+  logic le_0_le_0_we;
+  logic le_0_le_1_qs;
+  logic le_0_le_1_wd;
+  logic le_0_le_1_we;
+  logic le_0_le_2_qs;
+  logic le_0_le_2_wd;
+  logic le_0_le_2_we;
+  logic le_0_le_3_qs;
+  logic le_0_le_3_wd;
+  logic le_0_le_3_we;
+  logic le_0_le_4_qs;
+  logic le_0_le_4_wd;
+  logic le_0_le_4_we;
+  logic le_0_le_5_qs;
+  logic le_0_le_5_wd;
+  logic le_0_le_5_we;
+  logic le_0_le_6_qs;
+  logic le_0_le_6_wd;
+  logic le_0_le_6_we;
+  logic le_0_le_7_qs;
+  logic le_0_le_7_wd;
+  logic le_0_le_7_we;
+  logic le_0_le_8_qs;
+  logic le_0_le_8_wd;
+  logic le_0_le_8_we;
+  logic le_0_le_9_qs;
+  logic le_0_le_9_wd;
+  logic le_0_le_9_we;
+  logic le_0_le_10_qs;
+  logic le_0_le_10_wd;
+  logic le_0_le_10_we;
+  logic le_0_le_11_qs;
+  logic le_0_le_11_wd;
+  logic le_0_le_11_we;
+  logic le_0_le_12_qs;
+  logic le_0_le_12_wd;
+  logic le_0_le_12_we;
+  logic le_0_le_13_qs;
+  logic le_0_le_13_wd;
+  logic le_0_le_13_we;
+  logic le_0_le_14_qs;
+  logic le_0_le_14_wd;
+  logic le_0_le_14_we;
+  logic le_0_le_15_qs;
+  logic le_0_le_15_wd;
+  logic le_0_le_15_we;
+  logic le_0_le_16_qs;
+  logic le_0_le_16_wd;
+  logic le_0_le_16_we;
+  logic le_0_le_17_qs;
+  logic le_0_le_17_wd;
+  logic le_0_le_17_we;
+  logic le_0_le_18_qs;
+  logic le_0_le_18_wd;
+  logic le_0_le_18_we;
+  logic le_0_le_19_qs;
+  logic le_0_le_19_wd;
+  logic le_0_le_19_we;
+  logic le_0_le_20_qs;
+  logic le_0_le_20_wd;
+  logic le_0_le_20_we;
+  logic le_0_le_21_qs;
+  logic le_0_le_21_wd;
+  logic le_0_le_21_we;
+  logic le_0_le_22_qs;
+  logic le_0_le_22_wd;
+  logic le_0_le_22_we;
+  logic le_0_le_23_qs;
+  logic le_0_le_23_wd;
+  logic le_0_le_23_we;
+  logic le_0_le_24_qs;
+  logic le_0_le_24_wd;
+  logic le_0_le_24_we;
+  logic le_0_le_25_qs;
+  logic le_0_le_25_wd;
+  logic le_0_le_25_we;
+  logic le_0_le_26_qs;
+  logic le_0_le_26_wd;
+  logic le_0_le_26_we;
+  logic le_0_le_27_qs;
+  logic le_0_le_27_wd;
+  logic le_0_le_27_we;
+  logic le_0_le_28_qs;
+  logic le_0_le_28_wd;
+  logic le_0_le_28_we;
+  logic le_0_le_29_qs;
+  logic le_0_le_29_wd;
+  logic le_0_le_29_we;
+  logic le_0_le_30_qs;
+  logic le_0_le_30_wd;
+  logic le_0_le_30_we;
+  logic le_0_le_31_qs;
+  logic le_0_le_31_wd;
+  logic le_0_le_31_we;
+  logic le_1_le_32_qs;
+  logic le_1_le_32_wd;
+  logic le_1_le_32_we;
+  logic le_1_le_33_qs;
+  logic le_1_le_33_wd;
+  logic le_1_le_33_we;
+  logic le_1_le_34_qs;
+  logic le_1_le_34_wd;
+  logic le_1_le_34_we;
+  logic le_1_le_35_qs;
+  logic le_1_le_35_wd;
+  logic le_1_le_35_we;
+  logic [1:0] prio0_qs;
+  logic [1:0] prio0_wd;
   logic prio0_we;
-  logic [2:0] prio1_qs;
-  logic [2:0] prio1_wd;
+  logic [1:0] prio1_qs;
+  logic [1:0] prio1_wd;
   logic prio1_we;
-  logic [2:0] prio2_qs;
-  logic [2:0] prio2_wd;
+  logic [1:0] prio2_qs;
+  logic [1:0] prio2_wd;
   logic prio2_we;
-  logic [2:0] prio3_qs;
-  logic [2:0] prio3_wd;
+  logic [1:0] prio3_qs;
+  logic [1:0] prio3_wd;
   logic prio3_we;
-  logic [2:0] prio4_qs;
-  logic [2:0] prio4_wd;
+  logic [1:0] prio4_qs;
+  logic [1:0] prio4_wd;
   logic prio4_we;
-  logic [2:0] prio5_qs;
-  logic [2:0] prio5_wd;
+  logic [1:0] prio5_qs;
+  logic [1:0] prio5_wd;
   logic prio5_we;
-  logic [2:0] prio6_qs;
-  logic [2:0] prio6_wd;
+  logic [1:0] prio6_qs;
+  logic [1:0] prio6_wd;
   logic prio6_we;
-  logic [2:0] prio7_qs;
-  logic [2:0] prio7_wd;
+  logic [1:0] prio7_qs;
+  logic [1:0] prio7_wd;
   logic prio7_we;
-  logic [2:0] prio8_qs;
-  logic [2:0] prio8_wd;
+  logic [1:0] prio8_qs;
+  logic [1:0] prio8_wd;
   logic prio8_we;
-  logic [2:0] prio9_qs;
-  logic [2:0] prio9_wd;
+  logic [1:0] prio9_qs;
+  logic [1:0] prio9_wd;
   logic prio9_we;
-  logic [2:0] prio10_qs;
-  logic [2:0] prio10_wd;
+  logic [1:0] prio10_qs;
+  logic [1:0] prio10_wd;
   logic prio10_we;
-  logic [2:0] prio11_qs;
-  logic [2:0] prio11_wd;
+  logic [1:0] prio11_qs;
+  logic [1:0] prio11_wd;
   logic prio11_we;
-  logic [2:0] prio12_qs;
-  logic [2:0] prio12_wd;
+  logic [1:0] prio12_qs;
+  logic [1:0] prio12_wd;
   logic prio12_we;
-  logic [2:0] prio13_qs;
-  logic [2:0] prio13_wd;
+  logic [1:0] prio13_qs;
+  logic [1:0] prio13_wd;
   logic prio13_we;
-  logic [2:0] prio14_qs;
-  logic [2:0] prio14_wd;
+  logic [1:0] prio14_qs;
+  logic [1:0] prio14_wd;
   logic prio14_we;
-  logic [2:0] prio15_qs;
-  logic [2:0] prio15_wd;
+  logic [1:0] prio15_qs;
+  logic [1:0] prio15_wd;
   logic prio15_we;
-  logic [2:0] prio16_qs;
-  logic [2:0] prio16_wd;
+  logic [1:0] prio16_qs;
+  logic [1:0] prio16_wd;
   logic prio16_we;
-  logic [2:0] prio17_qs;
-  logic [2:0] prio17_wd;
+  logic [1:0] prio17_qs;
+  logic [1:0] prio17_wd;
   logic prio17_we;
-  logic [2:0] prio18_qs;
-  logic [2:0] prio18_wd;
+  logic [1:0] prio18_qs;
+  logic [1:0] prio18_wd;
   logic prio18_we;
-  logic [2:0] prio19_qs;
-  logic [2:0] prio19_wd;
+  logic [1:0] prio19_qs;
+  logic [1:0] prio19_wd;
   logic prio19_we;
-  logic [2:0] prio20_qs;
-  logic [2:0] prio20_wd;
+  logic [1:0] prio20_qs;
+  logic [1:0] prio20_wd;
   logic prio20_we;
-  logic [2:0] prio21_qs;
-  logic [2:0] prio21_wd;
+  logic [1:0] prio21_qs;
+  logic [1:0] prio21_wd;
   logic prio21_we;
-  logic [2:0] prio22_qs;
-  logic [2:0] prio22_wd;
+  logic [1:0] prio22_qs;
+  logic [1:0] prio22_wd;
   logic prio22_we;
-  logic [2:0] prio23_qs;
-  logic [2:0] prio23_wd;
+  logic [1:0] prio23_qs;
+  logic [1:0] prio23_wd;
   logic prio23_we;
-  logic [2:0] prio24_qs;
-  logic [2:0] prio24_wd;
+  logic [1:0] prio24_qs;
+  logic [1:0] prio24_wd;
   logic prio24_we;
-  logic [2:0] prio25_qs;
-  logic [2:0] prio25_wd;
+  logic [1:0] prio25_qs;
+  logic [1:0] prio25_wd;
   logic prio25_we;
-  logic [2:0] prio26_qs;
-  logic [2:0] prio26_wd;
+  logic [1:0] prio26_qs;
+  logic [1:0] prio26_wd;
   logic prio26_we;
-  logic [2:0] prio27_qs;
-  logic [2:0] prio27_wd;
+  logic [1:0] prio27_qs;
+  logic [1:0] prio27_wd;
   logic prio27_we;
-  logic [2:0] prio28_qs;
-  logic [2:0] prio28_wd;
+  logic [1:0] prio28_qs;
+  logic [1:0] prio28_wd;
   logic prio28_we;
-  logic [2:0] prio29_qs;
-  logic [2:0] prio29_wd;
+  logic [1:0] prio29_qs;
+  logic [1:0] prio29_wd;
   logic prio29_we;
-  logic [2:0] prio30_qs;
-  logic [2:0] prio30_wd;
+  logic [1:0] prio30_qs;
+  logic [1:0] prio30_wd;
   logic prio30_we;
-  logic [2:0] prio31_qs;
-  logic [2:0] prio31_wd;
+  logic [1:0] prio31_qs;
+  logic [1:0] prio31_wd;
   logic prio31_we;
-  logic ie0_e_0_qs;
-  logic ie0_e_0_wd;
-  logic ie0_e_0_we;
-  logic ie0_e_1_qs;
-  logic ie0_e_1_wd;
-  logic ie0_e_1_we;
-  logic ie0_e_2_qs;
-  logic ie0_e_2_wd;
-  logic ie0_e_2_we;
-  logic ie0_e_3_qs;
-  logic ie0_e_3_wd;
-  logic ie0_e_3_we;
-  logic ie0_e_4_qs;
-  logic ie0_e_4_wd;
-  logic ie0_e_4_we;
-  logic ie0_e_5_qs;
-  logic ie0_e_5_wd;
-  logic ie0_e_5_we;
-  logic ie0_e_6_qs;
-  logic ie0_e_6_wd;
-  logic ie0_e_6_we;
-  logic ie0_e_7_qs;
-  logic ie0_e_7_wd;
-  logic ie0_e_7_we;
-  logic ie0_e_8_qs;
-  logic ie0_e_8_wd;
-  logic ie0_e_8_we;
-  logic ie0_e_9_qs;
-  logic ie0_e_9_wd;
-  logic ie0_e_9_we;
-  logic ie0_e_10_qs;
-  logic ie0_e_10_wd;
-  logic ie0_e_10_we;
-  logic ie0_e_11_qs;
-  logic ie0_e_11_wd;
-  logic ie0_e_11_we;
-  logic ie0_e_12_qs;
-  logic ie0_e_12_wd;
-  logic ie0_e_12_we;
-  logic ie0_e_13_qs;
-  logic ie0_e_13_wd;
-  logic ie0_e_13_we;
-  logic ie0_e_14_qs;
-  logic ie0_e_14_wd;
-  logic ie0_e_14_we;
-  logic ie0_e_15_qs;
-  logic ie0_e_15_wd;
-  logic ie0_e_15_we;
-  logic ie0_e_16_qs;
-  logic ie0_e_16_wd;
-  logic ie0_e_16_we;
-  logic ie0_e_17_qs;
-  logic ie0_e_17_wd;
-  logic ie0_e_17_we;
-  logic ie0_e_18_qs;
-  logic ie0_e_18_wd;
-  logic ie0_e_18_we;
-  logic ie0_e_19_qs;
-  logic ie0_e_19_wd;
-  logic ie0_e_19_we;
-  logic ie0_e_20_qs;
-  logic ie0_e_20_wd;
-  logic ie0_e_20_we;
-  logic ie0_e_21_qs;
-  logic ie0_e_21_wd;
-  logic ie0_e_21_we;
-  logic ie0_e_22_qs;
-  logic ie0_e_22_wd;
-  logic ie0_e_22_we;
-  logic ie0_e_23_qs;
-  logic ie0_e_23_wd;
-  logic ie0_e_23_we;
-  logic ie0_e_24_qs;
-  logic ie0_e_24_wd;
-  logic ie0_e_24_we;
-  logic ie0_e_25_qs;
-  logic ie0_e_25_wd;
-  logic ie0_e_25_we;
-  logic ie0_e_26_qs;
-  logic ie0_e_26_wd;
-  logic ie0_e_26_we;
-  logic ie0_e_27_qs;
-  logic ie0_e_27_wd;
-  logic ie0_e_27_we;
-  logic ie0_e_28_qs;
-  logic ie0_e_28_wd;
-  logic ie0_e_28_we;
-  logic ie0_e_29_qs;
-  logic ie0_e_29_wd;
-  logic ie0_e_29_we;
-  logic ie0_e_30_qs;
-  logic ie0_e_30_wd;
-  logic ie0_e_30_we;
-  logic ie0_e_31_qs;
-  logic ie0_e_31_wd;
-  logic ie0_e_31_we;
-  logic [2:0] threshold0_qs;
-  logic [2:0] threshold0_wd;
+  logic [1:0] prio32_qs;
+  logic [1:0] prio32_wd;
+  logic prio32_we;
+  logic [1:0] prio33_qs;
+  logic [1:0] prio33_wd;
+  logic prio33_we;
+  logic [1:0] prio34_qs;
+  logic [1:0] prio34_wd;
+  logic prio34_we;
+  logic [1:0] prio35_qs;
+  logic [1:0] prio35_wd;
+  logic prio35_we;
+  logic ie0_0_e_0_qs;
+  logic ie0_0_e_0_wd;
+  logic ie0_0_e_0_we;
+  logic ie0_0_e_1_qs;
+  logic ie0_0_e_1_wd;
+  logic ie0_0_e_1_we;
+  logic ie0_0_e_2_qs;
+  logic ie0_0_e_2_wd;
+  logic ie0_0_e_2_we;
+  logic ie0_0_e_3_qs;
+  logic ie0_0_e_3_wd;
+  logic ie0_0_e_3_we;
+  logic ie0_0_e_4_qs;
+  logic ie0_0_e_4_wd;
+  logic ie0_0_e_4_we;
+  logic ie0_0_e_5_qs;
+  logic ie0_0_e_5_wd;
+  logic ie0_0_e_5_we;
+  logic ie0_0_e_6_qs;
+  logic ie0_0_e_6_wd;
+  logic ie0_0_e_6_we;
+  logic ie0_0_e_7_qs;
+  logic ie0_0_e_7_wd;
+  logic ie0_0_e_7_we;
+  logic ie0_0_e_8_qs;
+  logic ie0_0_e_8_wd;
+  logic ie0_0_e_8_we;
+  logic ie0_0_e_9_qs;
+  logic ie0_0_e_9_wd;
+  logic ie0_0_e_9_we;
+  logic ie0_0_e_10_qs;
+  logic ie0_0_e_10_wd;
+  logic ie0_0_e_10_we;
+  logic ie0_0_e_11_qs;
+  logic ie0_0_e_11_wd;
+  logic ie0_0_e_11_we;
+  logic ie0_0_e_12_qs;
+  logic ie0_0_e_12_wd;
+  logic ie0_0_e_12_we;
+  logic ie0_0_e_13_qs;
+  logic ie0_0_e_13_wd;
+  logic ie0_0_e_13_we;
+  logic ie0_0_e_14_qs;
+  logic ie0_0_e_14_wd;
+  logic ie0_0_e_14_we;
+  logic ie0_0_e_15_qs;
+  logic ie0_0_e_15_wd;
+  logic ie0_0_e_15_we;
+  logic ie0_0_e_16_qs;
+  logic ie0_0_e_16_wd;
+  logic ie0_0_e_16_we;
+  logic ie0_0_e_17_qs;
+  logic ie0_0_e_17_wd;
+  logic ie0_0_e_17_we;
+  logic ie0_0_e_18_qs;
+  logic ie0_0_e_18_wd;
+  logic ie0_0_e_18_we;
+  logic ie0_0_e_19_qs;
+  logic ie0_0_e_19_wd;
+  logic ie0_0_e_19_we;
+  logic ie0_0_e_20_qs;
+  logic ie0_0_e_20_wd;
+  logic ie0_0_e_20_we;
+  logic ie0_0_e_21_qs;
+  logic ie0_0_e_21_wd;
+  logic ie0_0_e_21_we;
+  logic ie0_0_e_22_qs;
+  logic ie0_0_e_22_wd;
+  logic ie0_0_e_22_we;
+  logic ie0_0_e_23_qs;
+  logic ie0_0_e_23_wd;
+  logic ie0_0_e_23_we;
+  logic ie0_0_e_24_qs;
+  logic ie0_0_e_24_wd;
+  logic ie0_0_e_24_we;
+  logic ie0_0_e_25_qs;
+  logic ie0_0_e_25_wd;
+  logic ie0_0_e_25_we;
+  logic ie0_0_e_26_qs;
+  logic ie0_0_e_26_wd;
+  logic ie0_0_e_26_we;
+  logic ie0_0_e_27_qs;
+  logic ie0_0_e_27_wd;
+  logic ie0_0_e_27_we;
+  logic ie0_0_e_28_qs;
+  logic ie0_0_e_28_wd;
+  logic ie0_0_e_28_we;
+  logic ie0_0_e_29_qs;
+  logic ie0_0_e_29_wd;
+  logic ie0_0_e_29_we;
+  logic ie0_0_e_30_qs;
+  logic ie0_0_e_30_wd;
+  logic ie0_0_e_30_we;
+  logic ie0_0_e_31_qs;
+  logic ie0_0_e_31_wd;
+  logic ie0_0_e_31_we;
+  logic ie0_1_e_32_qs;
+  logic ie0_1_e_32_wd;
+  logic ie0_1_e_32_we;
+  logic ie0_1_e_33_qs;
+  logic ie0_1_e_33_wd;
+  logic ie0_1_e_33_we;
+  logic ie0_1_e_34_qs;
+  logic ie0_1_e_34_wd;
+  logic ie0_1_e_34_we;
+  logic ie0_1_e_35_qs;
+  logic ie0_1_e_35_wd;
+  logic ie0_1_e_35_we;
+  logic [1:0] threshold0_qs;
+  logic [1:0] threshold0_wd;
   logic threshold0_we;
   logic [5:0] cc0_qs;
   logic [5:0] cc0_wd;
@@ -403,14 +452,14 @@ module rv_plic_reg_top (
   // Register instances
 
   // Subregister 0 of Multireg ip
-  // R[ip]: V(False)
+  // R[ip_0]: V(False)
 
   // F[p_0]: 0:0
   prim_subreg #(
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_0 (
+  ) u_ip_0_p_0 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -426,7 +475,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_0_qs)
+    .qs     (ip_0_p_0_qs)
   );
 
 
@@ -435,7 +484,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_1 (
+  ) u_ip_0_p_1 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -451,7 +500,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_1_qs)
+    .qs     (ip_0_p_1_qs)
   );
 
 
@@ -460,7 +509,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_2 (
+  ) u_ip_0_p_2 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -476,7 +525,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_2_qs)
+    .qs     (ip_0_p_2_qs)
   );
 
 
@@ -485,7 +534,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_3 (
+  ) u_ip_0_p_3 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -501,7 +550,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_3_qs)
+    .qs     (ip_0_p_3_qs)
   );
 
 
@@ -510,7 +559,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_4 (
+  ) u_ip_0_p_4 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -526,7 +575,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_4_qs)
+    .qs     (ip_0_p_4_qs)
   );
 
 
@@ -535,7 +584,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_5 (
+  ) u_ip_0_p_5 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -551,7 +600,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_5_qs)
+    .qs     (ip_0_p_5_qs)
   );
 
 
@@ -560,7 +609,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_6 (
+  ) u_ip_0_p_6 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -576,7 +625,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_6_qs)
+    .qs     (ip_0_p_6_qs)
   );
 
 
@@ -585,7 +634,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_7 (
+  ) u_ip_0_p_7 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -601,7 +650,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_7_qs)
+    .qs     (ip_0_p_7_qs)
   );
 
 
@@ -610,7 +659,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_8 (
+  ) u_ip_0_p_8 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -626,7 +675,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_8_qs)
+    .qs     (ip_0_p_8_qs)
   );
 
 
@@ -635,7 +684,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_9 (
+  ) u_ip_0_p_9 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -651,7 +700,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_9_qs)
+    .qs     (ip_0_p_9_qs)
   );
 
 
@@ -660,7 +709,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_10 (
+  ) u_ip_0_p_10 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -676,7 +725,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_10_qs)
+    .qs     (ip_0_p_10_qs)
   );
 
 
@@ -685,7 +734,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_11 (
+  ) u_ip_0_p_11 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -701,7 +750,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_11_qs)
+    .qs     (ip_0_p_11_qs)
   );
 
 
@@ -710,7 +759,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_12 (
+  ) u_ip_0_p_12 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -726,7 +775,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_12_qs)
+    .qs     (ip_0_p_12_qs)
   );
 
 
@@ -735,7 +784,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_13 (
+  ) u_ip_0_p_13 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -751,7 +800,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_13_qs)
+    .qs     (ip_0_p_13_qs)
   );
 
 
@@ -760,7 +809,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_14 (
+  ) u_ip_0_p_14 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -776,7 +825,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_14_qs)
+    .qs     (ip_0_p_14_qs)
   );
 
 
@@ -785,7 +834,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_15 (
+  ) u_ip_0_p_15 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -801,7 +850,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_15_qs)
+    .qs     (ip_0_p_15_qs)
   );
 
 
@@ -810,7 +859,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_16 (
+  ) u_ip_0_p_16 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -826,7 +875,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_16_qs)
+    .qs     (ip_0_p_16_qs)
   );
 
 
@@ -835,7 +884,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_17 (
+  ) u_ip_0_p_17 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -851,7 +900,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_17_qs)
+    .qs     (ip_0_p_17_qs)
   );
 
 
@@ -860,7 +909,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_18 (
+  ) u_ip_0_p_18 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -876,7 +925,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_18_qs)
+    .qs     (ip_0_p_18_qs)
   );
 
 
@@ -885,7 +934,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_19 (
+  ) u_ip_0_p_19 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -901,7 +950,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_19_qs)
+    .qs     (ip_0_p_19_qs)
   );
 
 
@@ -910,7 +959,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_20 (
+  ) u_ip_0_p_20 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -926,7 +975,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_20_qs)
+    .qs     (ip_0_p_20_qs)
   );
 
 
@@ -935,7 +984,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_21 (
+  ) u_ip_0_p_21 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -951,7 +1000,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_21_qs)
+    .qs     (ip_0_p_21_qs)
   );
 
 
@@ -960,7 +1009,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_22 (
+  ) u_ip_0_p_22 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -976,7 +1025,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_22_qs)
+    .qs     (ip_0_p_22_qs)
   );
 
 
@@ -985,7 +1034,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_23 (
+  ) u_ip_0_p_23 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -1001,7 +1050,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_23_qs)
+    .qs     (ip_0_p_23_qs)
   );
 
 
@@ -1010,7 +1059,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_24 (
+  ) u_ip_0_p_24 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -1026,7 +1075,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_24_qs)
+    .qs     (ip_0_p_24_qs)
   );
 
 
@@ -1035,7 +1084,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_25 (
+  ) u_ip_0_p_25 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -1051,7 +1100,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_25_qs)
+    .qs     (ip_0_p_25_qs)
   );
 
 
@@ -1060,7 +1109,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_26 (
+  ) u_ip_0_p_26 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -1076,7 +1125,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_26_qs)
+    .qs     (ip_0_p_26_qs)
   );
 
 
@@ -1085,7 +1134,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_27 (
+  ) u_ip_0_p_27 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -1101,7 +1150,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_27_qs)
+    .qs     (ip_0_p_27_qs)
   );
 
 
@@ -1110,7 +1159,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_28 (
+  ) u_ip_0_p_28 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -1126,7 +1175,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_28_qs)
+    .qs     (ip_0_p_28_qs)
   );
 
 
@@ -1135,7 +1184,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_29 (
+  ) u_ip_0_p_29 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -1151,7 +1200,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_29_qs)
+    .qs     (ip_0_p_29_qs)
   );
 
 
@@ -1160,7 +1209,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_30 (
+  ) u_ip_0_p_30 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -1176,7 +1225,7 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_30_qs)
+    .qs     (ip_0_p_30_qs)
   );
 
 
@@ -1185,7 +1234,7 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RO"),
     .RESVAL  (1'h0)
-  ) u_ip_p_31 (
+  ) u_ip_0_p_31 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
@@ -1201,27 +1250,127 @@ module rv_plic_reg_top (
     .q      (),
 
     // to register interface (read)
-    .qs     (ip_p_31_qs)
+    .qs     (ip_0_p_31_qs)
+  );
+
+
+  // Subregister 32 of Multireg ip
+  // R[ip_1]: V(False)
+
+  // F[p_32]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip_1_p_32 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[32].de),
+    .d      (hw2reg.ip[32].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip_1_p_32_qs)
+  );
+
+
+  // F[p_33]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip_1_p_33 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[33].de),
+    .d      (hw2reg.ip[33].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip_1_p_33_qs)
+  );
+
+
+  // F[p_34]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip_1_p_34 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[34].de),
+    .d      (hw2reg.ip[34].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip_1_p_34_qs)
   );
 
 
+  // F[p_35]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip_1_p_35 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
 
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[35].de),
+    .d      (hw2reg.ip[35].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip_1_p_35_qs)
+  );
 
   // Subregister 0 of Multireg le
-  // R[le]: V(False)
+  // R[le_0]: V(False)
 
   // F[le_0]: 0:0
   prim_subreg #(
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_0 (
+  ) u_le_0_le_0 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_0_we),
-    .wd     (le_le_0_wd),
+    .we     (le_0_le_0_we),
+    .wd     (le_0_le_0_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1232,7 +1381,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[0].q ),
 
     // to register interface (read)
-    .qs     (le_le_0_qs)
+    .qs     (le_0_le_0_qs)
   );
 
 
@@ -1241,13 +1390,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_1 (
+  ) u_le_0_le_1 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_1_we),
-    .wd     (le_le_1_wd),
+    .we     (le_0_le_1_we),
+    .wd     (le_0_le_1_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1258,7 +1407,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[1].q ),
 
     // to register interface (read)
-    .qs     (le_le_1_qs)
+    .qs     (le_0_le_1_qs)
   );
 
 
@@ -1267,13 +1416,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_2 (
+  ) u_le_0_le_2 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_2_we),
-    .wd     (le_le_2_wd),
+    .we     (le_0_le_2_we),
+    .wd     (le_0_le_2_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1284,7 +1433,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[2].q ),
 
     // to register interface (read)
-    .qs     (le_le_2_qs)
+    .qs     (le_0_le_2_qs)
   );
 
 
@@ -1293,13 +1442,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_3 (
+  ) u_le_0_le_3 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_3_we),
-    .wd     (le_le_3_wd),
+    .we     (le_0_le_3_we),
+    .wd     (le_0_le_3_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1310,7 +1459,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[3].q ),
 
     // to register interface (read)
-    .qs     (le_le_3_qs)
+    .qs     (le_0_le_3_qs)
   );
 
 
@@ -1319,13 +1468,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_4 (
+  ) u_le_0_le_4 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_4_we),
-    .wd     (le_le_4_wd),
+    .we     (le_0_le_4_we),
+    .wd     (le_0_le_4_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1336,7 +1485,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[4].q ),
 
     // to register interface (read)
-    .qs     (le_le_4_qs)
+    .qs     (le_0_le_4_qs)
   );
 
 
@@ -1345,13 +1494,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_5 (
+  ) u_le_0_le_5 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_5_we),
-    .wd     (le_le_5_wd),
+    .we     (le_0_le_5_we),
+    .wd     (le_0_le_5_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1362,7 +1511,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[5].q ),
 
     // to register interface (read)
-    .qs     (le_le_5_qs)
+    .qs     (le_0_le_5_qs)
   );
 
 
@@ -1371,13 +1520,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_6 (
+  ) u_le_0_le_6 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_6_we),
-    .wd     (le_le_6_wd),
+    .we     (le_0_le_6_we),
+    .wd     (le_0_le_6_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1388,7 +1537,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[6].q ),
 
     // to register interface (read)
-    .qs     (le_le_6_qs)
+    .qs     (le_0_le_6_qs)
   );
 
 
@@ -1397,13 +1546,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_7 (
+  ) u_le_0_le_7 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_7_we),
-    .wd     (le_le_7_wd),
+    .we     (le_0_le_7_we),
+    .wd     (le_0_le_7_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1414,7 +1563,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[7].q ),
 
     // to register interface (read)
-    .qs     (le_le_7_qs)
+    .qs     (le_0_le_7_qs)
   );
 
 
@@ -1423,13 +1572,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_8 (
+  ) u_le_0_le_8 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_8_we),
-    .wd     (le_le_8_wd),
+    .we     (le_0_le_8_we),
+    .wd     (le_0_le_8_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1440,7 +1589,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[8].q ),
 
     // to register interface (read)
-    .qs     (le_le_8_qs)
+    .qs     (le_0_le_8_qs)
   );
 
 
@@ -1449,13 +1598,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_9 (
+  ) u_le_0_le_9 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_9_we),
-    .wd     (le_le_9_wd),
+    .we     (le_0_le_9_we),
+    .wd     (le_0_le_9_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1466,7 +1615,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[9].q ),
 
     // to register interface (read)
-    .qs     (le_le_9_qs)
+    .qs     (le_0_le_9_qs)
   );
 
 
@@ -1475,13 +1624,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_10 (
+  ) u_le_0_le_10 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_10_we),
-    .wd     (le_le_10_wd),
+    .we     (le_0_le_10_we),
+    .wd     (le_0_le_10_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1492,7 +1641,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[10].q ),
 
     // to register interface (read)
-    .qs     (le_le_10_qs)
+    .qs     (le_0_le_10_qs)
   );
 
 
@@ -1501,13 +1650,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_11 (
+  ) u_le_0_le_11 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_11_we),
-    .wd     (le_le_11_wd),
+    .we     (le_0_le_11_we),
+    .wd     (le_0_le_11_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1518,7 +1667,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[11].q ),
 
     // to register interface (read)
-    .qs     (le_le_11_qs)
+    .qs     (le_0_le_11_qs)
   );
 
 
@@ -1527,13 +1676,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_12 (
+  ) u_le_0_le_12 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_12_we),
-    .wd     (le_le_12_wd),
+    .we     (le_0_le_12_we),
+    .wd     (le_0_le_12_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1544,7 +1693,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[12].q ),
 
     // to register interface (read)
-    .qs     (le_le_12_qs)
+    .qs     (le_0_le_12_qs)
   );
 
 
@@ -1553,13 +1702,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_13 (
+  ) u_le_0_le_13 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_13_we),
-    .wd     (le_le_13_wd),
+    .we     (le_0_le_13_we),
+    .wd     (le_0_le_13_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1570,7 +1719,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[13].q ),
 
     // to register interface (read)
-    .qs     (le_le_13_qs)
+    .qs     (le_0_le_13_qs)
   );
 
 
@@ -1579,13 +1728,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_14 (
+  ) u_le_0_le_14 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_14_we),
-    .wd     (le_le_14_wd),
+    .we     (le_0_le_14_we),
+    .wd     (le_0_le_14_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1596,7 +1745,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[14].q ),
 
     // to register interface (read)
-    .qs     (le_le_14_qs)
+    .qs     (le_0_le_14_qs)
   );
 
 
@@ -1605,13 +1754,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_15 (
+  ) u_le_0_le_15 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_15_we),
-    .wd     (le_le_15_wd),
+    .we     (le_0_le_15_we),
+    .wd     (le_0_le_15_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1622,7 +1771,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[15].q ),
 
     // to register interface (read)
-    .qs     (le_le_15_qs)
+    .qs     (le_0_le_15_qs)
   );
 
 
@@ -1631,13 +1780,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_16 (
+  ) u_le_0_le_16 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_16_we),
-    .wd     (le_le_16_wd),
+    .we     (le_0_le_16_we),
+    .wd     (le_0_le_16_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1648,7 +1797,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[16].q ),
 
     // to register interface (read)
-    .qs     (le_le_16_qs)
+    .qs     (le_0_le_16_qs)
   );
 
 
@@ -1657,13 +1806,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_17 (
+  ) u_le_0_le_17 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_17_we),
-    .wd     (le_le_17_wd),
+    .we     (le_0_le_17_we),
+    .wd     (le_0_le_17_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1674,7 +1823,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[17].q ),
 
     // to register interface (read)
-    .qs     (le_le_17_qs)
+    .qs     (le_0_le_17_qs)
   );
 
 
@@ -1683,13 +1832,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_18 (
+  ) u_le_0_le_18 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_18_we),
-    .wd     (le_le_18_wd),
+    .we     (le_0_le_18_we),
+    .wd     (le_0_le_18_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1700,7 +1849,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[18].q ),
 
     // to register interface (read)
-    .qs     (le_le_18_qs)
+    .qs     (le_0_le_18_qs)
   );
 
 
@@ -1709,13 +1858,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_19 (
+  ) u_le_0_le_19 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_19_we),
-    .wd     (le_le_19_wd),
+    .we     (le_0_le_19_we),
+    .wd     (le_0_le_19_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1726,7 +1875,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[19].q ),
 
     // to register interface (read)
-    .qs     (le_le_19_qs)
+    .qs     (le_0_le_19_qs)
   );
 
 
@@ -1735,13 +1884,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_20 (
+  ) u_le_0_le_20 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_20_we),
-    .wd     (le_le_20_wd),
+    .we     (le_0_le_20_we),
+    .wd     (le_0_le_20_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1752,7 +1901,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[20].q ),
 
     // to register interface (read)
-    .qs     (le_le_20_qs)
+    .qs     (le_0_le_20_qs)
   );
 
 
@@ -1761,13 +1910,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_21 (
+  ) u_le_0_le_21 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_21_we),
-    .wd     (le_le_21_wd),
+    .we     (le_0_le_21_we),
+    .wd     (le_0_le_21_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1778,7 +1927,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[21].q ),
 
     // to register interface (read)
-    .qs     (le_le_21_qs)
+    .qs     (le_0_le_21_qs)
   );
 
 
@@ -1787,13 +1936,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_22 (
+  ) u_le_0_le_22 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_22_we),
-    .wd     (le_le_22_wd),
+    .we     (le_0_le_22_we),
+    .wd     (le_0_le_22_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1804,7 +1953,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[22].q ),
 
     // to register interface (read)
-    .qs     (le_le_22_qs)
+    .qs     (le_0_le_22_qs)
   );
 
 
@@ -1813,13 +1962,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_23 (
+  ) u_le_0_le_23 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_23_we),
-    .wd     (le_le_23_wd),
+    .we     (le_0_le_23_we),
+    .wd     (le_0_le_23_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1830,7 +1979,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[23].q ),
 
     // to register interface (read)
-    .qs     (le_le_23_qs)
+    .qs     (le_0_le_23_qs)
   );
 
 
@@ -1839,13 +1988,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_24 (
+  ) u_le_0_le_24 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_24_we),
-    .wd     (le_le_24_wd),
+    .we     (le_0_le_24_we),
+    .wd     (le_0_le_24_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1856,7 +2005,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[24].q ),
 
     // to register interface (read)
-    .qs     (le_le_24_qs)
+    .qs     (le_0_le_24_qs)
   );
 
 
@@ -1865,13 +2014,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_25 (
+  ) u_le_0_le_25 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_25_we),
-    .wd     (le_le_25_wd),
+    .we     (le_0_le_25_we),
+    .wd     (le_0_le_25_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1882,7 +2031,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[25].q ),
 
     // to register interface (read)
-    .qs     (le_le_25_qs)
+    .qs     (le_0_le_25_qs)
   );
 
 
@@ -1891,13 +2040,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_26 (
+  ) u_le_0_le_26 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_26_we),
-    .wd     (le_le_26_wd),
+    .we     (le_0_le_26_we),
+    .wd     (le_0_le_26_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1908,7 +2057,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[26].q ),
 
     // to register interface (read)
-    .qs     (le_le_26_qs)
+    .qs     (le_0_le_26_qs)
   );
 
 
@@ -1917,13 +2066,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_27 (
+  ) u_le_0_le_27 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_27_we),
-    .wd     (le_le_27_wd),
+    .we     (le_0_le_27_we),
+    .wd     (le_0_le_27_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1934,7 +2083,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[27].q ),
 
     // to register interface (read)
-    .qs     (le_le_27_qs)
+    .qs     (le_0_le_27_qs)
   );
 
 
@@ -1943,13 +2092,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_28 (
+  ) u_le_0_le_28 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_28_we),
-    .wd     (le_le_28_wd),
+    .we     (le_0_le_28_we),
+    .wd     (le_0_le_28_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1960,7 +2109,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[28].q ),
 
     // to register interface (read)
-    .qs     (le_le_28_qs)
+    .qs     (le_0_le_28_qs)
   );
 
 
@@ -1969,13 +2118,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_29 (
+  ) u_le_0_le_29 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_29_we),
-    .wd     (le_le_29_wd),
+    .we     (le_0_le_29_we),
+    .wd     (le_0_le_29_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1986,7 +2135,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[29].q ),
 
     // to register interface (read)
-    .qs     (le_le_29_qs)
+    .qs     (le_0_le_29_qs)
   );
 
 
@@ -1995,13 +2144,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_30 (
+  ) u_le_0_le_30 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_30_we),
-    .wd     (le_le_30_wd),
+    .we     (le_0_le_30_we),
+    .wd     (le_0_le_30_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -2012,7 +2161,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[30].q ),
 
     // to register interface (read)
-    .qs     (le_le_30_qs)
+    .qs     (le_0_le_30_qs)
   );
 
 
@@ -2021,13 +2170,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_le_le_31 (
+  ) u_le_0_le_31 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (le_le_31_we),
-    .wd     (le_le_31_wd),
+    .we     (le_0_le_31_we),
+    .wd     (le_0_le_31_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -2038,17 +2187,122 @@ module rv_plic_reg_top (
     .q      (reg2hw.le[31].q ),
 
     // to register interface (read)
-    .qs     (le_le_31_qs)
+    .qs     (le_0_le_31_qs)
   );
 
 
+  // Subregister 32 of Multireg le
+  // R[le_1]: V(False)
+
+  // F[le_32]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le_1_le_32 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le_1_le_32_we),
+    .wd     (le_1_le_32_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[32].q ),
+
+    // to register interface (read)
+    .qs     (le_1_le_32_qs)
+  );
+
+
+  // F[le_33]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le_1_le_33 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le_1_le_33_we),
+    .wd     (le_1_le_33_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[33].q ),
+
+    // to register interface (read)
+    .qs     (le_1_le_33_qs)
+  );
+
+
+  // F[le_34]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le_1_le_34 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le_1_le_34_we),
+    .wd     (le_1_le_34_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[34].q ),
+
+    // to register interface (read)
+    .qs     (le_1_le_34_qs)
+  );
+
+
+  // F[le_35]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le_1_le_35 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le_1_le_35_we),
+    .wd     (le_1_le_35_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[35].q ),
+
+    // to register interface (read)
+    .qs     (le_1_le_35_qs)
+  );
 
   // R[prio0]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio0 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2073,9 +2327,9 @@ module rv_plic_reg_top (
   // R[prio1]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio1 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2100,9 +2354,9 @@ module rv_plic_reg_top (
   // R[prio2]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio2 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2127,9 +2381,9 @@ module rv_plic_reg_top (
   // R[prio3]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio3 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2154,9 +2408,9 @@ module rv_plic_reg_top (
   // R[prio4]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio4 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2181,9 +2435,9 @@ module rv_plic_reg_top (
   // R[prio5]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio5 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2208,9 +2462,9 @@ module rv_plic_reg_top (
   // R[prio6]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio6 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2235,14 +2489,16 @@ module rv_plic_reg_top (
   // R[prio7]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio7 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
-    // from register interfaceqs;
+    // from register interface
+    .we     (prio7_we),
+    .wd     (prio7_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -2260,9 +2516,9 @@ module rv_plic_reg_top (
   // R[prio8]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio8 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2283,10 +2539,13 @@ module rv_plic_reg_top (
     .qs     (prio8_qs)
   );
 
+
+  // R[prio9]: V(False)
+
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio9 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2311,9 +2570,9 @@ module rv_plic_reg_top (
   // R[prio10]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio10 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2338,9 +2597,9 @@ module rv_plic_reg_top (
   // R[prio11]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio11 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2365,9 +2624,9 @@ module rv_plic_reg_top (
   // R[prio12]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio12 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2392,9 +2651,9 @@ module rv_plic_reg_top (
   // R[prio13]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio13 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2419,9 +2678,9 @@ module rv_plic_reg_top (
   // R[prio14]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio14 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2446,9 +2705,9 @@ module rv_plic_reg_top (
   // R[prio15]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio15 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2473,9 +2732,9 @@ module rv_plic_reg_top (
   // R[prio16]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio16 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2500,9 +2759,9 @@ module rv_plic_reg_top (
   // R[prio17]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio17 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2527,9 +2786,9 @@ module rv_plic_reg_top (
   // R[prio18]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio18 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2554,9 +2813,9 @@ module rv_plic_reg_top (
   // R[prio19]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio19 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2581,9 +2840,9 @@ module rv_plic_reg_top (
   // R[prio20]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio20 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2608,9 +2867,9 @@ module rv_plic_reg_top (
   // R[prio21]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio21 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2635,9 +2894,9 @@ module rv_plic_reg_top (
   // R[prio22]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio22 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2662,9 +2921,9 @@ module rv_plic_reg_top (
   // R[prio23]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio23 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2689,9 +2948,9 @@ module rv_plic_reg_top (
   // R[prio24]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio24 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2716,9 +2975,9 @@ module rv_plic_reg_top (
   // R[prio25]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio25 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2734,6 +2993,7 @@ module rv_plic_reg_top (
     // to internal hardware
     .qe     (),
     .q      (reg2hw.prio25.q ),
+
     // to register interface (read)
     .qs     (prio25_qs)
   );
@@ -2742,9 +3002,9 @@ module rv_plic_reg_top (
   // R[prio26]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio26 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2769,9 +3029,9 @@ module rv_plic_reg_top (
   // R[prio27]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio27 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2796,9 +3056,9 @@ module rv_plic_reg_top (
   // R[prio28]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio28 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2823,9 +3083,9 @@ module rv_plic_reg_top (
   // R[prio29]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio29 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2850,9 +3110,9 @@ module rv_plic_reg_top (
   // R[prio30]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio30 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2877,9 +3137,9 @@ module rv_plic_reg_top (
   // R[prio31]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_prio31 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -2901,22 +3161,128 @@ module rv_plic_reg_top (
   );
 
 
+  // R[prio32]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio32 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio32_we),
+    .wd     (prio32_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio32.q ),
+
+    // to register interface (read)
+    .qs     (prio32_qs)
+  );
+
+
+  // R[prio33]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio33 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio33_we),
+    .wd     (prio33_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio33.q ),
+
+    // to register interface (read)
+    .qs     (prio33_qs)
+  );
+
+
+  // R[prio34]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio34 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio34_we),
+    .wd     (prio34_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio34.q ),
+
+    // to register interface (read)
+    .qs     (prio34_qs)
+  );
+
+
+  // R[prio35]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio35 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio35_we),
+    .wd     (prio35_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio35.q ),
+
+    // to register interface (read)
+    .qs     (prio35_qs)
+  );
 
   // Subregister 0 of Multireg ie0
-  // R[ie0]: V(False)
+  // R[ie0_0]: V(False)
 
   // F[e_0]: 0:0
   prim_subreg #(
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_0 (
+  ) u_ie0_0_e_0 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_0_we),
-    .wd     (ie0_e_0_wd),
+    .we     (ie0_0_e_0_we),
+    .wd     (ie0_0_e_0_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -2927,7 +3293,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[0].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_0_qs)
+    .qs     (ie0_0_e_0_qs)
   );
 
 
@@ -2936,13 +3302,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_1 (
+  ) u_ie0_0_e_1 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_1_we),
-    .wd     (ie0_e_1_wd),
+    .we     (ie0_0_e_1_we),
+    .wd     (ie0_0_e_1_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -2953,7 +3319,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[1].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_1_qs)
+    .qs     (ie0_0_e_1_qs)
   );
 
 
@@ -2962,13 +3328,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_2 (
+  ) u_ie0_0_e_2 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_2_we),
-    .wd     (ie0_e_2_wd),
+    .we     (ie0_0_e_2_we),
+    .wd     (ie0_0_e_2_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -2979,7 +3345,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[2].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_2_qs)
+    .qs     (ie0_0_e_2_qs)
   );
 
 
@@ -2988,13 +3354,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_3 (
+  ) u_ie0_0_e_3 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_3_we),
-    .wd     (ie0_e_3_wd),
+    .we     (ie0_0_e_3_we),
+    .wd     (ie0_0_e_3_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3005,7 +3371,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[3].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_3_qs)
+    .qs     (ie0_0_e_3_qs)
   );
 
 
@@ -3014,13 +3380,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_4 (
+  ) u_ie0_0_e_4 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_4_we),
-    .wd     (ie0_e_4_wd),
+    .we     (ie0_0_e_4_we),
+    .wd     (ie0_0_e_4_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3031,7 +3397,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[4].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_4_qs)
+    .qs     (ie0_0_e_4_qs)
   );
 
 
@@ -3040,13 +3406,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_5 (
+  ) u_ie0_0_e_5 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_5_we),
-    .wd     (ie0_e_5_wd),
+    .we     (ie0_0_e_5_we),
+    .wd     (ie0_0_e_5_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3057,7 +3423,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[5].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_5_qs)
+    .qs     (ie0_0_e_5_qs)
   );
 
 
@@ -3066,13 +3432,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_6 (
+  ) u_ie0_0_e_6 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_6_we),
-    .wd     (ie0_e_6_wd),
+    .we     (ie0_0_e_6_we),
+    .wd     (ie0_0_e_6_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3083,7 +3449,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[6].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_6_qs)
+    .qs     (ie0_0_e_6_qs)
   );
 
 
@@ -3092,22 +3458,24 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_7 (
+  ) u_ie0_0_e_7 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_7_we),
-    .wd     (ie0_e_7_wd),
+    .we     (ie0_0_e_7_we),
+    .wd     (ie0_0_e_7_wd),
 
     // from internal hardware
     .de     (1'b0),
+    .d      ('0  ),
+
     // to internal hardware
     .qe     (),
     .q      (reg2hw.ie0[7].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_7_qs)
+    .qs     (ie0_0_e_7_qs)
   );
 
 
@@ -3116,13 +3484,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_8 (
+  ) u_ie0_0_e_8 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_8_we),
-    .wd     (ie0_e_8_wd),
+    .we     (ie0_0_e_8_we),
+    .wd     (ie0_0_e_8_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3133,7 +3501,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[8].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_8_qs)
+    .qs     (ie0_0_e_8_qs)
   );
 
 
@@ -3142,13 +3510,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_9 (
+  ) u_ie0_0_e_9 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_9_we),
-    .wd     (ie0_e_9_wd),
+    .we     (ie0_0_e_9_we),
+    .wd     (ie0_0_e_9_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3159,7 +3527,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[9].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_9_qs)
+    .qs     (ie0_0_e_9_qs)
   );
 
 
@@ -3168,13 +3536,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_10 (
+  ) u_ie0_0_e_10 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_10_we),
-    .wd     (ie0_e_10_wd),
+    .we     (ie0_0_e_10_we),
+    .wd     (ie0_0_e_10_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3185,7 +3553,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[10].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_10_qs)
+    .qs     (ie0_0_e_10_qs)
   );
 
 
@@ -3194,13 +3562,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_11 (
+  ) u_ie0_0_e_11 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_11_we),
-    .wd     (ie0_e_11_wd),
+    .we     (ie0_0_e_11_we),
+    .wd     (ie0_0_e_11_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3211,7 +3579,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[11].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_11_qs)
+    .qs     (ie0_0_e_11_qs)
   );
 
 
@@ -3220,13 +3588,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_12 (
+  ) u_ie0_0_e_12 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_12_we),
-    .wd     (ie0_e_12_wd),
+    .we     (ie0_0_e_12_we),
+    .wd     (ie0_0_e_12_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3237,7 +3605,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[12].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_12_qs)
+    .qs     (ie0_0_e_12_qs)
   );
 
 
@@ -3246,13 +3614,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_13 (
+  ) u_ie0_0_e_13 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_13_we),
-    .wd     (ie0_e_13_wd),
+    .we     (ie0_0_e_13_we),
+    .wd     (ie0_0_e_13_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3263,7 +3631,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[13].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_13_qs)
+    .qs     (ie0_0_e_13_qs)
   );
 
 
@@ -3272,13 +3640,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_14 (
+  ) u_ie0_0_e_14 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_14_we),
-    .wd     (ie0_e_14_wd),
+    .we     (ie0_0_e_14_we),
+    .wd     (ie0_0_e_14_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3289,7 +3657,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[14].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_14_qs)
+    .qs     (ie0_0_e_14_qs)
   );
 
 
@@ -3298,13 +3666,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_15 (
+  ) u_ie0_0_e_15 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_15_we),
-    .wd     (ie0_e_15_wd),
+    .we     (ie0_0_e_15_we),
+    .wd     (ie0_0_e_15_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3315,7 +3683,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[15].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_15_qs)
+    .qs     (ie0_0_e_15_qs)
   );
 
 
@@ -3324,13 +3692,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_16 (
+  ) u_ie0_0_e_16 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_16_we),
-    .wd     (ie0_e_16_wd),
+    .we     (ie0_0_e_16_we),
+    .wd     (ie0_0_e_16_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3341,7 +3709,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[16].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_16_qs)
+    .qs     (ie0_0_e_16_qs)
   );
 
 
@@ -3350,13 +3718,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_17 (
+  ) u_ie0_0_e_17 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_17_we),
-    .wd     (ie0_e_17_wd),
+    .we     (ie0_0_e_17_we),
+    .wd     (ie0_0_e_17_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3367,7 +3735,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[17].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_17_qs)
+    .qs     (ie0_0_e_17_qs)
   );
 
 
@@ -3376,13 +3744,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_18 (
+  ) u_ie0_0_e_18 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_18_we),
-    .wd     (ie0_e_18_wd),
+    .we     (ie0_0_e_18_we),
+    .wd     (ie0_0_e_18_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3393,7 +3761,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[18].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_18_qs)
+    .qs     (ie0_0_e_18_qs)
   );
 
 
@@ -3402,13 +3770,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_19 (
+  ) u_ie0_0_e_19 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_19_we),
-    .wd     (ie0_e_19_wd),
+    .we     (ie0_0_e_19_we),
+    .wd     (ie0_0_e_19_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3419,7 +3787,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[19].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_19_qs)
+    .qs     (ie0_0_e_19_qs)
   );
 
 
@@ -3428,13 +3796,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_20 (
+  ) u_ie0_0_e_20 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_20_we),
-    .wd     (ie0_e_20_wd),
+    .we     (ie0_0_e_20_we),
+    .wd     (ie0_0_e_20_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3445,7 +3813,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[20].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_20_qs)
+    .qs     (ie0_0_e_20_qs)
   );
 
 
@@ -3454,13 +3822,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_21 (
+  ) u_ie0_0_e_21 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_21_we),
-    .wd     (ie0_e_21_wd),
+    .we     (ie0_0_e_21_we),
+    .wd     (ie0_0_e_21_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3471,7 +3839,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[21].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_21_qs)
+    .qs     (ie0_0_e_21_qs)
   );
 
 
@@ -3480,13 +3848,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_22 (
+  ) u_ie0_0_e_22 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_22_we),
-    .wd     (ie0_e_22_wd),
+    .we     (ie0_0_e_22_we),
+    .wd     (ie0_0_e_22_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3497,7 +3865,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[22].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_22_qs)
+    .qs     (ie0_0_e_22_qs)
   );
 
 
@@ -3506,13 +3874,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_23 (
+  ) u_ie0_0_e_23 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_23_we),
-    .wd     (ie0_e_23_wd),
+    .we     (ie0_0_e_23_we),
+    .wd     (ie0_0_e_23_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3523,7 +3891,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[23].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_23_qs)
+    .qs     (ie0_0_e_23_qs)
   );
 
 
@@ -3532,13 +3900,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_24 (
+  ) u_ie0_0_e_24 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_24_we),
-    .wd     (ie0_e_24_wd),
+    .we     (ie0_0_e_24_we),
+    .wd     (ie0_0_e_24_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3549,7 +3917,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[24].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_24_qs)
+    .qs     (ie0_0_e_24_qs)
   );
 
 
@@ -3558,13 +3926,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_25 (
+  ) u_ie0_0_e_25 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_25_we),
-    .wd     (ie0_e_25_wd),
+    .we     (ie0_0_e_25_we),
+    .wd     (ie0_0_e_25_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3575,7 +3943,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[25].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_25_qs)
+    .qs     (ie0_0_e_25_qs)
   );
 
 
@@ -3584,24 +3952,24 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_26 (
+  ) u_ie0_0_e_26 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_26_we),
-    .wd     (ie0_e_26_wd),
+    .we     (ie0_0_e_26_we),
+    .wd     (ie0_0_e_26_wd),
 
     // from internal hardware
     .de     (1'b0),
     .d      ('0  ),
-        // to internal hardware
+
+    // to internal hardware
     .qe     (),
     .q      (reg2hw.ie0[26].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_26_qs)
-
+    .qs     (ie0_0_e_26_qs)
   );
 
 
@@ -3610,13 +3978,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_27 (
+  ) u_ie0_0_e_27 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_27_we),
-    .wd     (ie0_e_27_wd),
+    .we     (ie0_0_e_27_we),
+    .wd     (ie0_0_e_27_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3627,7 +3995,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[27].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_27_qs)
+    .qs     (ie0_0_e_27_qs)
   );
 
 
@@ -3636,13 +4004,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_28 (
+  ) u_ie0_0_e_28 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_28_we),
-    .wd     (ie0_e_28_wd),
+    .we     (ie0_0_e_28_we),
+    .wd     (ie0_0_e_28_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3653,7 +4021,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[28].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_28_qs)
+    .qs     (ie0_0_e_28_qs)
   );
 
 
@@ -3662,13 +4030,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_29 (
+  ) u_ie0_0_e_29 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_29_we),
-    .wd     (ie0_e_29_wd),
+    .we     (ie0_0_e_29_we),
+    .wd     (ie0_0_e_29_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3679,7 +4047,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[29].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_29_qs)
+    .qs     (ie0_0_e_29_qs)
   );
 
 
@@ -3688,13 +4056,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_30 (
-    .clk_i   (clk_i   ),
+  ) u_ie0_0_e_30 (
+    .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_30_we),
-    .wd     (ie0_e_30_wd),
+    .we     (ie0_0_e_30_we),
+    .wd     (ie0_0_e_30_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3705,7 +4073,7 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[30].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_30_qs)
+    .qs     (ie0_0_e_30_qs)
   );
 
 
@@ -3714,13 +4082,13 @@ module rv_plic_reg_top (
     .DW      (1),
     .SWACCESS("RW"),
     .RESVAL  (1'h0)
-  ) u_ie0_e_31 (
+  ) u_ie0_0_e_31 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
 
     // from register interface
-    .we     (ie0_e_31_we),
-    .wd     (ie0_e_31_wd),
+    .we     (ie0_0_e_31_we),
+    .wd     (ie0_0_e_31_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -3731,17 +4099,123 @@ module rv_plic_reg_top (
     .q      (reg2hw.ie0[31].q ),
 
     // to register interface (read)
-    .qs     (ie0_e_31_qs)
+    .qs     (ie0_0_e_31_qs)
+  );
+
+
+  // Subregister 32 of Multireg ie0
+  // R[ie0_1]: V(False)
+
+  // F[e_32]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie0_1_e_32 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie0_1_e_32_we),
+    .wd     (ie0_1_e_32_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[32].q ),
+
+    // to register interface (read)
+    .qs     (ie0_1_e_32_qs)
+  );
+
+
+  // F[e_33]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie0_1_e_33 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie0_1_e_33_we),
+    .wd     (ie0_1_e_33_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[33].q ),
+
+    // to register interface (read)
+    .qs     (ie0_1_e_33_qs)
   );
 
 
+  // F[e_34]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie0_1_e_34 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie0_1_e_34_we),
+    .wd     (ie0_1_e_34_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[34].q ),
+
+    // to register interface (read)
+    .qs     (ie0_1_e_34_qs)
+  );
+
+
+  // F[e_35]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie0_1_e_35 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie0_1_e_35_we),
+    .wd     (ie0_1_e_35_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[35].q ),
+
+    // to register interface (read)
+    .qs     (ie0_1_e_35_qs)
+  );
+
 
   // R[threshold0]: V(False)
 
   prim_subreg #(
-    .DW      (3),
+    .DW      (2),
     .SWACCESS("RW"),
-    .RESVAL  (3'h0)
+    .RESVAL  (2'h0)
   ) u_threshold0 (
     .clk_i   (clk_i    ),
     .rst_ni  (rst_ni  ),
@@ -3808,47 +4282,54 @@ module rv_plic_reg_top (
 
 
 
-  logic [37:0] addr_hit;
+  logic [44:0] addr_hit;
   always_comb begin
     addr_hit = '0;
-    addr_hit[ 0] = (reg_addr == RV_PLIC_IP_OFFSET);
-    addr_hit[ 1] = (reg_addr == RV_PLIC_LE_OFFSET);
-    addr_hit[ 2] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
-    addr_hit[ 3] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
-    addr_hit[ 4] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
-    addr_hit[ 5] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
-    addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
-    addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
-    addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
-    addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
-    addr_hit[10] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
-    addr_hit[11] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
-    addr_hit[12] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
-    addr_hit[13] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
-    addr_hit[14] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
-    addr_hit[15] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
-    addr_hit[16] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
-    addr_hit[17] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
-    addr_hit[18] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
-    addr_hit[19] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
-    addr_hit[20] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
-    addr_hit[21] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
-    addr_hit[22] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
-    addr_hit[23] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
-    addr_hit[24] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
-    addr_hit[25] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
-    addr_hit[26] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
-    addr_hit[27] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
-    addr_hit[28] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
-    addr_hit[29] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
-    addr_hit[30] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
-    addr_hit[31] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
-    addr_hit[32] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
-    addr_hit[33] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
-    addr_hit[34] = (reg_addr == RV_PLIC_IE0_OFFSET);
-    addr_hit[35] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
-    addr_hit[36] = (reg_addr == RV_PLIC_CC0_OFFSET);
-    addr_hit[37] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
+    addr_hit[  0] = (reg_addr == RV_PLIC_IP_0_OFFSET);
+    addr_hit[  1] = (reg_addr == RV_PLIC_IP_1_OFFSET);
+    addr_hit[  2] = (reg_addr == RV_PLIC_LE_0_OFFSET);
+    addr_hit[  3] = (reg_addr == RV_PLIC_LE_1_OFFSET);
+    addr_hit[  4] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
+    addr_hit[  5] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
+    addr_hit[  6] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
+    addr_hit[  7] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
+    addr_hit[  8] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
+    addr_hit[  9] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
+    addr_hit[ 10] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
+    addr_hit[ 11] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
+    addr_hit[ 12] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
+    addr_hit[ 13] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
+    addr_hit[ 14] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
+    addr_hit[ 15] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
+    addr_hit[ 16] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
+    addr_hit[ 17] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
+    addr_hit[ 18] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
+    addr_hit[ 19] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
+    addr_hit[ 20] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
+    addr_hit[ 21] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
+    addr_hit[ 22] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
+    addr_hit[ 23] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
+    addr_hit[ 24] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
+    addr_hit[ 25] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
+    addr_hit[ 26] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
+    addr_hit[ 27] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
+    addr_hit[ 28] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
+    addr_hit[ 29] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
+    addr_hit[ 30] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
+    addr_hit[ 31] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
+    addr_hit[ 32] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
+    addr_hit[ 33] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
+    addr_hit[ 34] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
+    addr_hit[ 35] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
+    addr_hit[ 36] = (reg_addr == RV_PLIC_PRIO32_OFFSET);
+    addr_hit[ 37] = (reg_addr == RV_PLIC_PRIO33_OFFSET);
+    addr_hit[ 38] = (reg_addr == RV_PLIC_PRIO34_OFFSET);
+    addr_hit[ 39] = (reg_addr == RV_PLIC_PRIO35_OFFSET);
+    addr_hit[ 40] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
+    addr_hit[ 41] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
+    addr_hit[ 42] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
+    addr_hit[ 43] = (reg_addr == RV_PLIC_CC0_OFFSET);
+    addr_hit[ 44] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -3856,44 +4337,51 @@ module rv_plic_reg_top (
   // Check sub-word write is permitted
   always_comb begin
     wr_err = 1'b0;
-    if (addr_hit[ 0] && reg_we && (RV_PLIC_PERMIT[ 0] != (RV_PLIC_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 1] && reg_we && (RV_PLIC_PERMIT[ 1] != (RV_PLIC_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 2] && reg_we && (RV_PLIC_PERMIT[ 2] != (RV_PLIC_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 3] && reg_we && (RV_PLIC_PERMIT[ 3] != (RV_PLIC_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 4] && reg_we && (RV_PLIC_PERMIT[ 4] != (RV_PLIC_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 5] && reg_we && (RV_PLIC_PERMIT[ 5] != (RV_PLIC_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 6] && reg_we && (RV_PLIC_PERMIT[ 6] != (RV_PLIC_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 7] && reg_we && (RV_PLIC_PERMIT[ 7] != (RV_PLIC_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 8] && reg_we && (RV_PLIC_PERMIT[ 8] != (RV_PLIC_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 9] && reg_we && (RV_PLIC_PERMIT[ 9] != (RV_PLIC_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[10] && reg_we && (RV_PLIC_PERMIT[10] != (RV_PLIC_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[11] && reg_we && (RV_PLIC_PERMIT[11] != (RV_PLIC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[12] && reg_we && (RV_PLIC_PERMIT[12] != (RV_PLIC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[13] && reg_we && (RV_PLIC_PERMIT[13] != (RV_PLIC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[14] && reg_we && (RV_PLIC_PERMIT[14] != (RV_PLIC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[15] && reg_we && (RV_PLIC_PERMIT[15] != (RV_PLIC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[16] && reg_we && (RV_PLIC_PERMIT[16] != (RV_PLIC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[17] && reg_we && (RV_PLIC_PERMIT[17] != (RV_PLIC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[18] && reg_we && (RV_PLIC_PERMIT[18] != (RV_PLIC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[19] && reg_we && (RV_PLIC_PERMIT[19] != (RV_PLIC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[20] && reg_we && (RV_PLIC_PERMIT[20] != (RV_PLIC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[21] && reg_we && (RV_PLIC_PERMIT[21] != (RV_PLIC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[22] && reg_we && (RV_PLIC_PERMIT[22] != (RV_PLIC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[23] && reg_we && (RV_PLIC_PERMIT[23] != (RV_PLIC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[24] && reg_we && (RV_PLIC_PERMIT[24] != (RV_PLIC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[25] && reg_we && (RV_PLIC_PERMIT[25] != (RV_PLIC_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[26] && reg_we && (RV_PLIC_PERMIT[26] != (RV_PLIC_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[27] && reg_we && (RV_PLIC_PERMIT[27] != (RV_PLIC_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[28] && reg_we && (RV_PLIC_PERMIT[28] != (RV_PLIC_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[29] && reg_we && (RV_PLIC_PERMIT[29] != (RV_PLIC_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[30] && reg_we && (RV_PLIC_PERMIT[30] != (RV_PLIC_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[31] && reg_we && (RV_PLIC_PERMIT[31] != (RV_PLIC_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[32] && reg_we && (RV_PLIC_PERMIT[32] != (RV_PLIC_PERMIT[32] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[33] && reg_we && (RV_PLIC_PERMIT[33] != (RV_PLIC_PERMIT[33] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[34] && reg_we && (RV_PLIC_PERMIT[34] != (RV_PLIC_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[35] && reg_we && (RV_PLIC_PERMIT[35] != (RV_PLIC_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[36] && reg_we && (RV_PLIC_PERMIT[36] != (RV_PLIC_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[37] && reg_we && (RV_PLIC_PERMIT[37] != (RV_PLIC_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[  0] && reg_we && (RV_PLIC_PERMIT[  0] != (RV_PLIC_PERMIT[  0] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[  1] && reg_we && (RV_PLIC_PERMIT[  1] != (RV_PLIC_PERMIT[  1] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[  2] && reg_we && (RV_PLIC_PERMIT[  2] != (RV_PLIC_PERMIT[  2] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[  3] && reg_we && (RV_PLIC_PERMIT[  3] != (RV_PLIC_PERMIT[  3] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[  4] && reg_we && (RV_PLIC_PERMIT[  4] != (RV_PLIC_PERMIT[  4] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[  5] && reg_we && (RV_PLIC_PERMIT[  5] != (RV_PLIC_PERMIT[  5] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[  6] && reg_we && (RV_PLIC_PERMIT[  6] != (RV_PLIC_PERMIT[  6] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[  7] && reg_we && (RV_PLIC_PERMIT[  7] != (RV_PLIC_PERMIT[  7] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[  8] && reg_we && (RV_PLIC_PERMIT[  8] != (RV_PLIC_PERMIT[  8] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[  9] && reg_we && (RV_PLIC_PERMIT[  9] != (RV_PLIC_PERMIT[  9] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 10] && reg_we && (RV_PLIC_PERMIT[ 10] != (RV_PLIC_PERMIT[ 10] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 11] && reg_we && (RV_PLIC_PERMIT[ 11] != (RV_PLIC_PERMIT[ 11] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 12] && reg_we && (RV_PLIC_PERMIT[ 12] != (RV_PLIC_PERMIT[ 12] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 13] && reg_we && (RV_PLIC_PERMIT[ 13] != (RV_PLIC_PERMIT[ 13] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 14] && reg_we && (RV_PLIC_PERMIT[ 14] != (RV_PLIC_PERMIT[ 14] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 15] && reg_we && (RV_PLIC_PERMIT[ 15] != (RV_PLIC_PERMIT[ 15] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 16] && reg_we && (RV_PLIC_PERMIT[ 16] != (RV_PLIC_PERMIT[ 16] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 17] && reg_we && (RV_PLIC_PERMIT[ 17] != (RV_PLIC_PERMIT[ 17] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 18] && reg_we && (RV_PLIC_PERMIT[ 18] != (RV_PLIC_PERMIT[ 18] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 19] && reg_we && (RV_PLIC_PERMIT[ 19] != (RV_PLIC_PERMIT[ 19] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 20] && reg_we && (RV_PLIC_PERMIT[ 20] != (RV_PLIC_PERMIT[ 20] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 21] && reg_we && (RV_PLIC_PERMIT[ 21] != (RV_PLIC_PERMIT[ 21] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 22] && reg_we && (RV_PLIC_PERMIT[ 22] != (RV_PLIC_PERMIT[ 22] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 23] && reg_we && (RV_PLIC_PERMIT[ 23] != (RV_PLIC_PERMIT[ 23] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 24] && reg_we && (RV_PLIC_PERMIT[ 24] != (RV_PLIC_PERMIT[ 24] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 25] && reg_we && (RV_PLIC_PERMIT[ 25] != (RV_PLIC_PERMIT[ 25] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 26] && reg_we && (RV_PLIC_PERMIT[ 26] != (RV_PLIC_PERMIT[ 26] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 27] && reg_we && (RV_PLIC_PERMIT[ 27] != (RV_PLIC_PERMIT[ 27] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 28] && reg_we && (RV_PLIC_PERMIT[ 28] != (RV_PLIC_PERMIT[ 28] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 29] && reg_we && (RV_PLIC_PERMIT[ 29] != (RV_PLIC_PERMIT[ 29] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 30] && reg_we && (RV_PLIC_PERMIT[ 30] != (RV_PLIC_PERMIT[ 30] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 31] && reg_we && (RV_PLIC_PERMIT[ 31] != (RV_PLIC_PERMIT[ 31] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 32] && reg_we && (RV_PLIC_PERMIT[ 32] != (RV_PLIC_PERMIT[ 32] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 33] && reg_we && (RV_PLIC_PERMIT[ 33] != (RV_PLIC_PERMIT[ 33] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 34] && reg_we && (RV_PLIC_PERMIT[ 34] != (RV_PLIC_PERMIT[ 34] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 35] && reg_we && (RV_PLIC_PERMIT[ 35] != (RV_PLIC_PERMIT[ 35] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 36] && reg_we && (RV_PLIC_PERMIT[ 36] != (RV_PLIC_PERMIT[ 36] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 37] && reg_we && (RV_PLIC_PERMIT[ 37] != (RV_PLIC_PERMIT[ 37] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 38] && reg_we && (RV_PLIC_PERMIT[ 38] != (RV_PLIC_PERMIT[ 38] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 39] && reg_we && (RV_PLIC_PERMIT[ 39] != (RV_PLIC_PERMIT[ 39] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 40] && reg_we && (RV_PLIC_PERMIT[ 40] != (RV_PLIC_PERMIT[ 40] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 41] && reg_we && (RV_PLIC_PERMIT[ 41] != (RV_PLIC_PERMIT[ 41] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 42] && reg_we && (RV_PLIC_PERMIT[ 42] != (RV_PLIC_PERMIT[ 42] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 43] && reg_we && (RV_PLIC_PERMIT[ 43] != (RV_PLIC_PERMIT[ 43] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 44] && reg_we && (RV_PLIC_PERMIT[ 44] != (RV_PLIC_PERMIT[ 44] & reg_be))) wr_err = 1'b1 ;
   end
 
 
@@ -3901,329 +4389,338 @@ module rv_plic_reg_top (
 
 
 
+  assign le_0_le_0_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_0_wd = reg_wdata[0];
 
+  assign le_0_le_1_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_1_wd = reg_wdata[1];
 
+  assign le_0_le_2_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_2_wd = reg_wdata[2];
 
+  assign le_0_le_3_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_3_wd = reg_wdata[3];
 
+  assign le_0_le_4_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_4_wd = reg_wdata[4];
 
+  assign le_0_le_5_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_5_wd = reg_wdata[5];
 
+  assign le_0_le_6_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_6_wd = reg_wdata[6];
 
+  assign le_0_le_7_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_7_wd = reg_wdata[7];
 
+  assign le_0_le_8_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_8_wd = reg_wdata[8];
 
+  assign le_0_le_9_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_9_wd = reg_wdata[9];
 
+  assign le_0_le_10_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_10_wd = reg_wdata[10];
 
+  assign le_0_le_11_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_11_wd = reg_wdata[11];
 
+  assign le_0_le_12_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_12_wd = reg_wdata[12];
 
+  assign le_0_le_13_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_13_wd = reg_wdata[13];
 
+  assign le_0_le_14_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_14_wd = reg_wdata[14];
 
+  assign le_0_le_15_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_15_wd = reg_wdata[15];
 
+  assign le_0_le_16_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_16_wd = reg_wdata[16];
 
+  assign le_0_le_17_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_17_wd = reg_wdata[17];
 
+  assign le_0_le_18_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_18_wd = reg_wdata[18];
 
+  assign le_0_le_19_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_19_wd = reg_wdata[19];
 
+  assign le_0_le_20_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_20_wd = reg_wdata[20];
 
+  assign le_0_le_21_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_21_wd = reg_wdata[21];
 
+  assign le_0_le_22_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_22_wd = reg_wdata[22];
 
+  assign le_0_le_23_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_23_wd = reg_wdata[23];
 
+  assign le_0_le_24_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_24_wd = reg_wdata[24];
 
+  assign le_0_le_25_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_25_wd = reg_wdata[25];
 
+  assign le_0_le_26_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_26_wd = reg_wdata[26];
 
-  assign le_le_0_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_0_wd = reg_wdata[0];
-
-  assign le_le_1_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_1_wd = reg_wdata[1];
-
-  assign le_le_2_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_2_wd = reg_wdata[2];
-
-  assign le_le_3_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_3_wd = reg_wdata[3];
-
-  assign le_le_4_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_4_wd = reg_wdata[4];
-
-  assign le_le_5_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_5_wd = reg_wdata[5];
-
-  assign le_le_6_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_6_wd = reg_wdata[6];
-
-  assign le_le_7_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_7_wd = reg_wdata[7];
-
-  assign le_le_8_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_8_wd = reg_wdata[8];
-
-  assign le_le_9_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_9_wd = reg_wdata[9];
-
-  assign le_le_10_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_10_wd = reg_wdata[10];
-
-  assign le_le_11_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_11_wd = reg_wdata[11];
-
-  assign le_le_12_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_12_wd = reg_wdata[12];
-
-  assign le_le_13_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_13_wd = reg_wdata[13];
+  assign le_0_le_27_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_27_wd = reg_wdata[27];
 
-  assign le_le_14_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_14_wd = reg_wdata[14];
+  assign le_0_le_28_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_28_wd = reg_wdata[28];
 
-  assign le_le_15_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_15_wd = reg_wdata[15];
+  assign le_0_le_29_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_29_wd = reg_wdata[29];
 
-  assign le_le_16_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_16_wd = reg_wdata[16];
+  assign le_0_le_30_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_30_wd = reg_wdata[30];
 
-  assign le_le_17_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_17_wd = reg_wdata[17];
+  assign le_0_le_31_we = addr_hit[2] & reg_we & ~wr_err;
+  assign le_0_le_31_wd = reg_wdata[31];
 
-  assign le_le_18_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_18_wd = reg_wdata[18];
+  assign le_1_le_32_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le_1_le_32_wd = reg_wdata[0];
 
-  assign le_le_19_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_19_wd = reg_wdata[19];
+  assign le_1_le_33_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le_1_le_33_wd = reg_wdata[1];
 
-  assign le_le_20_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_20_wd = reg_wdata[20];
+  assign le_1_le_34_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le_1_le_34_wd = reg_wdata[2];
 
-  assign le_le_21_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_21_wd = reg_wdata[21];
+  assign le_1_le_35_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le_1_le_35_wd = reg_wdata[3];
 
-  assign le_le_22_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_22_wd = reg_wdata[22];
+  assign prio0_we = addr_hit[4] & reg_we & ~wr_err;
+  assign prio0_wd = reg_wdata[1:0];
 
-  assign le_le_23_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_23_wd = reg_wdata[23];
+  assign prio1_we = addr_hit[5] & reg_we & ~wr_err;
+  assign prio1_wd = reg_wdata[1:0];
 
-  assign le_le_24_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_24_wd = reg_wdata[24];
+  assign prio2_we = addr_hit[6] & reg_we & ~wr_err;
+  assign prio2_wd = reg_wdata[1:0];
 
-  assign le_le_25_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_25_wd = reg_wdata[25];
+  assign prio3_we = addr_hit[7] & reg_we & ~wr_err;
+  assign prio3_wd = reg_wdata[1:0];
 
-  assign le_le_26_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_26_wd = reg_wdata[26];
+  assign prio4_we = addr_hit[8] & reg_we & ~wr_err;
+  assign prio4_wd = reg_wdata[1:0];
 
-  assign le_le_27_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_27_wd = reg_wdata[27];
+  assign prio5_we = addr_hit[9] & reg_we & ~wr_err;
+  assign prio5_wd = reg_wdata[1:0];
 
-  assign le_le_28_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_28_wd = reg_wdata[28];
+  assign prio6_we = addr_hit[10] & reg_we & ~wr_err;
+  assign prio6_wd = reg_wdata[1:0];
 
-  assign le_le_29_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_29_wd = reg_wdata[29];
+  assign prio7_we = addr_hit[11] & reg_we & ~wr_err;
+  assign prio7_wd = reg_wdata[1:0];
 
-  assign le_le_30_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_30_wd = reg_wdata[30];
+  assign prio8_we = addr_hit[12] & reg_we & ~wr_err;
+  assign prio8_wd = reg_wdata[1:0];
 
-  assign le_le_31_we = addr_hit[1] & reg_we & ~wr_err;
-  assign le_le_31_wd = reg_wdata[31];
+  assign prio9_we = addr_hit[13] & reg_we & ~wr_err;
+  assign prio9_wd = reg_wdata[1:0];
 
-  assign prio0_we = addr_hit[2] & reg_we & ~wr_err;
-  assign prio0_wd = reg_wdata[2:0];
+  assign prio10_we = addr_hit[14] & reg_we & ~wr_err;
+  assign prio10_wd = reg_wdata[1:0];
 
-  assign prio1_we = addr_hit[3] & reg_we & ~wr_err;
-  assign prio1_wd = reg_wdata[2:0];
+  assign prio11_we = addr_hit[15] & reg_we & ~wr_err;
+  assign prio11_wd = reg_wdata[1:0];
 
-  assign prio2_we = addr_hit[4] & reg_we & ~wr_err;
-  assign prio2_wd = reg_wdata[2:0];
+  assign prio12_we = addr_hit[16] & reg_we & ~wr_err;
+  assign prio12_wd = reg_wdata[1:0];
 
-  assign prio3_we = addr_hit[5] & reg_we & ~wr_err;
-  assign prio3_wd = reg_wdata[2:0];
+  assign prio13_we = addr_hit[17] & reg_we & ~wr_err;
+  assign prio13_wd = reg_wdata[1:0];
 
-  assign prio4_we = addr_hit[6] & reg_we & ~wr_err;
-  assign prio4_wd = reg_wdata[2:0];
+  assign prio14_we = addr_hit[18] & reg_we & ~wr_err;
+  assign prio14_wd = reg_wdata[1:0];
 
-  assign prio5_we = addr_hit[7] & reg_we & ~wr_err;
-  assign prio5_wd = reg_wdata[2:0];
+  assign prio15_we = addr_hit[19] & reg_we & ~wr_err;
+  assign prio15_wd = reg_wdata[1:0];
 
-  assign prio6_we = addr_hit[8] & reg_we & ~wr_err;
-  assign prio6_wd = reg_wdata[2:0];
+  assign prio16_we = addr_hit[20] & reg_we & ~wr_err;
+  assign prio16_wd = reg_wdata[1:0];
 
-  assign prio7_we = addr_hit[9] & reg_we & ~wr_err;
-  assign prio7_wd = reg_wdata[2:0];
+  assign prio17_we = addr_hit[21] & reg_we & ~wr_err;
+  assign prio17_wd = reg_wdata[1:0];
 
-  assign prio8_we = addr_hit[10] & reg_we & ~wr_err;
-  assign prio8_wd = reg_wdata[2:0];
+  assign prio18_we = addr_hit[22] & reg_we & ~wr_err;
+  assign prio18_wd = reg_wdata[1:0];
 
-  assign prio9_we = addr_hit[11] & reg_we & ~wr_err;
-  assign prio9_wd = reg_wdata[2:0];
+  assign prio19_we = addr_hit[23] & reg_we & ~wr_err;
+  assign prio19_wd = reg_wdata[1:0];
 
-  assign prio10_we = addr_hit[12] & reg_we & ~wr_err;
-  assign prio10_wd = reg_wdata[2:0];
+  assign prio20_we = addr_hit[24] & reg_we & ~wr_err;
+  assign prio20_wd = reg_wdata[1:0];
 
-  assign prio11_we = addr_hit[13] & reg_we & ~wr_err;
-  assign prio11_wd = reg_wdata[2:0];
+  assign prio21_we = addr_hit[25] & reg_we & ~wr_err;
+  assign prio21_wd = reg_wdata[1:0];
 
-  assign prio12_we = addr_hit[14] & reg_we & ~wr_err;
-  assign prio12_wd = reg_wdata[2:0];
+  assign prio22_we = addr_hit[26] & reg_we & ~wr_err;
+  assign prio22_wd = reg_wdata[1:0];
 
-  assign prio13_we = addr_hit[15] & reg_we & ~wr_err;
-  assign prio13_wd = reg_wdata[2:0];
+  assign prio23_we = addr_hit[27] & reg_we & ~wr_err;
+  assign prio23_wd = reg_wdata[1:0];
 
-  assign prio14_we = addr_hit[16] & reg_we & ~wr_err;
-  assign prio14_wd = reg_wdata[2:0];
+  assign prio24_we = addr_hit[28] & reg_we & ~wr_err;
+  assign prio24_wd = reg_wdata[1:0];
 
-  assign prio15_we = addr_hit[17] & reg_we & ~wr_err;
-  assign prio15_wd = reg_wdata[2:0];
+  assign prio25_we = addr_hit[29] & reg_we & ~wr_err;
+  assign prio25_wd = reg_wdata[1:0];
 
-  assign prio16_we = addr_hit[18] & reg_we & ~wr_err;
-  assign prio16_wd = reg_wdata[2:0];
+  assign prio26_we = addr_hit[30] & reg_we & ~wr_err;
+  assign prio26_wd = reg_wdata[1:0];
 
-  assign prio17_we = addr_hit[19] & reg_we & ~wr_err;
-  assign prio17_wd = reg_wdata[2:0];
+  assign prio27_we = addr_hit[31] & reg_we & ~wr_err;
+  assign prio27_wd = reg_wdata[1:0];
 
-  assign prio18_we = addr_hit[20] & reg_we & ~wr_err;
-  assign prio18_wd = reg_wdata[2:0];
+  assign prio28_we = addr_hit[32] & reg_we & ~wr_err;
+  assign prio28_wd = reg_wdata[1:0];
 
-  assign prio19_we = addr_hit[21] & reg_we & ~wr_err;
-  assign prio19_wd = reg_wdata[2:0];
+  assign prio29_we = addr_hit[33] & reg_we & ~wr_err;
+  assign prio29_wd = reg_wdata[1:0];
 
-  assign prio20_we = addr_hit[22] & reg_we & ~wr_err;
-  assign prio20_wd = reg_wdata[2:0];
+  assign prio30_we = addr_hit[34] & reg_we & ~wr_err;
+  assign prio30_wd = reg_wdata[1:0];
 
-  assign prio21_we = addr_hit[23] & reg_we & ~wr_err;
-  assign prio21_wd = reg_wdata[2:0];
+  assign prio31_we = addr_hit[35] & reg_we & ~wr_err;
+  assign prio31_wd = reg_wdata[1:0];
 
-  assign prio22_we = addr_hit[24] & reg_we & ~wr_err;
-  assign prio22_wd = reg_wdata[2:0];
+  assign prio32_we = addr_hit[36] & reg_we & ~wr_err;
+  assign prio32_wd = reg_wdata[1:0];
 
-  assign prio23_we = addr_hit[25] & reg_we & ~wr_err;
-  assign prio23_wd = reg_wdata[2:0];
+  assign prio33_we = addr_hit[37] & reg_we & ~wr_err;
+  assign prio33_wd = reg_wdata[1:0];
 
-  assign prio24_we = addr_hit[26] & reg_we & ~wr_err;
-  assign prio24_wd = reg_wdata[2:0];
+  assign prio34_we = addr_hit[38] & reg_we & ~wr_err;
+  assign prio34_wd = reg_wdata[1:0];
 
-  assign prio25_we = addr_hit[27] & reg_we & ~wr_err;
-  assign prio25_wd = reg_wdata[2:0];
+  assign prio35_we = addr_hit[39] & reg_we & ~wr_err;
+  assign prio35_wd = reg_wdata[1:0];
 
-  assign prio26_we = addr_hit[28] & reg_we & ~wr_err;
-  assign prio26_wd = reg_wdata[2:0];
+  assign ie0_0_e_0_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_0_wd = reg_wdata[0];
 
-  assign prio27_we = addr_hit[29] & reg_we & ~wr_err;
-  assign prio27_wd = reg_wdata[2:0];
+  assign ie0_0_e_1_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_1_wd = reg_wdata[1];
 
-  assign prio28_we = addr_hit[30] & reg_we & ~wr_err;
-  assign prio28_wd = reg_wdata[2:0];
+  assign ie0_0_e_2_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_2_wd = reg_wdata[2];
 
-  assign prio29_we = addr_hit[31] & reg_we & ~wr_err;
-  assign prio29_wd = reg_wdata[2:0];
+  assign ie0_0_e_3_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_3_wd = reg_wdata[3];
 
-  assign prio30_we = addr_hit[32] & reg_we & ~wr_err;
-  assign prio30_wd = reg_wdata[2:0];
+  assign ie0_0_e_4_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_4_wd = reg_wdata[4];
 
-  assign prio31_we = addr_hit[33] & reg_we & ~wr_err;
-  assign prio31_wd = reg_wdata[2:0];
+  assign ie0_0_e_5_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_5_wd = reg_wdata[5];
 
-  assign ie0_e_0_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_0_wd = reg_wdata[0];
+  assign ie0_0_e_6_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_6_wd = reg_wdata[6];
 
-  assign ie0_e_1_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_1_wd = reg_wdata[1];
+  assign ie0_0_e_7_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_7_wd = reg_wdata[7];
 
-  assign ie0_e_2_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_2_wd = reg_wdata[2];
+  assign ie0_0_e_8_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_8_wd = reg_wdata[8];
 
-  assign ie0_e_3_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_3_wd = reg_wdata[3];
+  assign ie0_0_e_9_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_9_wd = reg_wdata[9];
 
-  assign ie0_e_4_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_4_wd = reg_wdata[4];
+  assign ie0_0_e_10_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_10_wd = reg_wdata[10];
 
-  assign ie0_e_5_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_5_wd = reg_wdata[5];
+  assign ie0_0_e_11_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_11_wd = reg_wdata[11];
 
-  assign ie0_e_6_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_6_wd = reg_wdata[6];
+  assign ie0_0_e_12_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_12_wd = reg_wdata[12];
 
-  assign ie0_e_7_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_7_wd = reg_wdata[7];
+  assign ie0_0_e_13_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_13_wd = reg_wdata[13];
 
-  assign ie0_e_8_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_8_wd = reg_wdata[8];
+  assign ie0_0_e_14_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_14_wd = reg_wdata[14];
 
-  assign ie0_e_9_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_9_wd = reg_wdata[9];
+  assign ie0_0_e_15_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_15_wd = reg_wdata[15];
 
-  assign ie0_e_10_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_10_wd = reg_wdata[10];
+  assign ie0_0_e_16_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_16_wd = reg_wdata[16];
 
-  assign ie0_e_11_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_11_wd = reg_wdata[11];
+  assign ie0_0_e_17_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_17_wd = reg_wdata[17];
 
-  assign ie0_e_12_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_12_wd = reg_wdata[12];
+  assign ie0_0_e_18_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_18_wd = reg_wdata[18];
 
-  assign ie0_e_13_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_13_wd = reg_wdata[13];
+  assign ie0_0_e_19_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_19_wd = reg_wdata[19];
 
-  assign ie0_e_14_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_14_wd = reg_wdata[14];
+  assign ie0_0_e_20_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_20_wd = reg_wdata[20];
 
-  assign ie0_e_15_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_15_wd = reg_wdata[15];
+  assign ie0_0_e_21_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_21_wd = reg_wdata[21];
 
-  assign ie0_e_16_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_16_wd = reg_wdata[16];
+  assign ie0_0_e_22_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_22_wd = reg_wdata[22];
 
-  assign ie0_e_17_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_17_wd = reg_wdata[17];
+  assign ie0_0_e_23_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_23_wd = reg_wdata[23];
 
-  assign ie0_e_18_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_18_wd = reg_wdata[18];
+  assign ie0_0_e_24_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_24_wd = reg_wdata[24];
 
-  assign ie0_e_19_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_19_wd = reg_wdata[19];
+  assign ie0_0_e_25_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_25_wd = reg_wdata[25];
 
-  assign ie0_e_20_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_20_wd = reg_wdata[20];
+  assign ie0_0_e_26_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_26_wd = reg_wdata[26];
 
-  assign ie0_e_21_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_21_wd = reg_wdata[21];
+  assign ie0_0_e_27_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_27_wd = reg_wdata[27];
 
-  assign ie0_e_22_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_22_wd = reg_wdata[22];
+  assign ie0_0_e_28_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_28_wd = reg_wdata[28];
 
-  assign ie0_e_23_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_23_wd = reg_wdata[23];
+  assign ie0_0_e_29_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_29_wd = reg_wdata[29];
 
-  assign ie0_e_24_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_24_wd = reg_wdata[24];
+  assign ie0_0_e_30_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_30_wd = reg_wdata[30];
 
-  assign ie0_e_25_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_25_wd = reg_wdata[25];
+  assign ie0_0_e_31_we = addr_hit[40] & reg_we & ~wr_err;
+  assign ie0_0_e_31_wd = reg_wdata[31];
 
-  assign ie0_e_26_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_26_wd = reg_wdata[26];
+  assign ie0_1_e_32_we = addr_hit[41] & reg_we & ~wr_err;
+  assign ie0_1_e_32_wd = reg_wdata[0];
 
-  assign ie0_e_27_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_27_wd = reg_wdata[27];
+  assign ie0_1_e_33_we = addr_hit[41] & reg_we & ~wr_err;
+  assign ie0_1_e_33_wd = reg_wdata[1];
 
-  assign ie0_e_28_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_28_wd = reg_wdata[28];
+  assign ie0_1_e_34_we = addr_hit[41] & reg_we & ~wr_err;
+  assign ie0_1_e_34_wd = reg_wdata[2];
 
-  assign ie0_e_29_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_29_wd = reg_wdata[29];
+  assign ie0_1_e_35_we = addr_hit[41] & reg_we & ~wr_err;
+  assign ie0_1_e_35_wd = reg_wdata[3];
+  
+  assign threshold0_we = addr_hit[42] & reg_we & ~wr_err;
+  assign threshold0_wd = reg_wdata[1:0];
 
-  assign ie0_e_30_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_30_wd = reg_wdata[30];
+  assign cc0_we = addr_hit[43] & reg_we & ~wr_err;
+  assign cc0_wd = reg_wdata[7:0];
+  assign cc0_re = addr_hit[43] && reg_re;
 
-  assign ie0_e_31_we = addr_hit[34] & reg_we & ~wr_err;
-  assign ie0_e_31_wd = reg_wdata[31];
-
-  assign threshold0_we = addr_hit[35] & reg_we & ~wr_err;
-  assign threshold0_wd = reg_wdata[2:0];
-
-  assign cc0_we = addr_hit[36] & reg_we & ~wr_err;
-  assign cc0_wd = reg_wdata[5:0];
-  assign cc0_re = addr_hit[36] && reg_re;
-
-  assign msip0_we = addr_hit[37] & reg_we & ~wr_err;
+  assign msip0_we = addr_hit[44] & reg_we & ~wr_err;
   assign msip0_wd = reg_wdata[0];
 
   // Read data return
@@ -4231,242 +4728,283 @@ module rv_plic_reg_top (
     reg_rdata_next = '0;
     unique case (1'b1)
       addr_hit[0]: begin
-        reg_rdata_next[0] = ip_p_0_qs;
-        reg_rdata_next[1] = ip_p_1_qs;
-        reg_rdata_next[2] = ip_p_2_qs;
-        reg_rdata_next[3] = ip_p_3_qs;
-        reg_rdata_next[4] = ip_p_4_qs;
-        reg_rdata_next[5] = ip_p_5_qs;
-        reg_rdata_next[6] = ip_p_6_qs;
-        reg_rdata_next[7] = ip_p_7_qs;
-        reg_rdata_next[8] = ip_p_8_qs;
-        reg_rdata_next[9] = ip_p_9_qs;
-        reg_rdata_next[10] = ip_p_10_qs;
-        reg_rdata_next[11] = ip_p_11_qs;
-        reg_rdata_next[12] = ip_p_12_qs;
-        reg_rdata_next[13] = ip_p_13_qs;
-        reg_rdata_next[14] = ip_p_14_qs;
-        reg_rdata_next[15] = ip_p_15_qs;
-        reg_rdata_next[16] = ip_p_16_qs;
-        reg_rdata_next[17] = ip_p_17_qs;
-        reg_rdata_next[18] = ip_p_18_qs;
-        reg_rdata_next[19] = ip_p_19_qs;
-        reg_rdata_next[20] = ip_p_20_qs;
-        reg_rdata_next[21] = ip_p_21_qs;
-        reg_rdata_next[22] = ip_p_22_qs;
-        reg_rdata_next[23] = ip_p_23_qs;
-        reg_rdata_next[24] = ip_p_24_qs;
-        reg_rdata_next[25] = ip_p_25_qs;
-        reg_rdata_next[26] = ip_p_26_qs;
-        reg_rdata_next[27] = ip_p_27_qs;
-        reg_rdata_next[28] = ip_p_28_qs;
-        reg_rdata_next[29] = ip_p_29_qs;
-        reg_rdata_next[30] = ip_p_30_qs;
-        reg_rdata_next[31] = ip_p_31_qs;
+        reg_rdata_next[0] = ip_0_p_0_qs;
+        reg_rdata_next[1] = ip_0_p_1_qs;
+        reg_rdata_next[2] = ip_0_p_2_qs;
+        reg_rdata_next[3] = ip_0_p_3_qs;
+        reg_rdata_next[4] = ip_0_p_4_qs;
+        reg_rdata_next[5] = ip_0_p_5_qs;
+        reg_rdata_next[6] = ip_0_p_6_qs;
+        reg_rdata_next[7] = ip_0_p_7_qs;
+        reg_rdata_next[8] = ip_0_p_8_qs;
+        reg_rdata_next[9] = ip_0_p_9_qs;
+        reg_rdata_next[10] = ip_0_p_10_qs;
+        reg_rdata_next[11] = ip_0_p_11_qs;
+        reg_rdata_next[12] = ip_0_p_12_qs;
+        reg_rdata_next[13] = ip_0_p_13_qs;
+        reg_rdata_next[14] = ip_0_p_14_qs;
+        reg_rdata_next[15] = ip_0_p_15_qs;
+        reg_rdata_next[16] = ip_0_p_16_qs;
+        reg_rdata_next[17] = ip_0_p_17_qs;
+        reg_rdata_next[18] = ip_0_p_18_qs;
+        reg_rdata_next[19] = ip_0_p_19_qs;
+        reg_rdata_next[20] = ip_0_p_20_qs;
+        reg_rdata_next[21] = ip_0_p_21_qs;
+        reg_rdata_next[22] = ip_0_p_22_qs;
+        reg_rdata_next[23] = ip_0_p_23_qs;
+        reg_rdata_next[24] = ip_0_p_24_qs;
+        reg_rdata_next[25] = ip_0_p_25_qs;
+        reg_rdata_next[26] = ip_0_p_26_qs;
+        reg_rdata_next[27] = ip_0_p_27_qs;
+        reg_rdata_next[28] = ip_0_p_28_qs;
+        reg_rdata_next[29] = ip_0_p_29_qs;
+        reg_rdata_next[30] = ip_0_p_30_qs;
+        reg_rdata_next[31] = ip_0_p_31_qs;
       end
 
       addr_hit[1]: begin
-        reg_rdata_next[0] = le_le_0_qs;
-        reg_rdata_next[1] = le_le_1_qs;
-        reg_rdata_next[2] = le_le_2_qs;
-        reg_rdata_next[3] = le_le_3_qs;
-        reg_rdata_next[4] = le_le_4_qs;
-        reg_rdata_next[5] = le_le_5_qs;
-        reg_rdata_next[6] = le_le_6_qs;
-        reg_rdata_next[7] = le_le_7_qs;
-        reg_rdata_next[8] = le_le_8_qs;
-        reg_rdata_next[9] = le_le_9_qs;
-        reg_rdata_next[10] = le_le_10_qs;
-        reg_rdata_next[11] = le_le_11_qs;
-        reg_rdata_next[12] = le_le_12_qs;
-        reg_rdata_next[13] = le_le_13_qs;
-        reg_rdata_next[14] = le_le_14_qs;
-        reg_rdata_next[15] = le_le_15_qs;
-        reg_rdata_next[16] = le_le_16_qs;
-        reg_rdata_next[17] = le_le_17_qs;
-        reg_rdata_next[18] = le_le_18_qs;
-        reg_rdata_next[19] = le_le_19_qs;
-        reg_rdata_next[20] = le_le_20_qs;
-        reg_rdata_next[21] = le_le_21_qs;
-        reg_rdata_next[22] = le_le_22_qs;
-        reg_rdata_next[23] = le_le_23_qs;
-        reg_rdata_next[24] = le_le_24_qs;
-        reg_rdata_next[25] = le_le_25_qs;
-        reg_rdata_next[26] = le_le_26_qs;
-        reg_rdata_next[27] = le_le_27_qs;
-        reg_rdata_next[28] = le_le_28_qs;
-        reg_rdata_next[29] = le_le_29_qs;
-        reg_rdata_next[30] = le_le_30_qs;
-        reg_rdata_next[31] = le_le_31_qs;
+        reg_rdata_next[0] = ip_1_p_32_qs;
+        reg_rdata_next[1] = ip_1_p_33_qs;
+        reg_rdata_next[2] = ip_1_p_34_qs;
+        reg_rdata_next[3] = ip_1_p_35_qs;
       end
-
       addr_hit[2]: begin
-        reg_rdata_next[2:0] = prio0_qs;
+        reg_rdata_next[0] = le_0_le_0_qs;
+        reg_rdata_next[1] = le_0_le_1_qs;
+        reg_rdata_next[2] = le_0_le_2_qs;
+        reg_rdata_next[3] = le_0_le_3_qs;
+        reg_rdata_next[4] = le_0_le_4_qs;
+        reg_rdata_next[5] = le_0_le_5_qs;
+        reg_rdata_next[6] = le_0_le_6_qs;
+        reg_rdata_next[7] = le_0_le_7_qs;
+        reg_rdata_next[8] = le_0_le_8_qs;
+        reg_rdata_next[9] = le_0_le_9_qs;
+        reg_rdata_next[10] = le_0_le_10_qs;
+        reg_rdata_next[11] = le_0_le_11_qs;
+        reg_rdata_next[12] = le_0_le_12_qs;
+        reg_rdata_next[13] = le_0_le_13_qs;
+        reg_rdata_next[14] = le_0_le_14_qs;
+        reg_rdata_next[15] = le_0_le_15_qs;
+        reg_rdata_next[16] = le_0_le_16_qs;
+        reg_rdata_next[17] = le_0_le_17_qs;
+        reg_rdata_next[18] = le_0_le_18_qs;
+        reg_rdata_next[19] = le_0_le_19_qs;
+        reg_rdata_next[20] = le_0_le_20_qs;
+        reg_rdata_next[21] = le_0_le_21_qs;
+        reg_rdata_next[22] = le_0_le_22_qs;
+        reg_rdata_next[23] = le_0_le_23_qs;
+        reg_rdata_next[24] = le_0_le_24_qs;
+        reg_rdata_next[25] = le_0_le_25_qs;
+        reg_rdata_next[26] = le_0_le_26_qs;
+        reg_rdata_next[27] = le_0_le_27_qs;
+        reg_rdata_next[28] = le_0_le_28_qs;
+        reg_rdata_next[29] = le_0_le_29_qs;
+        reg_rdata_next[30] = le_0_le_30_qs;
+        reg_rdata_next[31] = le_0_le_31_qs;
       end
 
       addr_hit[3]: begin
-        reg_rdata_next[2:0] = prio1_qs;
+        reg_rdata_next[0] = le_1_le_32_qs;
+        reg_rdata_next[1] = le_1_le_33_qs;
+        reg_rdata_next[2] = le_1_le_34_qs;
+        reg_rdata_next[3] = le_1_le_35_qs;
       end
-
       addr_hit[4]: begin
-        reg_rdata_next[2:0] = prio2_qs;
+        reg_rdata_next[1:0] = prio0_qs;
       end
 
       addr_hit[5]: begin
-        reg_rdata_next[2:0] = prio3_qs;
+        reg_rdata_next[1:0] = prio1_qs;
       end
 
       addr_hit[6]: begin
-        reg_rdata_next[2:0] = prio4_qs;
+        reg_rdata_next[1:0] = prio2_qs;
       end
 
       addr_hit[7]: begin
-        reg_rdata_next[2:0] = prio5_qs;
+        reg_rdata_next[1:0] = prio3_qs;
       end
 
       addr_hit[8]: begin
-        reg_rdata_next[2:0] = prio6_qs;
+        reg_rdata_next[1:0] = prio4_qs;
       end
 
       addr_hit[9]: begin
-        reg_rdata_next[2:0] = prio7_qs;
+        reg_rdata_next[1:0] = prio5_qs;
       end
 
       addr_hit[10]: begin
-        reg_rdata_next[2:0] = prio8_qs;
+        reg_rdata_next[1:0] = prio6_qs;
       end
+
+      addr_hit[11]: begin
+        reg_rdata_next[1:0] = prio7_qs;
+      end
+
       addr_hit[12]: begin
-        reg_rdata_next[2:0] = prio10_qs;
+        reg_rdata_next[1:0] = prio8_qs;
       end
 
       addr_hit[13]: begin
-        reg_rdata_next[2:0] = prio11_qs;
+        reg_rdata_next[1:0] = prio9_qs;
       end
 
       addr_hit[14]: begin
-        reg_rdata_next[2:0] = prio12_qs;
+        reg_rdata_next[1:0] = prio10_qs;
       end
 
       addr_hit[15]: begin
-        reg_rdata_next[2:0] = prio13_qs;
+        reg_rdata_next[1:0] = prio11_qs;
       end
 
       addr_hit[16]: begin
-        reg_rdata_next[2:0] = prio14_qs;
+        reg_rdata_next[1:0] = prio12_qs;
       end
 
       addr_hit[17]: begin
-        reg_rdata_next[2:0] = prio15_qs;
+        reg_rdata_next[1:0] = prio13_qs;
       end
 
       addr_hit[18]: begin
-        reg_rdata_next[2:0] = prio16_qs;
+        reg_rdata_next[1:0] = prio14_qs;
       end
 
       addr_hit[19]: begin
-        reg_rdata_next[2:0] = prio17_qs;
+        reg_rdata_next[1:0] = prio15_qs;
       end
 
       addr_hit[20]: begin
-        reg_rdata_next[2:0] = prio18_qs;
+        reg_rdata_next[1:0] = prio16_qs;
       end
 
       addr_hit[21]: begin
-        reg_rdata_next[2:0] = prio19_qs;
+        reg_rdata_next[1:0] = prio17_qs;
       end
 
       addr_hit[22]: begin
-        reg_rdata_next[2:0] = prio20_qs;
+        reg_rdata_next[1:0] = prio18_qs;
       end
 
       addr_hit[23]: begin
-        reg_rdata_next[2:0] = prio21_qs;
+        reg_rdata_next[1:0] = prio19_qs;
       end
 
       addr_hit[24]: begin
-        reg_rdata_next[2:0] = prio22_qs;
+        reg_rdata_next[1:0] = prio20_qs;
       end
 
       addr_hit[25]: begin
-        reg_rdata_next[2:0] = prio23_qs;
+        reg_rdata_next[1:0] = prio21_qs;
       end
 
       addr_hit[26]: begin
-        reg_rdata_next[2:0] = prio24_qs;
+        reg_rdata_next[1:0] = prio22_qs;
       end
 
       addr_hit[27]: begin
-        reg_rdata_next[2:0] = prio25_qs;
+        reg_rdata_next[1:0] = prio23_qs;
       end
 
       addr_hit[28]: begin
-        reg_rdata_next[2:0] = prio26_qs;
+        reg_rdata_next[1:0] = prio24_qs;
       end
 
       addr_hit[29]: begin
-        reg_rdata_next[2:0] = prio27_qs;
+        reg_rdata_next[1:0] = prio25_qs;
       end
 
       addr_hit[30]: begin
-        reg_rdata_next[2:0] = prio28_qs;
+        reg_rdata_next[1:0] = prio26_qs;
       end
 
       addr_hit[31]: begin
-        reg_rdata_next[2:0] = prio29_qs;
+        reg_rdata_next[1:0] = prio27_qs;
       end
 
       addr_hit[32]: begin
-        reg_rdata_next[2:0] = prio30_qs;
+        reg_rdata_next[1:0] = prio28_qs;
       end
 
       addr_hit[33]: begin
-        reg_rdata_next[2:0] = prio31_qs;
+        reg_rdata_next[1:0] = prio29_qs;
       end
 
       addr_hit[34]: begin
-        reg_rdata_next[0] = ie0_e_0_qs;
-        reg_rdata_next[1] = ie0_e_1_qs;
-        reg_rdata_next[2] = ie0_e_2_qs;
-        reg_rdata_next[3] = ie0_e_3_qs;
-        reg_rdata_next[4] = ie0_e_4_qs;
-        reg_rdata_next[5] = ie0_e_5_qs;
-        reg_rdata_next[6] = ie0_e_6_qs;
-        reg_rdata_next[7] = ie0_e_7_qs;
-        reg_rdata_next[8] = ie0_e_8_qs;
-        reg_rdata_next[9] = ie0_e_9_qs;
-        reg_rdata_next[10] = ie0_e_10_qs;
-        reg_rdata_next[11] = ie0_e_11_qs;
-        reg_rdata_next[12] = ie0_e_12_qs;
-        reg_rdata_next[13] = ie0_e_13_qs;
-        reg_rdata_next[14] = ie0_e_14_qs;
-        reg_rdata_next[15] = ie0_e_15_qs;
-        reg_rdata_next[16] = ie0_e_16_qs;
-        reg_rdata_next[17] = ie0_e_17_qs;
-        reg_rdata_next[18] = ie0_e_18_qs;
-        reg_rdata_next[19] = ie0_e_19_qs;
-        reg_rdata_next[20] = ie0_e_20_qs;
-        reg_rdata_next[21] = ie0_e_21_qs;
-        reg_rdata_next[22] = ie0_e_22_qs;
-        reg_rdata_next[23] = ie0_e_23_qs;
-        reg_rdata_next[24] = ie0_e_24_qs;
-        reg_rdata_next[25] = ie0_e_25_qs;
-        reg_rdata_next[26] = ie0_e_26_qs;
-        reg_rdata_next[27] = ie0_e_27_qs;
-        reg_rdata_next[28] = ie0_e_28_qs;
-        reg_rdata_next[29] = ie0_e_29_qs;
-        reg_rdata_next[30] = ie0_e_30_qs;
-        reg_rdata_next[31] = ie0_e_31_qs;
+        reg_rdata_next[1:0] = prio30_qs;
       end
 
       addr_hit[35]: begin
-        reg_rdata_next[2:0] = threshold0_qs;
+        reg_rdata_next[1:0] = prio31_qs;
       end
 
       addr_hit[36]: begin
-        reg_rdata_next[5:0] = cc0_qs;
+        reg_rdata_next[1:0] = prio32_qs;
       end
 
       addr_hit[37]: begin
+        reg_rdata_next[1:0] = prio33_qs;
+      end
+
+      addr_hit[38]: begin
+        reg_rdata_next[1:0] = prio34_qs;
+      end
+
+      addr_hit[39]: begin
+        reg_rdata_next[1:0] = prio35_qs;
+      end
+
+      addr_hit[40]: begin
+        reg_rdata_next[0] = ie0_0_e_0_qs;
+        reg_rdata_next[1] = ie0_0_e_1_qs;
+        reg_rdata_next[2] = ie0_0_e_2_qs;
+        reg_rdata_next[3] = ie0_0_e_3_qs;
+        reg_rdata_next[4] = ie0_0_e_4_qs;
+        reg_rdata_next[5] = ie0_0_e_5_qs;
+        reg_rdata_next[6] = ie0_0_e_6_qs;
+        reg_rdata_next[7] = ie0_0_e_7_qs;
+        reg_rdata_next[8] = ie0_0_e_8_qs;
+        reg_rdata_next[9] = ie0_0_e_9_qs;
+        reg_rdata_next[10] = ie0_0_e_10_qs;
+        reg_rdata_next[11] = ie0_0_e_11_qs;
+        reg_rdata_next[12] = ie0_0_e_12_qs;
+        reg_rdata_next[13] = ie0_0_e_13_qs;
+        reg_rdata_next[14] = ie0_0_e_14_qs;
+        reg_rdata_next[15] = ie0_0_e_15_qs;
+        reg_rdata_next[16] = ie0_0_e_16_qs;
+        reg_rdata_next[17] = ie0_0_e_17_qs;
+        reg_rdata_next[18] = ie0_0_e_18_qs;
+        reg_rdata_next[19] = ie0_0_e_19_qs;
+        reg_rdata_next[20] = ie0_0_e_20_qs;
+        reg_rdata_next[21] = ie0_0_e_21_qs;
+        reg_rdata_next[22] = ie0_0_e_22_qs;
+        reg_rdata_next[23] = ie0_0_e_23_qs;
+        reg_rdata_next[24] = ie0_0_e_24_qs;
+        reg_rdata_next[25] = ie0_0_e_25_qs;
+        reg_rdata_next[26] = ie0_0_e_26_qs;
+        reg_rdata_next[27] = ie0_0_e_27_qs;
+        reg_rdata_next[28] = ie0_0_e_28_qs;
+        reg_rdata_next[29] = ie0_0_e_29_qs;
+        reg_rdata_next[30] = ie0_0_e_30_qs;
+        reg_rdata_next[31] = ie0_0_e_31_qs;
+      end
+
+      addr_hit[41]: begin
+        reg_rdata_next[0] = ie0_1_e_32_qs;
+        reg_rdata_next[1] = ie0_1_e_33_qs;
+        reg_rdata_next[2] = ie0_1_e_34_qs;
+        reg_rdata_next[3] = ie0_1_e_35_qs;
+      end
+
+     
+      addr_hit[42]: begin
+        reg_rdata_next[1:0] = threshold0_qs;
+      end
+
+      addr_hit[43]: begin
+        reg_rdata_next[7:0] = cc0_qs;
+      end
+
+      addr_hit[44]: begin
         reg_rdata_next[0] = msip0_qs;
       end
 
diff --git a/hw/ip/rv_plic/rtl/rv_plic_target.sv b/hw/ip/rv_plic/rtl/rv_plic_target.sv
index 045c202a..da1aafb0 100644
--- a/hw/ip/rv_plic/rtl/rv_plic_target.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic_target.sv
@@ -21,14 +21,14 @@ module rv_plic_target #(
   localparam int SrcWidth  = $clog2(N_SOURCE+1),  // derived parameter
   localparam int PrioWidth = $clog2(MAX_PRIO+1)   // derived parameter
 ) (
-  input clk_i,
-  input rst_ni,
+  input logic clk_i,
+  input logic rst_ni,
 
-  input [N_SOURCE-1:0]  ip_i,
-  input [N_SOURCE-1:0]  ie_i,
+  input logic [N_SOURCE-1:0]  ip_i,
+  input logic [N_SOURCE-1:0]  ie_i,
 
-  input [PrioWidth-1:0] prio_i [N_SOURCE],
-  input [PrioWidth-1:0] threshold_i,
+  input logic [PrioWidth-1:0] prio_i [N_SOURCE],
+  input logic [PrioWidth-1:0] threshold_i,
 
   output logic            irq_o,
   output logic [SrcWidth-1:0] irq_id_o
diff --git a/hw/ip/spi_host/rtl/spi_clgen.v b/hw/ip/spi_host/rtl/spi_clgen.v
index bbeeafe2..a548f888 100644
--- a/hw/ip/spi_host/rtl/spi_clgen.v
+++ b/hw/ip/spi_host/rtl/spi_clgen.v
@@ -1,13 +1,13 @@
-// `include "/home/merl/github_repos/azadi/src/spi_host/rtl/spi_defines.v"
-// `include "/home/zeeshan/fyp/azadi/src/spi_host/rtl/spi_defines.v"
+// `include "/home/merl/github_repos/azadi/src/spi_host/rtl/spi_defines.v"//
+//`include "spi_defines.v"
 
 module spi_clgen (
-  input                            clk_in,   // input clock (system clock)
-  input                            rst,      // reset
-  input                            enable,   // clock enable
-  input                            go,       // start transfer
-  input                            last_clk, // last clock
-  input     [`SPI_DIVIDER_LEN-1:0] divider,  // clock divider (output clock is divided by this value)
+  input    wire                        clk_i,   // input clock (system clock)
+  input    wire                        rst_ni,      // reset
+  input    wire                        enable,   // clock enable
+  input    wire                        go,       // start transfer
+  input    wire                        last_clk, // last clock
+  input    wire [`SPI_DIVIDER_LEN-1:0] divider,  // clock divider (output clock is divided by this value)
   output    reg                    clk_out,  // output clock
   output    reg                    pos_edge, // pulse marking positive edge of clk_out
   output    reg                    neg_edge // pulse marking negative edge of clk_out
@@ -17,51 +17,31 @@ module spi_clgen (
   //reg                              clk_out;
   //reg                              pos_edge;
   //reg                              neg_edge;
-                            
-  reg       [`SPI_DIVIDER_LEN-1:0] cnt;      // clock counter 
-  wire                             cnt_zero; // conter is equal to zero
-  wire                             cnt_one;  // conter is equal to one
-  
-  
-  assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}};
-  assign cnt_one  = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
-  
-  // Counter counts half period
-  always @(posedge clk_in or posedge rst)
-  begin
-    if(rst)
-      cnt <=  {`SPI_DIVIDER_LEN{1'b1}};
-    else
-      begin
-        if(!enable || cnt_zero)
-          cnt <=  divider;
-        else
-          cnt <=  cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
-      end
-  end
-  
-  // clk_out is asserted every other half period
-  always @(posedge clk_in or posedge rst)
-  begin
-    if(rst)
-      clk_out <=  1'b0;
-    else
-      clk_out <=  (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
-  end
-   
-  // Pos and neg edge signals
-  always @(posedge clk_in or posedge rst)
-  begin
-    if(rst)
-      begin
-        pos_edge  <=  1'b0;
-        neg_edge  <=  1'b0;
-      end
-    else
-      begin
-        pos_edge  <=  (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
-        neg_edge  <=  (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
-      end
-  end
+  reg [15:0] cnt;                          
+  wire cnt_zero;
+	wire cnt_one;
+	assign cnt_zero = cnt == {16 {1'b0}};
+	assign cnt_one = cnt == {{15 {1'b0}}, 1'b1};
+	always @(posedge clk_i or negedge rst_ni)
+	if (~rst_ni)
+		cnt <= {16 {1'b1}};
+	else if (!enable || cnt_zero)
+		cnt <= divider;
+	else
+		cnt <= cnt - {{15 {1'b0}}, 1'b1};
+	always @(posedge clk_i or negedge rst_ni)
+	if (~rst_ni)
+		clk_out <= 1'b0;
+	else
+		clk_out <= ((enable && cnt_zero) && (!last_clk || clk_out) ? ~clk_out : clk_out);
+	always @(posedge clk_i or negedge rst_ni)
+	if (~rst_ni) begin
+		pos_edge <= 1'b0;
+		neg_edge <= 1'b0;
+	end
+	else begin
+		pos_edge <= (((enable && !clk_out) && cnt_one) || (!(|divider) && clk_out)) || ((!(|divider) && go) && !enable);
+		neg_edge <= ((enable && clk_out) && cnt_one) || ((!(|divider) && !clk_out) && enable);
+	end
 endmodule
  
diff --git a/hw/ip/spi_host/rtl/spi_core.sv b/hw/ip/spi_host/rtl/spi_core.sv
new file mode 100644
index 00000000..ed85f128
--- /dev/null
+++ b/hw/ip/spi_host/rtl/spi_core.sv
@@ -0,0 +1,158 @@
+// `include "/home/merl/github_repos/azadi/src/spi_host/rtl/spi_defines.v"
+//`include "/home/zeeshan/fyp/azadi/src/spi_host/rtl/spi_defines.v"
+//`include "spi_defines.v"
+module spi_core
+(
+  // tlul signals
+  input  logic        clk_i,        
+  input  logic        rst_ni,        
+  input  logic [7:0]  addr_i,            
+  input  logic [31:0] wdata_i,              
+  output reg   [31:0] rdata_o,             
+  input  logic [3:0]  be_i,           
+  input  logic        we_i,       
+  input  logic        re_i,        
+  output reg    error_o,       
+  output reg    intr_rx_o,
+  output reg    intr_tx_o,         
+                                                     
+  // SPI signals                                     
+  output logic    [`SPI_SS_NB-1:0] ss_o,         // slave select
+  output logic                     sclk_o,       // serial clock
+  output logic                     sd_o,
+  output reg                       sd_oe,       // master out slave in
+  input  logic                     sd_i       // master in slave out
+);
+
+                                               
+  // Internal signals
+  reg [15:0] divider;
+	reg [15:0] ctrl;
+	reg [3:0] ss;
+	reg [31:0] wb_dat;
+	wire [31:0] rx;
+	wire rx_negedge;
+	wire tx_negedge;
+	wire [4:0] char_len;
+	wire go;
+	wire lsb;
+	wire ie;
+	wire ass;
+	wire spi_divider_sel;
+	wire spi_ctrl_sel;
+	wire spi_tx_sel;
+	wire spi_ss_sel;
+	wire tip;
+	wire pos_edge;
+	wire neg_edge;
+	wire last_bit;
+	wire tx_en;
+	wire rx_en;
+	assign spi_divider_sel = (we_i & ~re_i) & (addr_i[6:0] == 7'h14);
+	assign spi_ctrl_sel = (we_i & ~re_i) & (addr_i[6:0] == 7'h10);
+	assign spi_tx_sel = ((we_i & ~re_i) & (addr_i[6:0] == 7'h0));
+	assign spi_ss_sel = (we_i & ~re_i) & (addr_i[6:0] == 7'h18);
+	always @(addr_i or rx or ctrl or divider or ss)
+		case (addr_i[6:2])
+			8: wb_dat = rx[31:0];
+			default: wb_dat = 32'b00000000000000000000000000000000;
+		endcase
+	always @(posedge clk_i)
+		if (~rst_ni)
+			rdata_o <= 32'b00000000000000000000000000000000;
+		else
+			rdata_o <= wb_dat;
+	wire [1:1] sv2v_tmp_46A40;
+	assign sv2v_tmp_46A40 = 1'b0;
+	always @(*) error_o = sv2v_tmp_46A40;
+	always @(posedge clk_i)
+		if (~rst_ni)
+			intr_tx_o <= 1'b0;
+		else if ((((ie && tip) && last_bit) && pos_edge) && tx_en)
+			intr_tx_o <= 1'b1;
+		else
+			intr_tx_o <= 1'b0;
+	always @(posedge clk_i)
+		if (~rst_ni)
+			intr_rx_o <= 1'b0;
+		else if ((((ie && tip) && last_bit) && pos_edge) && rx_en)
+			intr_rx_o <= 1'b1;
+		else
+			intr_rx_o <= 1'b0;
+	always @(posedge clk_i)
+		if (~rst_ni)
+			divider <= {16 {1'b0}};
+		else if ((spi_divider_sel && we_i) && !tip) begin
+			if (be_i[0])
+				divider[7:0] <= wdata_i[7:0];
+			if (be_i[1])
+				divider[15:8] <= wdata_i[15:8];
+		end
+	always @(posedge clk_i)
+		if (~rst_ni)
+			ctrl <= {16 {1'b0}};
+		else if ((spi_ctrl_sel && we_i) && !tip) begin
+			if (be_i[0])
+				ctrl[7:0] <= wdata_i[7:0] | {7'b0000000, ctrl[0]};
+			if (be_i[1])
+				ctrl[15:8] <= wdata_i[15:8];
+		end
+		else if ((tip && last_bit) && pos_edge)
+			ctrl[8] <= 1'b0;
+	assign rx_negedge = ctrl[9];
+	assign tx_negedge = ctrl[10];
+	assign go = ctrl[8];
+	assign char_len = ctrl[6:0];
+	assign lsb = ctrl[11];
+	assign ie = ctrl[12];
+	assign ass = ctrl[13];
+	assign rx_en = ctrl[15];
+	assign tx_en = ctrl[14];
+	always @(posedge clk_i or negedge rst_ni)
+		if (~rst_ni)
+			sd_oe <= 1'b0;
+		else if (tx_en & !rx_en)
+			sd_oe <= 1'b1;
+		else
+			sd_oe <= 1'b0;
+	always @(posedge clk_i)
+		if (~rst_ni)
+			ss <= {4 {1'b0}};
+		else if ((spi_ss_sel && we_i) && !tip)
+			if (be_i[0])
+				ss <= wdata_i[3:0];
+	assign ss_o = ~((ss & {4 {tip & ass}}) | (ss & {4 {!ass}}));
+	spi_clgen clgen(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.go(go),
+		.enable(tip),
+		.last_clk(last_bit),
+		.divider(divider),
+		.clk_out(sclk_o),
+		.pos_edge(pos_edge),
+		.neg_edge(neg_edge)
+	);
+	spi_shift shift(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.len(char_len[4:0]),
+		.latch(spi_tx_sel & we_i),
+		.byte_sel(be_i),
+		.lsb(lsb),
+		.go(go),
+		.pos_edge(pos_edge),
+		.neg_edge(neg_edge),
+		.rx_negedge(rx_negedge),
+		.tx_negedge(tx_negedge),
+		.tip(tip),
+		.last(last_bit),
+		.p_in(wdata_i),
+		.p_out(rx),
+		.s_clk(sclk_o),
+		.s_in(sd_i),
+		.s_out(sd_o),
+		.rx_en(rx_en)
+	);
+endmodule
+  
diff --git a/hw/ip/spi_host/rtl/spi_core.v b/hw/ip/spi_host/rtl/spi_core.v
deleted file mode 100644
index 717bacd8..00000000
--- a/hw/ip/spi_host/rtl/spi_core.v
+++ /dev/null
@@ -1,245 +0,0 @@
-// `include "/home/merl/github_repos/azadi/src/spi_host/rtl/spi_defines.v"
-// `include "/home/zeeshan/fyp/azadi/src/spi_host/rtl/spi_defines.v"
-
-module spi_core
-(
-  // tlul signals
-  input         clk_i,        
-  input         rst_ni,        
-  input  [7:0]  addr_i,            
-  input  [31:0] wdata_i,              
-  output reg [31:0] rdata_o,             
-  input  [3:0]  be_i,           
-  input         we_i,       
-  input         re_i,        
-  output        error_o,       
-  output        intr_rx_o,
-  output        intr_tx_o,         
-                                                     
-  // SPI signals                                     
-  output          [`SPI_SS_NB-1:0] ss_o,         // slave select
-  output                           sclk_o,       // serial clock
-  output                           sd_o,       // master out slave in
-  input                            sd_i       // master in slave out
-);
-
-                                               
-  // Internal signals
-  reg       [`SPI_DIVIDER_LEN-1:0] divider;          // Divider register
-  reg       [`SPI_CTRL_BIT_NB-1:0] ctrl;             // Control and status register
-  reg             [`SPI_SS_NB-1:0] ss;               // Slave select register
-  reg                     [32-1:0] wb_dat;           // wb data out
-  wire         [`SPI_MAX_CHAR-1:0] rx;               // Rx register
-  wire                             rx_negedge;       // miso is sampled on negative edge
-  wire                             tx_negedge;       // mosi is driven on negative edge
-  wire    [`SPI_CHAR_LEN_BITS-1:0] char_len;         // char len
-  wire                             go;               // go
-  wire                             lsb;              // lsb first on line
-  wire                             ie;               // interrupt enable
-  wire                             ass;              // automatic slave select
-  wire                             spi_divider_sel;  // divider register select
-  wire                             spi_ctrl_sel;     // ctrl register select
-  wire                             spi_tx_sel;       // tx_l register select
-  wire                             spi_ss_sel;       // ss register select
-  wire                             tip;              // transfer in progress
-  wire                             pos_edge;         // recognize posedge of sclk
-  wire                             neg_edge;         // recognize negedge of sclk
-  wire                             last_bit;         // marks last character bit
-  wire                             tx_en;            // enables spi transmission
-  wire                             rx_en;            // enables spi reception
-  
-  // Address decoder
-  assign spi_divider_sel = we_i & ~re_i & (addr_i[`SPI_OFS_BITS] == `SPI_DEVIDE);
-  assign spi_ctrl_sel    = we_i & ~re_i & (addr_i[`SPI_OFS_BITS] == `SPI_CTRL);
-  assign spi_tx_sel      = we_i & ~re_i & (addr_i[`SPI_OFS_BITS] == `SPI_TX_0) & tx_en;
-  assign spi_ss_sel      = we_i & ~re_i & (addr_i[`SPI_OFS_BITS] == `SPI_SS);
-  
-  // Read from registers
-  always @(addr_i or rx or ctrl or divider or ss)
-  begin
-    case (addr_i[`SPI_OFS_BITS])
-      `SPI_RX_0:    wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]};
-      `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
-      `SPI_DEVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
-      `SPI_SS:      wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
-      default:      wb_dat = 32'b0;
-    endcase
-  end
-  
-  // Wb data out
-  always @(posedge clk_i or posedge rst_ni)
-  begin
-    if (~rst_ni)
-      rdata_o <=  32'b0;
-    else
-      rdata_o <=  wb_dat;
-  end
-
-  
-  // Wb error
-  assign error_o = 1'b0;
-  
-  // Interrupt
-  always @(posedge clk_i or posedge rst_ni)
-  begin
-    if (~rst_ni)
-      intr_tx_o <=  1'b0;
-    else if (ie && tip && last_bit && pos_edge && tx_en)
-      intr_tx_o <=  1'b1;
-    else 
-      intr_tx_o <=  1'b0;
-  end
-
-  always @(posedge clk_i or posedge rst_ni)
-  begin
-    if (~rst_ni)
-      intr_rx_o <=  1'b0;
-    else if (ie && tip && last_bit && pos_edge && rx_en)
-      intr_rx_o <=  1'b1;
-    else 
-      intr_rx_o <=  1'b0;
-  end
-  
-  // Divider register
-  always @(posedge clk_i or posedge rst_ni)
-  begin
-    if (~rst_ni)
-        divider <=  {`SPI_DIVIDER_LEN{1'b0}};
-    else if (spi_divider_sel && we_i && !tip)
-      begin
-      `ifdef SPI_DIVIDER_LEN_8
-        if (be_i[0])
-          divider <=  wdata_i[`SPI_DIVIDER_LEN-1:0];
-      `endif
-      `ifdef SPI_DIVIDER_LEN_16
-        if (be_i[0])
-          divider[7:0] <=  wdata_i[7:0];
-        if (be_i[1])
-          divider[`SPI_DIVIDER_LEN-1:8] <=  wdata_i[`SPI_DIVIDER_LEN-1:8];
-      `endif
-      `ifdef SPI_DIVIDER_LEN_24
-        if (be_i[0])
-          divider[7:0] <=  wdata_i[7:0];
-        if (be_i[1])
-          divider[15:8] <=  wdata_i[15:8];
-        if (be_i[2])
-          divider[`SPI_DIVIDER_LEN-1:16] <=  wdata_i[`SPI_DIVIDER_LEN-1:16];
-      `endif
-      `ifdef SPI_DIVIDER_LEN_32
-        if (be_i[0])
-          divider[7:0] <=  wdata_i[7:0];
-        if (be_i[1])
-          divider[15:8] <=  wdata_i[15:8];
-        if (be_i[2])
-          divider[23:16] <=  wdata_i[23:16];
-        if (be_i[3])
-          divider[`SPI_DIVIDER_LEN-1:24] <=  wdata_i[`SPI_DIVIDER_LEN-1:24];
-      `endif
-      end
-  end
-  
-  // Ctrl register
-  always @(posedge clk_i or posedge rst_ni)
-  begin
-    if (~rst_ni)
-      ctrl <=  {`SPI_CTRL_BIT_NB{1'b0}};
-    else if(spi_ctrl_sel && we_i && !tip)
-      begin
-        if (be_i[0])
-          ctrl[7:0] <=  wdata_i[7:0] | {7'b0, ctrl[0]};
-        if (be_i[1])
-          ctrl[`SPI_CTRL_BIT_NB-1:8] <=  wdata_i[`SPI_CTRL_BIT_NB-1:8];
-      end
-    else if(tip && last_bit && pos_edge)
-      ctrl[`SPI_CTRL_GO] <=  1'b0;
-  end
-  
-  assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
-  assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
-  assign go         = ctrl[`SPI_CTRL_GO];
-  assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];
-  assign lsb        = ctrl[`SPI_CTRL_LSB];
-  assign ie         = ctrl[`SPI_CTRL_IE];
-  assign ass        = ctrl[`SPI_CTRL_ASS];
-  assign rx_en      = ctrl[`SPI_RX_SEL];
-  assign tx_en      = ctrl[`SPI_TX_SEL];
-  
-  // Slave select register
-  always @(posedge clk_i or posedge rst_ni)
-  begin
-    if (~rst_ni)
-      ss <=  {`SPI_SS_NB{1'b0}};
-    else if(spi_ss_sel && we_i && !tip)
-      begin
-      `ifdef SPI_SS_NB_4
-        if (be_i[0])
-          ss <=  wdata_i[`SPI_SS_NB-1:0];
-      `endif
-      `ifdef SPI_SS_NB_8
-        if (be_i[0])
-          ss <=  wdata_i[`SPI_SS_NB-1:0];
-      `endif
-      `ifdef SPI_SS_NB_16
-        if (be_i[0])
-          ss[7:0] <=  wdata_i[7:0];
-        if (be_i[1])
-          ss[`SPI_SS_NB-1:8] <=  wdata_i[`SPI_SS_NB-1:8];
-      `endif
-      `ifdef SPI_SS_NB_24
-        if (be_i[0])
-          ss[7:0] <=  wdata_i[7:0];
-        if (be_i[1])
-          ss[15:8] <=  wdata_i[15:8];
-        if (be_i[2])
-          ss[`SPI_SS_NB-1:16] <=  wdata_i[`SPI_SS_NB-1:16];
-      `endif
-      `ifdef SPI_SS_NB_32
-        if (be_i[0])
-          ss[7:0] <=  wdata_i[7:0];
-        if (be_i[1])
-          ss[15:8] <=  wdata_i[15:8];
-        if (be_i[2])
-          ss[23:16] <=  wdata_i[23:16];
-        if (be_i[3])
-          ss[`SPI_SS_NB-1:24] <=  wdata_i[`SPI_SS_NB-1:24];
-      `endif
-      end
-  end
-  
-  assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
-  
-  spi_clgen clgen (
-    .clk_in      (clk_i), 
-    .rst         (~rst_ni), 
-    .go          (go), 
-    .enable      (tip), 
-    .last_clk    (last_bit),
-    .divider     (divider), 
-    .clk_out     (sclk_o), 
-    .pos_edge    (pos_edge), 
-    .neg_edge    (neg_edge)
-    );
-  
-  spi_shift shift (
-    .clk          (clk_i), 
-    .rst          (~rst_ni), 
-    .len          (char_len[`SPI_CHAR_LEN_BITS-1:0]),
-    .latch        (spi_tx_sel & we_i), 
-    .byte_sel     (be_i), 
-    .lsb          (lsb), 
-    .go           (go), 
-    .pos_edge     (pos_edge), 
-    .neg_edge     (neg_edge), 
-    .rx_negedge   (rx_negedge), 
-    .tx_negedge   (tx_negedge),
-    .tip          (tip), 
-    .last         (last_bit), 
-    .p_in         (wdata_i), 
-    .p_out        (rx), 
-    .s_clk        (sclk_o), 
-    .s_in         (sd_i), 
-    .s_out        (sd_o),
-    .rx_en        (rx_en) 
-    );
-endmodule
-  
diff --git a/hw/ip/spi_host/rtl/spi_defines.v b/hw/ip/spi_host/rtl/spi_defines.v
index 8ba50942..3e43ac96 100644
--- a/hw/ip/spi_host/rtl/spi_defines.v
+++ b/hw/ip/spi_host/rtl/spi_defines.v
@@ -4,7 +4,7 @@
 // Use SPI_DIVIDER_LEN for fine tuning theexact number.
 //
 //`define SPI_DIVIDER_LEN_8
-`define SPI_DIVIDER_LEN_32
+`define SPI_DIVIDER_LEN_16
 //`define SPI_DIVIDER_LEN_24
 //`define SPI_DIVIDER_LEN_32
 
@@ -85,7 +85,7 @@
 //
 // Bits of WISHBONE address used for partial decoding of SPI registers.
 //
-`define SPI_OFS_BITS	          4:2
+`define SPI_OFS_BITS	          6:2
 
 //
 // Register offset
diff --git a/hw/ip/spi_host/rtl/spi_shift.v b/hw/ip/spi_host/rtl/spi_shift.v
index f4b8aab3..6b954b5d 100644
--- a/hw/ip/spi_host/rtl/spi_shift.v
+++ b/hw/ip/spi_host/rtl/spi_shift.v
@@ -1,103 +1,76 @@
-
+//`include "spi_defines.v"
 
 module spi_shift (
-  input                          clk,          // system clock
-  input                          rst,          // reset
-  input                          latch,        // latch signal for storing the data in shift register
-  input                    [3:0] byte_sel,     // byte select signals for storing the data in shift register
-  input [`SPI_CHAR_LEN_BITS-1:0] len,          // data len in bits (minus one)
-  input                          lsb,          // lbs first on the line
-  input                          go,           // start stansfer
-  input                          pos_edge,     // recognize posedge of sclk
-  input                          neg_edge,     // recognize negedge of sclk
-  input                          rx_negedge,   // s_in is sampled on negative edge 
-  input                          tx_negedge,   // s_out is driven on negative edge
+  input  wire                        clk_i,          // system clock
+  input  wire                        rst_ni,          // reset
+  input  wire                        latch,        // latch signal for storing the data in shift register
+  input  wire                  [3:0] byte_sel,     // byte select signals for storing the data in shift register
+  input  wire [`SPI_CHAR_LEN_BITS-1:0] len,          // data len in bits (minus one)
+  input  wire                        lsb,          // lbs first_ni on the line
+  input  wire                        go,           // start stansfer
+  input  wire                        pos_edge,     // recognize posedge of sclk_i
+  input  wire                        neg_edge,     // recognize negedge of sclk_i
+  input  wire                        rx_negedge,   // s_in is sampled on negative edge 
+  input  wire                        tx_negedge,   // s_out is driven on negative edge
   output   reg                   tip,          // transfer in progress
-  output                         last,         // last bit
-  input                   [31:0] p_in,         // parallel in
-  output     [`SPI_MAX_CHAR-1:0] p_out,        // parallel out
-  input                          s_clk,        // serial clock
-  input                          s_in,         // serial in
+  output wire                        last,         // last bit
+  input  wire                 [31:0] p_in,         // parallel in
+  output wire    [`SPI_MAX_CHAR-1:0] p_out,        // parallel out
+  input  wire                        s_clk,        // serial clock
+  input  wire                        s_in,         // serial in
   output   reg                   s_out,        // serial out
-  input                          rx_en         // serial rx enable  
+  input  wire                        rx_en         // serial rx enable  
 );
                                    
  // reg                            s_out;        
  // reg                            tip;
                               
-  reg     [`SPI_CHAR_LEN_BITS:0] cnt;          // data bit count
-  reg        [`SPI_MAX_CHAR-1:0] data; 
-  reg        [`SPI_MAX_CHAR-1:0] data_rx;        // shift register
-  wire    [`SPI_CHAR_LEN_BITS:0] tx_bit_pos;   // next bit position
-  wire    [`SPI_CHAR_LEN_BITS:0] rx_bit_pos;   // next bit position
-  wire                           rx_clk;       // rx clock enable
-  wire                           tx_clk;       // tx clock enable
-  
-  assign p_out = data_rx;
-  
-  assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
-  assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : 
-                            (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
-  
-  assign last = !(|cnt);
-  
-  assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
-  assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
-  
-  // Character bit counter
-  always @(posedge clk or posedge rst)
-  begin
-    if(rst)
-      cnt <=  {`SPI_CHAR_LEN_BITS+1{1'b0}};
-    else
-      begin
-        if(tip)
-          cnt <=  pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
-        else
-          cnt <=  !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
-      end
-  end
-  
-  // Transfer in progress
-  always @(posedge clk or posedge rst)
-  begin
-    if(rst)
-      tip <=  1'b0;
-  else if(go && ~tip)
-    tip <=  1'b1;
-  else if(tip && last && pos_edge)
-    tip <=  1'b0;
-  end
-  
-  // Sending bits to the line
-  always @(posedge clk or posedge rst)
-  begin
-    if (rst)
-      s_out   <=  1'b0;
-    else
-      s_out <=  (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
-  end
-  
-  // Receiving bits from the line
-  always @(posedge clk or posedge rst)
-  begin
-    if (rst)
-      data   <=  {`SPI_MAX_CHAR{1'b0}};
-    else if (latch && !tip)
-      begin
-        if (byte_sel[0])
-          data[7:0] <=   p_in[7:0];
-        if (byte_sel[1])
-          data[15:8] <=  p_in[15:8];
-        if (byte_sel[2])
-          data[23:16] <= p_in[23:16];
-        if (byte_sel[3])
-          data[`SPI_MAX_CHAR-1:24] <=  p_in[`SPI_MAX_CHAR-1:24];
-      end
-    else if (rx_en && tip) begin
-      data_rx[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <=  rx_clk ? s_in : data_rx[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
-    end
-  end
-  
+ reg [5:0] cnt;
+	reg [31:0] data;
+	reg [31:0] data_rx;
+	wire [5:0] tx_bit_pos;
+	wire [5:0] rx_bit_pos;
+	wire rx_clk_i;
+	wire tx_clk_i;
+	assign p_out = data_rx;
+	assign tx_bit_pos = (lsb ? {!(|len), len} - cnt : cnt - {{5 {1'b0}}, 1'b1});
+	assign rx_bit_pos = (lsb ? {!(|len), len} - (rx_negedge ? cnt + {{5 {1'b0}}, 1'b1} : cnt) : (rx_negedge ? cnt : cnt - {{5 {1'b0}}, 1'b1}));
+	assign last = !(|cnt);
+	assign rx_clk_i = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
+	assign tx_clk_i = (tx_negedge ? neg_edge : pos_edge) && !last;
+	always @(posedge clk_i or negedge rst_ni)
+		if (~rst_ni)
+			cnt <= {6 {1'b0}};
+		else if (tip)
+			cnt <= (pos_edge ? cnt - {{5 {1'b0}}, 1'b1} : cnt);
+		else
+			cnt <= (!(|len) ? {1'b1, {5 {1'b0}}} : {1'b0, len});
+	always @(posedge clk_i or negedge rst_ni)
+		if (~rst_ni)
+			tip <= 1'b0;
+		else if (go && ~tip)
+			tip <= 1'b1;
+		else if ((tip && last) && pos_edge)
+			tip <= 1'b0;
+	always @(posedge clk_i or negedge rst_ni)
+		if (~rst_ni)
+			s_out <= 1'b0;
+		else
+			s_out <= (tx_clk_i || !tip ? data[tx_bit_pos[4:0]] : s_out);
+	always @(posedge clk_i)
+		if (~rst_ni)
+			data <= {32 {1'b0}};
+		else if (latch && !tip) begin
+			if (byte_sel[0])
+				data[7:0] <= p_in[7:0];
+			if (byte_sel[1])
+				data[15:8] <= p_in[15:8];
+			if (byte_sel[2])
+				data[23:16] <= p_in[23:16];
+			if (byte_sel[3])
+				data[31:24] <= p_in[31:24];
+		end
+		else if (rx_en && tip)
+			data_rx[rx_bit_pos[4:0]] <= (rx_clk_i ? s_in : data_rx[rx_bit_pos[4:0]]);
 endmodule
 
diff --git a/hw/ip/spi_host/rtl/spi_top.sv b/hw/ip/spi_host/rtl/spi_top.sv
index 79f3ea2f..ce2b418e 100644
--- a/hw/ip/spi_host/rtl/spi_top.sv
+++ b/hw/ip/spi_host/rtl/spi_top.sv
@@ -1,21 +1,22 @@
 // `include "/home/merl/github_repos/azadi/src/spi_host/rtl/spi_defines.v"
-// `include "/home/zeeshan/fyp/azadi/src/spi_host/rtl/spi_defines.v"
-
+//`include "/home/zeeshan/fyp/azadi/src/spi_host/rtl/spi_defines.v"
+//`include "spi_defines.v"
 module spi_top(
 
-  input clk_i,
-  input rst_ni,
+  input logic clk_i,
+  input logic rst_ni,
 
   input  tlul_pkg::tl_h2d_t tl_i,
   output tlul_pkg::tl_d2h_t tl_o,
 
   // SPI signals                  
-  output        intr_rx_o,
-  output        intr_tx_o,                   
-  output          [`SPI_SS_NB-1:0] ss_o,        
-  output                           sclk_o,      
-  output                           sd_o,       
-  input                            sd_i      
+  output logic    intr_rx_o,
+  output logic    intr_tx_o,                   
+  output logic    [`SPI_SS_NB-1:0] ss_o,        
+  output logic                     sclk_o,      
+  output logic                     sd_o,
+  output logic                     sd_oe,       
+  input  logic                     sd_i      
 
 );
 
@@ -49,6 +50,7 @@ spi_core spi_host(
   .ss_o        (ss_o),         // slave select
   .sclk_o      (sclk_o),       // serial clock
   .sd_o        (sd_o),       // master out slave in
+  .sd_oe       (sd_oe),
   .sd_i        (sd_i)     // master in slave out
 );
 
@@ -72,4 +74,4 @@ tlul_adapter_reg #(
   .error_i (err)
 );
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/hw/ip/tlul/rtl/tlul_adapter_host.sv b/hw/ip/tlul/rtl/tlul_adapter_host.sv
deleted file mode 100644
index 934e7b71..00000000
--- a/hw/ip/tlul/rtl/tlul_adapter_host.sv
+++ /dev/null
@@ -1,173 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// tlul_adapter (Host adapter) converts basic req/grant/rvalid into TL-UL interface. If
-// MAX_REQS == 1 it is purely combinational logic. If MAX_REQS > 1 flops are required.
-//
-// The host driving the adapter is responsible for ensuring it doesn't have more requests in flight
-// than the specified MAX_REQS.
-//
-// The outgoing address is always word aligned. The access size is always the word size (as
-// specified by TL_DW). For write accesses that occupy all lanes the operation is PutFullData,
-// otherwise it is PutPartialData, mask is generated from be_i. For reads all lanes are enabled as
-// required by TL-UL (every bit in mask set).
-//
-// When MAX_REQS > 1 tlul_adapter_host does not do anything to order responses from the TL-UL
-// interface which could return them out of order. It is the host's responsibility to either only
-// have outstanding requests to an address space it knows will return responses in order or to not
-// care about out of order responses (note that if read data is returned out of order there is no
-// way to determine this).
-
-`include "prim_assert.sv"
-
-module tlul_adapter_host import tlul_pkg::*; #(
-  parameter int unsigned MAX_REQS = 2
-) (
-  input clk_i,
-  input rst_ni,
-
-  input                              req_i,
-  output logic                       gnt_o,
-  input  logic [top_pkg::TL_AW-1:0]  addr_i,
-  input  logic                       we_i,
-  input  logic [top_pkg::TL_DW-1:0]  wdata_i,
-  input  logic [top_pkg::TL_DBW-1:0] be_i,
-  input  tl_type_e                   type_i,
-
-  output logic                       valid_o,
-  output logic [top_pkg::TL_DW-1:0]  rdata_o,
-  output logic                       err_o,
-  output logic                       intg_err_o,
-
-  output tl_h2d_t                    tl_o,
-  input  tl_d2h_t                    tl_i
-);
-  localparam int WordSize = $clog2(top_pkg::TL_DBW);
-
-  logic [top_pkg::TL_AIW-1:0] tl_source;
-  logic [top_pkg::TL_DBW-1:0] tl_be;
-  tl_h2d_t                    tl_out;
-
-  if (MAX_REQS == 1) begin : g_single_req
-    assign tl_source = '0;
-  end else begin : g_multiple_reqs
-    localparam int ReqNumW  = $clog2(MAX_REQS);
-    localparam int unsigned MaxSource = MAX_REQS - 1;
-
-    logic [ReqNumW-1:0] source_d;
-    logic [ReqNumW-1:0] source_q;
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        source_q <= '0;
-      end else begin
-        source_q <= source_d;
-      end
-    end
-
-    always_comb begin
-      source_d = source_q;
-
-      if (req_i && gnt_o) begin
-        if (source_q == MaxSource[ReqNumW-1:0]) begin
-          source_d = '0;
-        end else  begin
-          source_d = source_q + 1;
-        end
-      end
-    end
-
-    assign tl_source = top_pkg::TL_AIW'(source_q);
-  end
-
-  // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
-  // bits set. For writes the supplied be_i is used as the mask.
-  assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
-
-  assign tl_out = '{
-    a_valid:   req_i,
-    a_opcode:  (~we_i) ? Get           :
-               (&be_i) ? PutFullData   :
-                         PutPartialData,
-    a_param:   3'h0,
-    a_size:    top_pkg::TL_SZW'(WordSize),
-    a_mask:    tl_be,
-    a_source:  tl_source,
-    a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
-    a_data:    wdata_i,
-    a_user:    '{default: '0, tl_type: type_i},
-    d_ready:   1'b1
-  };
-
-  tlul_cmd_intg_gen u_cmd_intg_gen (
-    .tl_i(tl_out),
-    .tl_o(tl_o)
-  );
-
-  assign gnt_o   = tl_i.a_ready;
-
-  assign valid_o = tl_i.d_valid;
-  assign rdata_o = tl_i.d_data;
-
-  logic intg_err;
-  tlul_rsp_intg_chk u_rsp_chk (
-    .tl_i,
-    .err_o(intg_err)
-  );
-
-  logic intg_err_q;
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      intg_err_q <= '0;
-    end else if (intg_err) begin
-      intg_err_q <= 1'b1;
-    end
-  end
-
-  // err_o is transactional.  This allows the host to continue
-  // debug without receiving an endless stream of errors.
-  assign err_o   = tl_i.d_error | intg_err;
-
-  // intg_err_o is permanent once detected, and should be used
-  // to trigger alerts
-  assign intg_err_o = intg_err_q | intg_err;
-
-  // Addresses are assumed to be word-aligned, and the bottom bits are ignored
-  logic unused_addr_bottom_bits;
-  assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
-
-  // Explicitly ignore unused fields of tl_i
-  logic unused_tl_i_fields;
-  assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
-                                tl_i.d_size, tl_i.d_source, tl_i.d_sink,
-                                tl_i.d_user};
-
-`ifdef INC_ASSERT
-  localparam int OutstandingReqCntW =
-    (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
-
-  logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
-  logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
-
-  always_comb begin
-    outstanding_reqs_d = outstanding_reqs_q;
-
-    if ((req_i && gnt_o) && !valid_o) begin
-      outstanding_reqs_d = outstanding_reqs_q + 1;
-    end else if (!(req_i && gnt_o) && valid_o) begin
-      outstanding_reqs_d = outstanding_reqs_q - 1;
-    end
-  end
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      outstanding_reqs_q <= '0;
-    end else begin
-      outstanding_reqs_q <= outstanding_reqs_d;
-    end
-  end
-
-  `ASSERT(DontExceeedMaxReqs, req_i |-> outstanding_reqs_d <= MAX_REQS)
-`endif
-endmodule
diff --git a/hw/ip/tlul/rtl/tlul_adapter_reg.sv b/hw/ip/tlul/rtl/tlul_adapter_reg.sv
index 3c0be45b..a7c8008b 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_reg.sv
+++ b/hw/ip/tlul/rtl/tlul_adapter_reg.sv
@@ -1,21 +1,10 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-`include "prim_assert.sv"
-
-/**
- * Tile-Link UL adapter for Register interface
- */
-
 module tlul_adapter_reg import tlul_pkg::*; #(
-  parameter  bit EnableDataIntgGen = 1'b0,
   parameter  int RegAw = 8,
   parameter  int RegDw = 32, // Shall be matched with TL_DW
   localparam int RegBw = RegDw/8
 ) (
-  input clk_i,
-  input rst_ni,
+  input logic clk_i,
+  input logic rst_ni,
 
   // TL-UL interface
   input  tl_h2d_t tl_i,
@@ -27,8 +16,8 @@ module tlul_adapter_reg import tlul_pkg::*; #(
   output logic [RegAw-1:0] addr_o,
   output logic [RegDw-1:0] wdata_o,
   output logic [RegBw-1:0] be_o,
-  input        [RegDw-1:0] rdata_i,
-  input                    error_i
+  input  logic      [RegDw-1:0] rdata_i,
+  input  logic                  error_i
 );
 
   localparam int IW  = $bits(tl_i.a_source);
@@ -41,12 +30,12 @@ module tlul_adapter_reg import tlul_pkg::*; #(
   logic             error, err_internal;
 
   logic addr_align_err;     // Size and alignment
-  logic malformed_meta_err; // User signal format error or unsupported
+//  logic malformed_meta_err; // User signal format error or unsupported
   logic tl_err;             // Common TL-UL error checker
 
   logic [IW-1:0]  reqid;
   logic [SZW-1:0] reqsz;
-  tl_d_op_e       rspop;
+  tlul_pkg::tl_d_m_op       rspop;
 
   logic rd_req, wr_req;
 
@@ -58,15 +47,10 @@ module tlul_adapter_reg import tlul_pkg::*; #(
 
   assign we_o    = wr_req & ~err_internal;
   assign re_o    = rd_req & ~err_internal;
+  assign addr_o  = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align
   assign wdata_o = tl_i.a_data;
   assign be_o    = tl_i.a_mask;
 
-  if (RegAw <= 2) begin : gen_only_one_reg
-    assign addr_o  = '0;
-  end else begin : gen_more_regs
-    assign addr_o  = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align
-  end
-
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni)    outstanding <= 1'b0;
     else if (a_ack) outstanding <= 1'b1;
@@ -91,23 +75,11 @@ module tlul_adapter_reg import tlul_pkg::*; #(
       rdata  <= '0;
       error <= 1'b0;
     end else if (a_ack) begin
-      rdata <= (error_i || err_internal || wr_req) ? '1 : rdata_i;
+      rdata <= (err_internal) ? '1 : rdata_i;
       error <= error_i | err_internal;
     end
   end
 
-  logic [DataIntgWidth-1:0] data_intg;
-  if (EnableDataIntgGen) begin : gen_data_intg
-    logic [DataMaxWidth-1:0] unused_data;
-
-    prim_secded_64_57_enc u_data_gen (
-      .in(DataMaxWidth'(rdata)),
-      .out({data_intg, unused_data})
-    );
-  end else begin : gen_tieoff_data_intg
-    assign data_intg = '0;
-  end
-
   assign tl_o = '{
     a_ready:  ~outstanding,
     d_valid:  outstanding,
@@ -117,17 +89,17 @@ module tlul_adapter_reg import tlul_pkg::*; #(
     d_source: reqid,
     d_sink:   '0,
     d_data:   rdata,
-    d_user:   '{default: '0, data_intg: data_intg},
-    d_error:  error
+    d_error: error
   };
 
   ////////////////////
   // Error Handling //
   ////////////////////
-  assign err_internal = addr_align_err | malformed_meta_err | tl_err ;
+  assign err_internal = addr_align_err | tl_err ;
 
-  // Don't allow unsupported values.
-  assign malformed_meta_err = tl_a_user_chk(tl_i.a_user);
+  // malformed_meta_err
+  //    Raised if not supported feature is turned on or user signal has malformed
+ // assign malformed_meta_err = (tl_i.a_user.parity_en == 1'b1);
 
   // addr_align_err
   //    Raised if addr isn't aligned with the size
@@ -144,13 +116,10 @@ module tlul_adapter_reg import tlul_pkg::*; #(
   end
 
   // tl_err : separate checker
-  tlul_err u_err (
-    .clk_i,
-    .rst_ni,
-    .tl_i,
+ tlul_err u_err (
+    .tl_i (tl_i),
     .err_o (tl_err)
   );
 
-  `ASSERT_INIT(MatchedWidthAssert, RegDw == top_pkg::TL_DW)
 
 endmodule
diff --git a/hw/ip/tlul/rtl/tlul_err.sv b/hw/ip/tlul/rtl/tlul_err.sv
index 8a9afbea..32d7b672 100644
--- a/hw/ip/tlul/rtl/tlul_err.sv
+++ b/hw/ip/tlul/rtl/tlul_err.sv
@@ -1,13 +1,6 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
 
 
-`include "prim_assert.sv"
-
 module tlul_err import tlul_pkg::*; (
-  input clk_i,
-  input rst_ni,
 
   input tl_h2d_t tl_i,
 
@@ -27,13 +20,8 @@ module tlul_err import tlul_pkg::*; (
   assign op_partial = (tl_i.a_opcode == PutPartialData);
   assign op_get     = (tl_i.a_opcode == Get);
 
-  // An instruction type transaction cannot be write
-  logic instr_wr_err;
-  assign instr_wr_err = (tl_i.a_user.tl_type == InstrType) &
-                        (op_full | op_partial);
-
   // Anything that doesn't fall into the permitted category, it raises an error
-  assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err;
+  assign err_o = ~(opcode_allowed & a_config_allowed);
 
   // opcode check
   assign opcode_allowed = (tl_i.a_opcode == PutFullData)
@@ -93,7 +81,6 @@ module tlul_err import tlul_pkg::*; (
                           & mask_chk
                           & (op_get | op_partial | fulldata_chk) ;
 
-  // Only 32 bit data width for current tlul_err
-  `ASSERT_INIT(dataWidthOnly32_A, DW == 32)
 
 endmodule
+
diff --git a/hw/ip/tlul/rtl/tlul_err_resp.sv b/hw/ip/tlul/rtl/tlul_err_resp.sv
index b1f31915..63d19276 100644
--- a/hw/ip/tlul/rtl/tlul_err_resp.sv
+++ b/hw/ip/tlul/rtl/tlul_err_resp.sv
@@ -1,20 +1,18 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
+
 // TL-UL error responder module, used by tlul_socket_1n to help response
 // to requests to no correct address space. Responses are always one cycle
 // after request with no stalling unless response is stuck on the way out.
-
+//`include "/home/sajjad/Shaheen-sv/src/buraq_core_top/ibex_core/tlul_pkg.sv"
 module tlul_err_resp (
-  input                     clk_i,
-  input                     rst_ni,
+  input  logic              clk_i,
+  input  logic              rst_ni,
   input  tlul_pkg::tl_h2d_t tl_h_i,
   output tlul_pkg::tl_d2h_t tl_h_o
 );
   import tlul_pkg::*;
 
-  tl_a_op_e                          err_opcode;
+  tlul_pkg::tl_a_m_op        err_opcode;
+//  tlul_pkg::tl_a_m_op    get;
   logic [$bits(tl_h_i.a_source)-1:0] err_source;
   logic [$bits(tl_h_i.a_size)-1:0]   err_size;
   logic                              err_req_pending, err_rsp_pending;
@@ -22,8 +20,8 @@ module tlul_err_resp (
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       err_req_pending <= 1'b0;
-      err_source      <= {top_pkg::TL_AIW{1'b0}};
-      err_opcode      <= Get;
+      err_source      <= {tlul_pkg::TL_AIW{1'b0}};
+      err_opcode      <= tlul_pkg::Get;
       err_size        <= '0;
     end else if (tl_h_i.a_valid && tl_h_o.a_ready) begin
       err_req_pending <= 1'b1;
@@ -42,8 +40,7 @@ module tlul_err_resp (
   assign tl_h_o.d_sink   = '0;
   assign tl_h_o.d_param  = '0;
   assign tl_h_o.d_size   = err_size;
-  assign tl_h_o.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
-  assign tl_h_o.d_user   = '0;
+  assign tl_h_o.d_opcode = (err_opcode == tlul_pkg::Get) ? AccessAckData : AccessAck;
   assign tl_h_o.d_error  = 1'b1;
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -56,10 +53,4 @@ module tlul_err_resp (
     end
   end
 
-  // Waive unused bits of tl_h_i
-  logic unused_tl_h;
-  assign unused_tl_h = &{1'b0,
-                         tl_h_i.a_param, tl_h_i.a_address, tl_h_i.a_mask,
-                         tl_h_i.a_data, tl_h_i.a_user, tl_h_i.d_ready};
-
 endmodule
diff --git a/hw/ip/tlul/rtl/tlul_fifo_sync.sv b/hw/ip/tlul/rtl/tlul_fifo_sync.sv
index a34835ec..d3a1c09b 100644
--- a/hw/ip/tlul/rtl/tlul_fifo_sync.sv
+++ b/hw/ip/tlul/rtl/tlul_fifo_sync.sv
@@ -1,7 +1,4 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
+
 // TL-UL fifo, used to add elasticity or an asynchronous clock crossing
 // to an TL-UL bus.  This instantiates two FIFOs, one for the request side,
 // and one for the response side.
@@ -9,13 +6,13 @@
 module tlul_fifo_sync #(
   parameter bit          ReqPass = 1'b1,
   parameter bit          RspPass = 1'b1,
-  parameter int unsigned ReqDepth = 2,
-  parameter int unsigned RspDepth = 2,
+  parameter int unsigned ReqDepth = 0,
+  parameter int unsigned RspDepth = 0,
   parameter int unsigned SpareReqW = 1,
   parameter int unsigned SpareRspW = 1
 ) (
-  input                     clk_i,
-  input                     rst_ni,
+  input  logic              clk_i,
+  input  logic              rst_ni,
   input  tlul_pkg::tl_h2d_t tl_h_i,
   output tlul_pkg::tl_d2h_t tl_h_o,
   output tlul_pkg::tl_h2d_t tl_d_o,
@@ -29,9 +26,9 @@ module tlul_fifo_sync #(
   // Put everything on the request side into one FIFO
   localparam int unsigned REQFIFO_WIDTH = $bits(tlul_pkg::tl_h2d_t) -2 + SpareReqW;
 
-  prim_fifo_sync #(.Width(REQFIFO_WIDTH), .Pass(ReqPass), .Depth(ReqDepth)) reqfifo (
-    .clk_i,
-    .rst_ni,
+  fifo_sync #(.Width(REQFIFO_WIDTH), .Pass(ReqPass), .Depth(ReqDepth)) reqfifo (
+    .clk_i (clk_i),
+    .rst_ni (rst_ni),
     .clr_i         (1'b0          ),
     .wvalid_i      (tl_h_i.a_valid),
     .wready_o      (tl_h_o.a_ready),
@@ -42,8 +39,8 @@ module tlul_fifo_sync #(
                      tl_h_i.a_address,
                      tl_h_i.a_mask   ,
                      tl_h_i.a_data   ,
-                     tl_h_i.a_user   ,
                      spare_req_i}),
+    .depth_o       (),
     .rvalid_o      (tl_d_o.a_valid),
     .rready_i      (tl_d_i.a_ready),
     .rdata_o       ({tl_d_o.a_opcode ,
@@ -53,18 +50,15 @@ module tlul_fifo_sync #(
                      tl_d_o.a_address,
                      tl_d_o.a_mask   ,
                      tl_d_o.a_data   ,
-                     tl_d_o.a_user   ,
-                     spare_req_o}),
-    .full_o        (),
-    .depth_o       ());
+                     spare_req_o}));
 
   // Put everything on the response side into the other FIFO
 
   localparam int unsigned RSPFIFO_WIDTH = $bits(tlul_pkg::tl_d2h_t) -2 + SpareRspW;
 
-  prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
-    .clk_i,
-    .rst_ni,
+  fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
+    .clk_i (clk_i),
+    .rst_ni (rst_ni),
     .clr_i         (1'b0          ),
     .wvalid_i      (tl_d_i.d_valid),
     .wready_o      (tl_d_o.d_ready),
@@ -74,10 +68,10 @@ module tlul_fifo_sync #(
                      tl_d_i.d_source,
                      tl_d_i.d_sink  ,
                      (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
-                                                                    {top_pkg::TL_DW{1'b0}} ,
-                     tl_d_i.d_user  ,
+                                                                    {tlul_pkg::TL_DW{1'b0}} ,
                      tl_d_i.d_error ,
                      spare_rsp_i}),
+    .depth_o       (),
     .rvalid_o      (tl_h_o.d_valid),
     .rready_i      (tl_h_i.d_ready),
     .rdata_o       ({tl_h_o.d_opcode,
@@ -86,10 +80,7 @@ module tlul_fifo_sync #(
                      tl_h_o.d_source,
                      tl_h_o.d_sink  ,
                      tl_h_o.d_data  ,
-                     tl_h_o.d_user  ,
                      tl_h_o.d_error ,
-                     spare_rsp_o}),
-    .full_o        (),
-    .depth_o       ());
+                     spare_rsp_o}));
 
 endmodule
diff --git a/hw/ip/tlul/rtl/tlul_host_adapter.sv b/hw/ip/tlul/rtl/tlul_host_adapter.sv
new file mode 100644
index 00000000..bb29f4a7
--- /dev/null
+++ b/hw/ip/tlul/rtl/tlul_host_adapter.sv
@@ -0,0 +1,95 @@
+// tlul_adapter (Host adapter) converts basic req/grant/rvalid into TL-UL interface. If
+// MAX_REQS == 1 it is purely combinational logic. If MAX_REQS > 1 flops are required.
+//
+// The host driving the adapter is responsible for ensuring it doesn't have more requests in flight
+// than the specified MAX_REQS.
+//
+// The outgoing address is always word aligned. The access size is always the word size (as
+// specified by TL_DW). For write accesses that occupy all lanes the operation is PutFullData,
+// otherwise it is PutPartialData, mask is generated from be_i. For reads all lanes are enabled as
+// required by TL-UL (every bit in mask set).
+//
+// When MAX_REQS > 1 tlul_adapter_host does not do anything to order responses from the TL-UL
+// interface which could return them out of order. It is the host's responsibility to either only
+// have outstanding requests to an address space it knows will return responses in order or to not
+// care about out of order responses (note that if read data is returned out of order there is no
+// way to determine this).
+
+module tlul_host_adapter #(
+    parameter int unsigned MAX_REQS = 1
+) (
+    input logic clk_i,
+    input logic rst_ni,
+// interface with host agent 
+    input                               req_i,
+    output logic                        gnt_o,
+    input logic [tlul_pkg::TL_AW-1:0]  addr_i,
+    input logic                         we_i,
+    input logic [tlul_pkg::TL_DW-1:0]  wdata_i,
+    input logic [tlul_pkg::TL_DBW-1:0] be_i,
+    output logic                        valid_o,
+    output logic [tlul_pkg::TL_DW-1:0] rdata_o,
+    output logic                        err_o,
+// interface with other tilelink agents or tlul interface
+    output tlul_pkg::tl_h2d_t          tl_h_c_a, // tilelink host channel A
+    input  tlul_pkg::tl_d2h_t          tl_h_c_d  // tilelink host channel D
+);
+
+    localparam int WordSize = $clog2(tlul_pkg::TL_DBW);
+
+    logic [tlul_pkg::TL_AIW-1:0] tl_source;
+    logic [tlul_pkg::TL_DBW-1:0] tl_be;
+
+    if(MAX_REQS == 1) begin
+        assign tl_source = '0;
+    end else begin
+        localparam int ReqNumW = $clog2(MAX_REQS);
+        logic [ReqNumW-1:0] source_d, source_q;
+
+        always_ff @(posedge clk_i) begin
+            if(!rst_ni) begin
+                source_q <= '0;
+            end else begin
+                source_q <= source_d;
+            end
+        end
+    
+
+        always_comb begin
+            source_d = source_q;
+
+            if(req_i && gnt_o) begin
+                if(source_q == MAX_REQS -1) source_d = '0;
+                else source_d = source_q + 1;
+            end
+        end
+        assign tl_source = tlul_pkg::TL_AIW'(source_q);
+    end
+
+// For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
+// bits set. For writes the supplied be_i is used as the mask.
+    assign tl_be = ~we_i ? {tlul_pkg::TL_DBW{1'b1}} : be_i;
+
+    assign tl_h_c_a = '{
+        a_valid:    req_i,
+        a_opcode:   (~we_i) ? tlul_pkg::Get         :   
+                    (&be_i) ? tlul_pkg::PutFullData :
+                              tlul_pkg::PutPartialData,
+        a_param:    3'h0,
+        a_size:     tlul_pkg::TL_SZW'(WordSize),
+        a_mask:     tl_be,
+        a_source:   tl_source,
+        a_address:  {addr_i[31:WordSize], {WordSize{1'b0}}},
+        a_data:     wdata_i,
+        d_ready:    1'b1
+    };
+
+    assign gnt_o = tl_h_c_d.a_ready;
+    //assign rdata_0 = tl_h_c_d.d_data;
+    assign err_o   = tl_h_c_d.d_error;
+    assign valid_o = tl_h_c_d.d_valid;
+    logic [31:0] rddata;
+    assign rddata = tl_h_c_d.d_data;
+    assign rdata_o = rddata;
+
+endmodule
\ No newline at end of file
diff --git a/hw/ip/tlul/rtl/tlul_pkg.sv b/hw/ip/tlul/rtl/tlul_pkg.sv
index 8c55992d..9da373f2 100644
--- a/hw/ip/tlul/rtl/tlul_pkg.sv
+++ b/hw/ip/tlul/rtl/tlul_pkg.sv
@@ -1,186 +1,120 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-
 package tlul_pkg;
 
-  // this can be either PPC or BINTREE
-  // there is no functional difference, but timing and area behavior is different
-  // between the two instances. PPC can result in smaller implementations when timing
-  // is not critical, whereas BINTREE is favorable when timing pressure is high (but this
-  // may also result in a larger implementation). on FPGA targets, BINTREE is favorable
-  // both in terms of area and timing.
-  parameter ArbiterImpl = "PPC";
-
-  typedef enum logic [2:0] {
-    PutFullData    = 3'h 0,
-    PutPartialData = 3'h 1,
-    Get            = 3'h 4
-  } tl_a_op_e;
-
-  typedef enum logic [2:0] {
-    AccessAck     = 3'h 0,
-    AccessAckData = 3'h 1
-  } tl_d_op_e;
-
-  typedef enum logic [2:0] {
-    InstrEn       = 3'b101,
-    InstrDis      = 3'b010
-  } tl_instr_en_e;
-
-  // used for intermodule connections
-  typedef tl_instr_en_e tl_instr_en_t;
-
-  typedef enum logic [1:0] {
-    InstrType     = 2'b01,
-    DataType      = 2'b10
-  } tl_type_e;
-
-  parameter int H2DCmdMaxWidth  = 57;
-  parameter int H2DCmdIntgWidth = 7;
-  parameter int H2DCmdFullWidth = H2DCmdMaxWidth + H2DCmdIntgWidth;
-  parameter int D2HRspMaxWidth  = 57;
-  parameter int D2HRspIntgWidth = 7;
-  parameter int D2HRspFullWidth = D2HRspMaxWidth + D2HRspIntgWidth;
-  parameter int DataMaxWidth    = 57;
-  parameter int DataIntgWidth   = 7;
-  parameter int DataFullWidth   = DataMaxWidth + DataIntgWidth;
-
-  typedef struct packed {
-    logic [4:0]                 rsvd;
-    tl_type_e                   tl_type;
-    logic [H2DCmdIntgWidth-1:0] cmd_intg;
-    logic [DataIntgWidth-1:0]   data_intg;
-  } tl_a_user_t;
-
-  parameter tl_a_user_t TL_A_USER_DEFAULT = '{
-    rsvd: '0,
-    tl_type: DataType,
-    cmd_intg:  '0,
-    data_intg: '0
-  };
-
-  typedef struct packed {
-    tl_type_e                     tl_type;
-    logic   [top_pkg::TL_AW-1:0]  addr;
-    tl_a_op_e                     opcode;
-    logic  [top_pkg::TL_DBW-1:0]  mask;
-  } tl_h2d_cmd_intg_t;
-
-  typedef struct packed {
-    logic                         a_valid;
-    tl_a_op_e                     a_opcode;
-    logic                  [2:0]  a_param;
-    logic  [top_pkg::TL_SZW-1:0]  a_size;
-    logic  [top_pkg::TL_AIW-1:0]  a_source;
-    logic   [top_pkg::TL_AW-1:0]  a_address;
-    logic  [top_pkg::TL_DBW-1:0]  a_mask;
-    logic   [top_pkg::TL_DW-1:0]  a_data;
-    tl_a_user_t                   a_user;
-
-    logic                         d_ready;
-  } tl_h2d_t;
-
-  localparam tl_h2d_t TL_H2D_DEFAULT = '{
-    d_ready:  1'b1,
-    a_opcode: tl_a_op_e'('0),
-    a_user:   tl_a_user_t'('0),
-    default:  '0
-  };
-
-  typedef struct packed {
-    logic [D2HRspIntgWidth-1:0]    rsp_intg;
-    logic [DataIntgWidth-1:0]      data_intg;
-  } tl_d_user_t;
-
-  parameter tl_d_user_t TL_D_USER_DEFAULT = '{
-    rsp_intg: '0,
-    data_intg: '0
-  };
-
-  typedef struct packed {
-    logic                         d_valid;
-    tl_d_op_e                     d_opcode;
-    logic                  [2:0]  d_param;
-    logic  [top_pkg::TL_SZW-1:0]  d_size;   // Bouncing back a_size
-    logic  [top_pkg::TL_AIW-1:0]  d_source;
-    logic  [top_pkg::TL_DIW-1:0]  d_sink;
-    logic   [top_pkg::TL_DW-1:0]  d_data;
-    tl_d_user_t                   d_user;
-    logic                         d_error;
-
-    logic                         a_ready;
-
-  } tl_d2h_t;
-
-  typedef struct packed {
-    tl_d_op_e                     opcode;
-    logic  [top_pkg::TL_SZW-1:0]  size;
-    // Temporarily removed because source changes throughout the fabric
-    // and thus cannot be used for end-to-end checking.
-    // A different PR will propose a work-around (a hoaky one) to see if
-    // it gets the job done.
-    //logic  [top_pkg::TL_AIW-1:0]  source;
-    logic                         error;
-  } tl_d2h_rsp_intg_t;
-
-  localparam tl_d2h_t TL_D2H_DEFAULT = '{
-    a_ready:  1'b1,
-    d_opcode: tl_d_op_e'('0),
-    d_user:   tl_d_user_t'(0),
-    default:  '0
-  };
-
-  // Check user for unsupported values
-  function automatic logic tl_a_user_chk(tl_a_user_t user);
-    logic malformed_err;
-    logic unused_user;
-    unused_user = |user;
-    malformed_err = ~(user.tl_type inside {InstrType, DataType});
-    return malformed_err;
-  endfunction // tl_a_user_chk
-
-  // extract variables used for command checking
-  function automatic tl_h2d_cmd_intg_t extract_h2d_cmd_intg(tl_h2d_t tl);
-    tl_h2d_cmd_intg_t payload;
-    logic unused_tlul;
-    unused_tlul = ^tl;
-    payload.addr = tl.a_address;
-    payload.opcode = tl.a_opcode;
-    payload.mask = tl.a_mask;
-    payload.tl_type = tl.a_user.tl_type;
-    return payload;
-  endfunction // extract_h2d_payload
 
-  // extract variables used for response checking
-  function automatic tl_d2h_rsp_intg_t extract_d2h_rsp_intg(tl_d2h_t tl);
-    tl_d2h_rsp_intg_t payload;
-    logic unused_tlul;
-    unused_tlul = ^tl;
-    payload.opcode = tl.d_opcode;
-    payload.size   = tl.d_size;
-    //payload.source = tl.d_source;
-    payload.error  = tl.d_error;
-    return payload;
-  endfunction // extract_d2h_rsp_intg
+    parameter ArbiterImpl = "PPC";
+function automatic integer _clog2(integer value);
+    integer result;
+    value = value - 1;
+    for (result = 0; value > 0; result = result + 1) begin
+      value = value >> 1;
+    end
+    return result;
+  endfunction
+
+
+  /**
+   * Math function: Number of bits needed to address |value| items.
+   *
+   *                  0        for value == 0
+   * vbits =          1        for value == 1
+   *         ceil(log2(value)) for value > 1
+   *
+   *
+   * The primary use case for this function is the definition of registers/arrays
+   * which are wide enough to contain |value| items.
+   *
+   * This function identical to $clog2() for all input values except the value 1;
+   * it could be considered an "enhanced" $clog2() function.
+   *
+   *
+   * Example 1:
+   *   parameter Items = 1;
+   *   localparam ItemsWidth = vbits(Items); // 1
+   *   logic [ItemsWidth-1:0] item_register; // items_register is now [0:0]
+   *
+   * Example 2:
+   *   parameter Items = 64;
+   *   localparam ItemsWidth = vbits(Items); // 6
+   *   logic [ItemsWidth-1:0] item_register; // items_register is now [5:0]
+   *
+   * Note: If you want to store the number "value" inside a register, you need
+   * a register with size vbits(value + 1), since you also need to store
+   * the number 0.
+   *
+   * Example 3:
+   *   logic [vbits(64)-1:0]     store_64_logic_values; // width is [5:0]
+   *   logic [vbits(64 + 1)-1:0] store_number_64;       // width is [6:0]
+   */
+  function automatic integer vbits(integer value);
+`ifdef XCELIUM
+    // The use of system functions was not allowed here in Verilog-2001, but is
+    // valid since (System)Verilog-2005, which is also when $clog2() first
+    // appeared.
+    // Xcelium < 19.10 does not yet support the use of $clog2() here, fall back
+    // to an implementation without a system function. Remove this workaround
+    // if we require a newer Xcelium version.
+    // See #2579 and #2597.
+    return (value == 1) ? 1 : prim_util_pkg::_clog2(value);
+`else
+    return (value == 1) ? 1 : $clog2(value);
+`endif
+  endfunction
+
+    localparam int TL_AW=32;
+    localparam int TL_DW=32;
+    localparam int TL_AIW=8;
+    localparam int TL_DIW=1;
+    localparam int TL_DBW=(TL_DW>>3);
+    localparam int TL_SZW=$clog2($clog2(TL_DBW)+1);
+
+// opcodes for channel D messages/operations defined in official TileLink spec
+    typedef enum logic [2:0] {
+        PutFullData     = 3'h0,
+        PutPartialData  = 3'h1,
+        Get             = 3'h4
+    } tl_a_m_op;
+// opcodes for channel D messages/operations defined in official TileLink spec
+    typedef enum logic [2:0] {
+        AccessAck     = 3'h0,
+        AccessAckData = 3'h1
+    } tl_d_m_op;
+
+    typedef struct packed {
+        logic                        a_valid;
+        tl_a_m_op                    a_opcode;
+        logic           [2:0]        a_param;
+        logic           [TL_SZW-1:0] a_size;
+        logic           [TL_AIW-1:0] a_source;
+        logic           [TL_AW-1:0]  a_address;
+        logic           [TL_DBW-1:0] a_mask;
+        logic           [TL_DW-1:0]  a_data;
+        logic                        d_ready;
+    } tl_h2d_t;
+
+    localparam tl_h2d_t TL_H2D_DEFAULT = '{
+        d_ready:  1'b1,
+        a_opcode: tl_a_m_op'('0),
+        default:  '0
+    };
+
+    typedef struct packed {
+        logic                   d_valid;
+        tl_d_m_op               d_opcode;
+        logic             [2:0] d_param;
+        logic      [TL_SZW-1:0] d_size;
+        logic      [TL_AIW-1:0] d_source;
+        logic      [TL_DIW-1:0] d_sink;
+        logic      [TL_DW-1:0]  d_data;
+        logic                   d_error;
+        logic                   a_ready;
+    } tl_d2h_t;
+
+    localparam tl_d2h_t TL_D2H_DEFAULT = '{
+        a_ready:  1'b1,
+        d_opcode: tl_d_m_op'('0),
+        default:  '0
+    };
 
-  // calculate ecc for command checking
-  function automatic logic [H2DCmdIntgWidth-1:0] get_cmd_intg(tl_h2d_t tl);
-    logic [H2DCmdIntgWidth-1:0] cmd_intg;
-    logic [H2DCmdMaxWidth-1:0] unused_cmd_payload;
-    tl_h2d_cmd_intg_t cmd;
-    cmd = extract_h2d_cmd_intg(tl);
-    {cmd_intg, unused_cmd_payload} = prim_secded_pkg::prim_secded_64_57_enc(H2DCmdMaxWidth'(cmd));
-   return cmd_intg;
-  endfunction  // get_cmd_intg
 
-  // calculate ecc for data checking
-  function automatic logic [DataIntgWidth-1:0] get_data_intg(logic [top_pkg::TL_DW-1:0] data);
-    logic [DataIntgWidth-1:0] data_intg;
-    logic [top_pkg::TL_DW-1:0] unused_data;
-    {data_intg, unused_data} = prim_secded_pkg::prim_secded_39_32_enc(data);
-    return data_intg;
-  endfunction  // get_data_intg
 
 endpackage
diff --git a/hw/ip/tlul/rtl/tlul_socket_1n.sv b/hw/ip/tlul/rtl/tlul_socket_1n.sv
index 9e444cee..0e03b883 100644
--- a/hw/ip/tlul/rtl/tlul_socket_1n.sv
+++ b/hw/ip/tlul/rtl/tlul_socket_1n.sv
@@ -1,7 +1,4 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
+
 // TL-UL socket 1:N module
 //
 // configuration settings
@@ -34,7 +31,6 @@
 //
 // The maximum value of N is 15
 
-`include "prim_assert.sv"
 
 module tlul_socket_1n #(
   parameter int unsigned  N         = 4,
@@ -48,17 +44,15 @@ module tlul_socket_1n #(
   parameter bit [N*4-1:0] DRspDepth = {N{4'h2}},
   localparam int unsigned NWD       = $clog2(N+1) // derived parameter
 ) (
-  input                     clk_i,
-  input                     rst_ni,
+  input  logic                   clk_i,
+  input  logic                   rst_ni,
   input  tlul_pkg::tl_h2d_t tl_h_i,
   output tlul_pkg::tl_d2h_t tl_h_o,
   output tlul_pkg::tl_h2d_t tl_d_o    [N],
   input  tlul_pkg::tl_d2h_t tl_d_i    [N],
-  input  [NWD-1:0]          dev_select_i
+  input  logic [NWD-1:0]          dev_select_i
 );
 
-  `ASSERT_INIT(maxN, N < 32)
-
   // Since our steering is done after potential FIFOing, we need to
   // shove our device select bits into spare bits of reqfifo
 
@@ -92,7 +86,7 @@ module tlul_socket_1n #(
   // We need to keep track of how many requests are outstanding,
   // and to which device. New requests are compared to this and
   // stall until that number is zero.
-  localparam int MaxOutstanding = 2**top_pkg::TL_AIW; // Up to 256 ounstanding
+  localparam int MaxOutstanding = 4**tlul_pkg::TL_AIW; // Up to 256 ounstanding
   localparam int OutstandingW = $clog2(MaxOutstanding+1);
   logic [OutstandingW-1:0] num_req_outstanding;
   logic [NWD-1:0]          dev_select_outstanding;
@@ -108,7 +102,6 @@ module tlul_socket_1n #(
       dev_select_outstanding <= '0;
     end else if (accept_t_req) begin
       if (!accept_t_rsp) begin
-        `ASSERT_I(NotOverflowed_A, num_req_outstanding <= MaxOutstanding)
         num_req_outstanding <= num_req_outstanding + 1'b1;
       end
       dev_select_outstanding <= dev_select_t;
@@ -138,7 +131,6 @@ module tlul_socket_1n #(
     assign tl_u_o[i].a_address = tl_t_o.a_address;
     assign tl_u_o[i].a_mask    = tl_t_o.a_mask;
     assign tl_u_o[i].a_data    = tl_t_o.a_data;
-    assign tl_u_o[i].a_user    = tl_t_o.a_user;
   end
 
   tlul_pkg::tl_d2h_t tl_t_p ;
@@ -170,7 +162,6 @@ module tlul_socket_1n #(
   assign tl_t_i.d_source = tl_t_p.d_source;
   assign tl_t_i.d_sink   = tl_t_p.d_sink  ;
   assign tl_t_i.d_data   = tl_t_p.d_data  ;
-  assign tl_t_i.d_user   = tl_t_p.d_user  ;
   assign tl_t_i.d_error  = tl_t_p.d_error ;
 
 
@@ -209,10 +200,9 @@ module tlul_socket_1n #(
   assign tl_u_o[N].a_address   = tl_t_o.a_address;
   assign tl_u_o[N].a_mask      = tl_t_o.a_mask;
   assign tl_u_o[N].a_data      = tl_t_o.a_data;
-  assign tl_u_o[N].a_user      = tl_t_o.a_user;
   tlul_err_resp err_resp (
-    .clk_i,
-    .rst_ni,
+    .clk_i      (clk_i),
+    .rst_ni     (rst_ni),
     .tl_h_i     (tl_u_o[N]),
     .tl_h_o     (tl_u_i[N]));
 
diff --git a/hw/ip/tlul/rtl/tlul_adapter_sram.sv b/hw/ip/tlul/rtl/tlul_sram_adapter.sv
similarity index 50%
rename from hw/ip/tlul/rtl/tlul_adapter_sram.sv
rename to hw/ip/tlul/rtl/tlul_sram_adapter.sv
index 2a71cb02..d1f822f8 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_sram.sv
+++ b/hw/ip/tlul/rtl/tlul_sram_adapter.sv
@@ -1,68 +1,47 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-`include "prim_assert.sv"
-
 /**
  * Tile-Link UL adapter for SRAM-like devices
  *
  * - Intentionally omitted BaseAddr in case of multiple memory maps are used in a SoC,
  *   it means that aliasing can happen if target device size in TL-UL crossbar is bigger
  *   than SRAM size
- * - At most one of EnableDataIntgGen / EnableDataIntgPt can be enabled. However it
- *   possible for both to be disabled.
- *   A module can neither generate an integrity response nor pass through any pre-existing
- *   integrity.  This might be the case for non-security critical memories where there is
- *   no stored integrity AND another entity upstream is already generating returning integrity.
- *   There is however no case where EnableDataIntgGen and EnableDataIntgPt are both true.
  */
-module tlul_adapter_sram import tlul_pkg::*; #(
-  parameter int SramAw            = 12,
-  parameter int SramDw            = 32, // Must be multiple of the TL width
-  parameter int Outstanding       = 1,  // Only one request is accepted
-  parameter bit ByteAccess        = 1,  // 1: true, 0: false
-  parameter bit ErrOnWrite        = 0,  // 1: Writes not allowed, automatically error
-  parameter bit ErrOnRead         = 0,  // 1: Reads not allowed, automatically error
-  parameter bit CmdIntgCheck      = 0,  // 1: Enable command integrity check
-  parameter bit EnableRspIntgGen  = 0,  // 1: Generate response integrity
-  parameter bit EnableDataIntgGen = 0,  // 1: Generate response data integrity
-  parameter bit EnableDataIntgPt  = 0,  // 1: Passthrough command/response data integrity
-  localparam int WidthMult        = SramDw / top_pkg::TL_DW,
-  localparam int IntgWidth        = tlul_pkg::DataIntgWidth * WidthMult,
-  localparam int DataOutW         = EnableDataIntgPt ? SramDw + IntgWidth : SramDw
+module tlul_sram_adapter #(
+  parameter int SramAw      = 12,
+  parameter int SramDw      = 32, // Must be multiple of the TL width
+  parameter int Outstanding = 1,  // Only one request is accepted
+  parameter bit ByteAccess  = 1,  // 1: true, 0: false
+  parameter bit ErrOnWrite  = 0,  // 1: Writes not allowed, automatically error
+  parameter bit ErrOnRead   = 0   // 1: Reads not allowed, automatically error
 ) (
-  input   clk_i,
-  input   rst_ni,
+  input   logic clk_i,
+  input   logic rst_ni,
 
   // TL-UL interface
-  input   tl_h2d_t          tl_i,
-  output  tl_d2h_t          tl_o,
-
-  // control interface
-  input   tl_instr_en_e     en_ifetch_i,
+  input   tlul_pkg::tl_h2d_t  tl_i,
+  output  tlul_pkg::tl_d2h_t  tl_o,
 
   // SRAM interface
-  output logic                req_o,
-  output tl_type_e            req_type_o,
-  input                       gnt_i,
-  output logic                we_o,
-  output logic [SramAw-1:0]   addr_o,
-  output logic [DataOutW-1:0] wdata_o,
-  output logic [DataOutW-1:0] wmask_o,
-  output logic                intg_error_o,
-  input        [DataOutW-1:0] rdata_i,
-  input                       rvalid_i,
-  input        [1:0]          rerror_i // 2 bit error [1]: Uncorrectable, [0]: Correctable
+  output logic              req_o,
+  input  logic              gnt_i,
+  output logic              we_o,
+  output logic [SramAw-1:0] addr_o,
+  output logic [SramDw-1:0] wdata_o,
+  output logic [SramDw-1:0] wmask_o,
+  input  logic [SramDw-1:0] rdata_i,
+  input  logic              rvalid_i,
+  input  logic [1:0]        rerror_i // 2 bit error [1]: Uncorrectable, [0]: Correctable
 );
 
+  import tlul_pkg::*;
+
   localparam int SramByte = SramDw/8;
-  localparam int DataBitWidth = prim_util_pkg::vbits(SramByte);
-  localparam int WoffsetWidth = (SramByte == top_pkg::TL_DBW) ? 1 :
-                                DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW);
+  localparam int DataBitWidth = tlul_pkg::vbits(SramByte);
+  localparam int WidthMult = SramDw / tlul_pkg::TL_DW;
+  localparam int WoffsetWidth = (SramByte == tlul_pkg::TL_DBW) ? 1 :
+                                DataBitWidth - tlul_pkg::vbits(tlul_pkg::TL_DBW);
 
   typedef struct packed {
-    logic [top_pkg::TL_DBW-1:0] mask ; // Byte mask within the TL-UL word
+    logic [tlul_pkg::TL_DBW-1:0] mask ; // Byte mask within the TL-UL word
     logic [WoffsetWidth-1:0]    woffset ; // Offset of the TL-UL word within the SRAM word
   } sram_req_t ;
 
@@ -75,14 +54,13 @@ module tlul_adapter_sram import tlul_pkg::*; #(
   typedef struct packed {
     req_op_e                    op ;
     logic                       error ;
-    logic [top_pkg::TL_SZW-1:0] size ;
-    logic [top_pkg::TL_AIW-1:0] source ;
+    logic [tlul_pkg::TL_SZW-1:0] size ;
+    logic [tlul_pkg::TL_AIW-1:0] source ;
   } req_t ;
 
   typedef struct packed {
-    logic [top_pkg::TL_DW-1:0] data ;
-    logic [DataIntgWidth-1:0]  data_intg ;
-    logic                      error ;
+    logic [SramDw-1:0] data ;
+    logic              error ;
   } rsp_t ;
 
   localparam int SramReqFifoWidth = $bits(sram_req_t) ;
@@ -106,9 +84,7 @@ module tlul_adapter_sram import tlul_pkg::*; #(
   rsp_t rspfifo_wdata,  rspfifo_rdata;
 
   logic error_internal; // Internal protocol error checker
-  logic intg_error;
   logic wr_attr_error;
-  logic instr_error;
   logic wr_vld_error;
   logic rd_vld_error;
   logic tlul_error;     // Error from `tlul_err` module
@@ -152,9 +128,7 @@ module tlul_adapter_sram import tlul_pkg::*; #(
     end
   end
 
-
-  tl_d2h_t tl_out;
-  assign tl_out = '{
+  assign tl_o = '{
       d_valid  : d_valid ,
       d_opcode : (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData,
       d_param  : '0,
@@ -163,21 +137,11 @@ module tlul_adapter_sram import tlul_pkg::*; #(
       d_sink   : 1'b0,
       d_data   : (d_valid && rspfifo_rvalid && reqfifo_rdata.op == OpRead)
                  ? rspfifo_rdata.data : '0,
-      d_user   : '{default: '1, data_intg: d_valid ? rspfifo_rdata.data_intg : '1},
       d_error  : d_valid && d_error,
 
       a_ready  : (gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready
   };
 
-
-  tlul_rsp_intg_gen #(
-    .EnableRspIntgGen(EnableRspIntgGen),
-    .EnableDataIntgGen(EnableDataIntgGen)
-  ) u_rsp_gen (
-    .tl_i(tl_out),
-    .tl_o
-  );
-
   // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter)
   // assemble response, including read response, write response, and error for unsupported stuff
 
@@ -185,93 +149,47 @@ module tlul_adapter_sram import tlul_pkg::*; #(
   //    Generate request only when no internal error occurs. If error occurs, the request should be
   //    dropped and returned error response to the host. So, error to be pushed to reqfifo.
   //    In this case, it is assumed the request is granted (may cause ordering issue later?)
-  assign req_o      = tl_i.a_valid & reqfifo_wready & ~error_internal;
-  assign req_type_o = tl_i.a_user.tl_type;
-  assign we_o       = tl_i.a_valid & logic'(tl_i.a_opcode inside {PutFullData, PutPartialData});
-  assign addr_o     = (tl_i.a_valid) ? tl_i.a_address[DataBitWidth+:SramAw] : '0;
+  assign req_o    = tl_i.a_valid & reqfifo_wready & ~error_internal;
+  assign we_o     = tl_i.a_valid & logic'(tl_i.a_opcode inside {PutFullData, PutPartialData});
+  assign addr_o   = (tl_i.a_valid) ? tl_i.a_address[DataBitWidth+:SramAw] : '0;
 
   // Support SRAMs wider than the TL-UL word width by mapping the parts of the
   // TL-UL address which are more fine-granular than the SRAM width to the
   // SRAM write mask.
   logic [WoffsetWidth-1:0] woffset;
-  if (top_pkg::TL_DW != SramDw) begin : gen_wordwidthadapt
-    assign woffset = tl_i.a_address[DataBitWidth-1:prim_util_pkg::vbits(top_pkg::TL_DBW)];
+  if (tlul_pkg::TL_DW != SramDw) begin : gen_wordwidthadapt
+    assign woffset = tl_i.a_address[DataBitWidth-1:tlul_pkg::vbits(tlul_pkg::TL_DBW)];
   end else begin : gen_no_wordwidthadapt
     assign woffset = '0;
   end
 
-  // The size of the data/wmask depends on whether passthrough integrity is enabled.
-  // If passthrough integrity is enabled, the data is concatenated with the integrity passed through
-  // the user bits.  Otherwise, it is the data only.
-  localparam int DataWidth = EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW;
-
-  // Final combined wmask / wdata
-  logic [WidthMult-1:0][DataWidth-1:0] wmask_combined;
-  logic [WidthMult-1:0][DataWidth-1:0] wdata_combined;
-
-  // Original tlul portion
-  logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wmask_int;
-  logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wdata_int;
-
-  // Integrity portion
-  logic [WidthMult-1:0][DataIntgWidth-1:0] wmask_intg;
-  logic [WidthMult-1:0][DataIntgWidth-1:0] wdata_intg;
+  // Convert byte mask to SRAM bit mask for writes, and only forward valid data
+  logic [WidthMult-1:0][tlul_pkg::TL_DW-1:0] wmask_int;
+  logic [WidthMult-1:0][tlul_pkg::TL_DW-1:0] wdata_int;
 
   always_comb begin
     wmask_int = '0;
     wdata_int = '0;
 
     if (tl_i.a_valid) begin
-      for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
+      for (int i = 0 ; i < tlul_pkg::TL_DW/8 ; i++) begin
         wmask_int[woffset][8*i +: 8] = {8{tl_i.a_mask[i]}};
         wdata_int[woffset][8*i +: 8] = (tl_i.a_mask[i] && we_o) ? tl_i.a_data[8*i+:8] : '0;
       end
     end
   end
 
-  // TODO: The logic below is incomplete.  If the adapter detects a write is NOT
-  // the full word, it must read back the other parts of the data from memory and
-  // re-generate the integrity.
-  // Since that will cause back-pressure to the upstream agent and likely substantial
-  // change into this module, it is left to a different PR.
-  always_comb begin
-    wmask_intg  = '0;
-    wdata_intg  = '0;
-
-    if (tl_i.a_valid) begin
-      wmask_intg[woffset] = '1;
-      wdata_intg[woffset] = tl_i.a_user.data_intg;
-    end
-  end
-
-  for (genvar i = 0; i < WidthMult; i++) begin : gen_write_output
-    if (EnableDataIntgPt) begin : gen_combined_output
-      assign wmask_combined[i] = {wmask_intg[i], wmask_int[i]};
-      assign wdata_combined[i] = {wdata_intg[i], wdata_int[i]};
-    end else begin : gen_ft_output
-      logic unused_w;
-      assign wmask_combined[i] = wmask_int[i];
-      assign wdata_combined[i] = wdata_int[i];
-      assign unused_w = |wmask_intg & |wdata_intg;
-    end
-  end
-
-  assign wmask_o = wmask_combined;
-  assign wdata_o = wdata_combined;
-
+  assign wmask_o = wmask_int;
+  assign wdata_o = wdata_int;
 
   // Begin: Request Error Detection
 
   // wr_attr_error: Check if the request size,mask are permitted.
   //    Basic check of size, mask, addr align is done in tlul_err module.
   //    Here it checks any partial write if ByteAccess isn't allowed.
-  assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData)
-                         ? ((ByteAccess == 0) ? (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0)
-                         : 1'b0;
-
-  // An instruction type transaction is only valid if en_ifetch is enabled
-  assign instr_error = tl_i.a_user.tl_type == InstrType &
-                       en_ifetch_i == InstrDis;
+  assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData) ?
+                         (ByteAccess == 0) ? (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0 :
+                         1'b0;
 
   if (ErrOnWrite == 1) begin : gen_no_writes
     assign wr_vld_error = tl_i.a_opcode != Get;
@@ -285,40 +203,12 @@ module tlul_adapter_sram import tlul_pkg::*; #(
     assign rd_vld_error = 1'b0;
   end
 
-  if (CmdIntgCheck) begin : gen_cmd_intg_check
-    tlul_cmd_intg_chk u_cmd_intg_chk (
-      .tl_i,
-      .err_o (intg_error)
-    );
-  end else begin : gen_no_cmd_intg_check
-    assign intg_error = '0;
-  end
-
-
-  // permanently latch integrity error until reset
-  logic intg_error_q;
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      intg_error_q <= '0;
-    end else if (intg_error) begin
-      intg_error_q <= 1'b1;
-    end
-  end
-
-  // integrity error output is permanent and should be used for alert generation
-  // or other downstream effects
-  assign intg_error_o = intg_error | intg_error_q;
-
   tlul_err u_err (
-    .clk_i,
-    .rst_ni,
-    .tl_i,
+    .tl_i   (tl_i),
     .err_o (tlul_error)
   );
 
-  // error return is transactional and thus does not used the "latched" intg_err signal
-  assign error_internal = wr_attr_error | wr_vld_error | rd_vld_error | instr_error |
-                          tlul_error    | intg_error;
+  assign error_internal = wr_attr_error | wr_vld_error | rd_vld_error | tlul_error;
   // End: Request Error Detection
 
   assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted
@@ -341,20 +231,15 @@ module tlul_adapter_sram import tlul_pkg::*; #(
   assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
 
   // Make sure only requested bytes are forwarded
-  logic [WidthMult-1:0][DataWidth-1:0] rdata;
-  logic [WidthMult-1:0][DataWidth-1:0] rmask;
-  logic [DataWidth-1:0] rdata_tlword;
-
-  // When passing through data integrity, we must feedback the entire
-  // read data, otherwise the stored integrity will not calculate correctly
-  if (EnableDataIntgPt) begin : gen_no_rmask
-    assign rmask = {DataOutW{|sramreqfifo_rdata.mask}};
-  end else begin : gen_rmask
-    always_comb begin
-      rmask = '0;
-      for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
-        rmask[sramreqfifo_rdata.woffset][8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}};
-      end
+  logic [WidthMult-1:0][tlul_pkg::TL_DW-1:0] rdata;
+  logic [WidthMult-1:0][tlul_pkg::TL_DW-1:0] rmask;
+  //logic [SramDw-1:0] rmask;
+  logic [tlul_pkg::TL_DW-1:0] rdata_tlword;
+
+  always_comb begin
+    rmask = '0;
+    for (int i = 0 ; i < tlul_pkg::TL_DW/8 ; i++) begin
+      rmask[sramreqfifo_rdata.woffset][8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}};
     end
   end
 
@@ -362,9 +247,8 @@ module tlul_adapter_sram import tlul_pkg::*; #(
   assign rdata_tlword = rdata[sramreqfifo_rdata.woffset];
 
   assign rspfifo_wdata  = '{
-    data      : rdata_tlword[top_pkg::TL_DW-1:0],
-    data_intg : EnableDataIntgPt ? rdata_tlword[DataWidth-1 -: DataIntgWidth] : '1,
-    error     : rerror_i[1] // Only care for Uncorrectable error
+    data : rdata_tlword,
+    error: rerror_i[1] // Only care for Uncorrectable error
   };
   assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
                         ? reqfifo_rready : 1'b0 ;
@@ -390,7 +274,7 @@ module tlul_adapter_sram import tlul_pkg::*; #(
   // oustanding as long as the outgoing ready is qualified with the acceptance
   // of the response in the same cycle.  Doing so however creates a path from
   // ready_i to ready_o, which may not be desireable.
-  prim_fifo_sync #(
+  fifo_sync #(
     .Width   (ReqFifoWidth),
     .Pass    (1'b0),
     .Depth   (Outstanding)
@@ -401,18 +285,17 @@ module tlul_adapter_sram import tlul_pkg::*; #(
     .wvalid_i(reqfifo_wvalid),
     .wready_o(reqfifo_wready),
     .wdata_i (reqfifo_wdata),
+    .depth_o (),
     .rvalid_o(reqfifo_rvalid),
     .rready_i(reqfifo_rready),
-    .rdata_o (reqfifo_rdata),
-    .full_o  (),
-    .depth_o ()
+    .rdata_o (reqfifo_rdata)
   );
 
   // sramreqfifo:
   //    While the ReqFIFO holds the request until it is sent back via TL-UL, the
   //    sramreqfifo only needs to hold the mask and word offset until the read
   //    data returns from memory.
-  prim_fifo_sync #(
+  fifo_sync #(
     .Width   (SramReqFifoWidth),
     .Pass    (1'b0),
     .Depth   (Outstanding)
@@ -423,11 +306,10 @@ module tlul_adapter_sram import tlul_pkg::*; #(
     .wvalid_i(sramreqfifo_wvalid),
     .wready_o(sramreqfifo_wready),
     .wdata_i (sramreqfifo_wdata),
+    .depth_o (),
     .rvalid_o(),
     .rready_i(sramreqfifo_rready),
-    .rdata_o (sramreqfifo_rdata),
-    .full_o  (),
-    .depth_o ()
+    .rdata_o (sramreqfifo_rdata)
   );
 
   // Rationale having #Outstanding depth in response FIFO.
@@ -436,7 +318,7 @@ module tlul_adapter_sram import tlul_pkg::*; #(
   //    back pressured, the response FIFO should store the returned data not to
   //    lose the data from the SRAM interface. Remember, SRAM interface doesn't
   //    have back-pressure signal such as read_ready.
-  prim_fifo_sync #(
+  fifo_sync #(
     .Width   (RspFifoWidth),
     .Pass    (1'b1),
     .Depth   (Outstanding)
@@ -447,35 +329,10 @@ module tlul_adapter_sram import tlul_pkg::*; #(
     .wvalid_i(rspfifo_wvalid),
     .wready_o(rspfifo_wready),
     .wdata_i (rspfifo_wdata),
+    .depth_o (),
     .rvalid_o(rspfifo_rvalid),
     .rready_i(rspfifo_rready),
-    .rdata_o (rspfifo_rdata),
-    .full_o  (),
-    .depth_o ()
+    .rdata_o (rspfifo_rdata)
   );
 
-  // below assertion fails when SRAM rvalid is asserted even though ReqFifo is empty
-  `ASSERT(rvalidHighReqFifoEmpty, rvalid_i |-> reqfifo_rvalid)
-
-  // below assertion fails when outstanding value is too small (SRAM rvalid is asserted
-  // even though the RspFifo is full)
-  `ASSERT(rvalidHighWhenRspFifoFull, rvalid_i |-> rspfifo_wready)
-
-  // If both ErrOnWrite and ErrOnRead are set, this block is useless
-  `ASSERT_INIT(adapterNoReadOrWrite, (ErrOnWrite & ErrOnRead) == 0)
-
-  `ASSERT_INIT(SramDwHasByteGranularity_A, SramDw % 8 == 0)
-  `ASSERT_INIT(SramDwIsMultipleOfTlulWidth_A, SramDw % top_pkg::TL_DW == 0)
-
-  // These parameter options cannot both be true at the same time
-  `ASSERT_INIT(DataIntgOptions_A, ~(EnableDataIntgGen & EnableDataIntgPt))
-
-  // make sure outputs are defined
-  `ASSERT_KNOWN(TlOutKnown_A,    tl_o   )
-  `ASSERT_KNOWN(ReqOutKnown_A,   req_o  )
-  `ASSERT_KNOWN(WeOutKnown_A,    we_o   )
-  `ASSERT_KNOWN(AddrOutKnown_A,  addr_o )
-  `ASSERT_KNOWN(WdataOutKnown_A, wdata_o)
-  `ASSERT_KNOWN(WmaskOutKnown_A, wmask_o)
-
 endmodule
diff --git a/hw/ip/uart/rtl/uart.sv b/hw/ip/uart/rtl/uart.sv
deleted file mode 100644
index 090b02b9..00000000
--- a/hw/ip/uart/rtl/uart.sv
+++ /dev/null
@@ -1,85 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Description: UART top level wrapper file
-
-// `include "prim_assert.sv"
-
-module uart (
-  input           clk_i,
-  input           rst_ni,
-
-  // Bus Interface
-  input  tlul_pkg::tl_h2d_t tl_i,
-  output tlul_pkg::tl_d2h_t tl_o,
-
-  // Generic IO
-  input           cio_rx_i,
-  output logic    cio_tx_o,
-  output logic    cio_tx_en_o,
-
-  // Interrupts
-  output logic    intr_tx_watermark_o ,
-  output logic    intr_rx_watermark_o ,
-  output logic    intr_tx_empty_o  ,
-  output logic    intr_rx_overflow_o  ,
-  output logic    intr_rx_frame_err_o ,
-  output logic    intr_rx_break_err_o ,
-  output logic    intr_rx_timeout_o   ,
-  output logic    intr_rx_parity_err_o
-);
-
-  import uart_reg_pkg::*;
-
-  uart_reg2hw_t reg2hw;
-  uart_hw2reg_t hw2reg;
-
-  uart_reg_top u_reg (
-    .clk_i,
-    .rst_ni,
-    .tl_i,
-    .tl_o,
-    .reg2hw,
-    .hw2reg,
-
-    .devmode_i  (1'b1)
-  );
-
-  uart_core uart_core (
-    .clk_i,
-    .rst_ni,
-    .reg2hw,
-    .hw2reg,
-
-    .rx    (cio_rx_i   ),
-    .tx    (cio_tx_o   ),
-
-    .intr_tx_watermark_o,
-    .intr_rx_watermark_o,
-    .intr_tx_empty_o,
-    .intr_rx_overflow_o,
-    .intr_rx_frame_err_o,
-    .intr_rx_break_err_o,
-    .intr_rx_timeout_o,
-    .intr_rx_parity_err_o
-  );
-
-  // always enable the driving out of TX
-  assign cio_tx_en_o = 1'b1;
-
-  // // Assert Known for outputs
-  // `ASSERT_KNOWN(txenKnown, cio_tx_en_o)
-  // `ASSERT_KNOWN(txKnown, cio_tx_o, clk_i, !rst_ni || !cio_tx_en_o)
-
-  // // Assert Known for interrupts
-  // `ASSERT_KNOWN(txWatermarkKnown, intr_tx_watermark_o)
-  // `ASSERT_KNOWN(rxWatermarkKnown, intr_rx_watermark_o)
-  // `ASSERT_KNOWN(txEmptyKnown, intr_tx_empty_o)
-  // `ASSERT_KNOWN(rxOverflowKnown, intr_rx_overflow_o)
-  // `ASSERT_KNOWN(rxFrameErrKnown, intr_rx_frame_err_o)
-  // `ASSERT_KNOWN(rxBreakErrKnown, intr_rx_break_err_o)
-  // `ASSERT_KNOWN(rxTimeoutKnown, intr_rx_timeout_o)
-  // `ASSERT_KNOWN(rxParityErrKnown, intr_rx_parity_err_o)
-
-endmodule
diff --git a/hw/ip/uart/rtl/uart_core.sv b/hw/ip/uart/rtl/uart_core.sv
deleted file mode 100644
index 114fd67e..00000000
--- a/hw/ip/uart/rtl/uart_core.sv
+++ /dev/null
@@ -1,490 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Description: UART core module
-//
-
-module uart_core (
-  input                  clk_i,
-  input                  rst_ni,
-
-  input  uart_reg_pkg::uart_reg2hw_t reg2hw,
-  output uart_reg_pkg::uart_hw2reg_t hw2reg,
-
-  input                  rx,
-  output logic           tx,
-
-  output logic           intr_tx_watermark_o,
-  output logic           intr_rx_watermark_o,
-  output logic           intr_tx_empty_o,
-  output logic           intr_rx_overflow_o,
-  output logic           intr_rx_frame_err_o,
-  output logic           intr_rx_break_err_o,
-  output logic           intr_rx_timeout_o,
-  output logic           intr_rx_parity_err_o
-);
-
-  import uart_reg_pkg::*;
-
-  localparam int NcoWidth = $bits(reg2hw.ctrl.nco.q);
-
-  logic   [15:0]  rx_val_q;
-  logic   [7:0]   uart_rdata;
-  logic           tick_baud_x16, rx_tick_baud;
-  logic   [5:0]   tx_fifo_depth, rx_fifo_depth;
-  logic   [5:0]   rx_fifo_depth_prev_q;
-  logic   [23:0]  rx_timeout_count_d, rx_timeout_count_q, uart_rxto_val;
-  logic           rx_fifo_depth_changed, uart_rxto_en;
-  logic           tx_enable, rx_enable;
-  logic           sys_loopback, line_loopback, rxnf_enable;
-  logic           uart_fifo_rxrst, uart_fifo_txrst;
-  logic   [2:0]   uart_fifo_rxilvl;
-  logic   [1:0]   uart_fifo_txilvl;
-  logic           ovrd_tx_en, ovrd_tx_val;
-  logic   [7:0]   tx_fifo_data;
-  logic           tx_fifo_rready, tx_fifo_rvalid;
-  logic           tx_fifo_wready, tx_uart_idle;
-  logic           tx_out;
-  logic           tx_out_q;
-  logic   [7:0]   rx_fifo_data;
-  logic           rx_valid, rx_fifo_wvalid, rx_fifo_rvalid;
-  logic           rx_fifo_wready, rx_uart_idle;
-  logic           rx_sync;
-  logic           rx_in;
-  logic           break_err;
-  logic   [4:0]   allzero_cnt_d, allzero_cnt_q;
-  logic           allzero_err, not_allzero_char;
-  logic           event_tx_watermark, event_rx_watermark, event_tx_empty, event_rx_overflow;
-  logic           event_rx_frame_err, event_rx_break_err, event_rx_timeout, event_rx_parity_err;
-  logic           tx_watermark_d, tx_watermark_prev_q;
-  logic           rx_watermark_d, rx_watermark_prev_q;
-  logic           tx_uart_idle_q;
-
-  assign tx_enable        = reg2hw.ctrl.tx.q;
-  assign rx_enable        = reg2hw.ctrl.rx.q;
-  assign rxnf_enable      = reg2hw.ctrl.nf.q;
-  assign sys_loopback     = reg2hw.ctrl.slpbk.q;
-  assign line_loopback    = reg2hw.ctrl.llpbk.q;
-
-  assign uart_fifo_rxrst  = reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe;
-  assign uart_fifo_txrst  = reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe;
-  assign uart_fifo_rxilvl = reg2hw.fifo_ctrl.rxilvl.q;
-  assign uart_fifo_txilvl = reg2hw.fifo_ctrl.txilvl.q;
-
-  assign ovrd_tx_en       = reg2hw.ovrd.txen.q;
-  assign ovrd_tx_val      = reg2hw.ovrd.txval.q;
-
-  typedef enum logic {
-    BRK_CHK,
-    BRK_WAIT
-  } break_st_e ;
-
-  break_st_e break_st_q;
-
-  assign not_allzero_char = rx_valid & (~event_rx_frame_err | (rx_fifo_data != 8'h0));
-  assign allzero_err = event_rx_frame_err & (rx_fifo_data == 8'h0);
-
-
-  assign allzero_cnt_d = (break_st_q == BRK_WAIT || not_allzero_char) ? 5'h0 :
-                          //allzero_cnt_q[4] never be 1b without break_st_q as BRK_WAIT
-                          //allzero_cnt_q[4] ? allzero_cnt_q :
-                          allzero_err ? allzero_cnt_q + 5'd1 :
-                          allzero_cnt_q;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni)        allzero_cnt_q <= '0;
-    else if (rx_enable) allzero_cnt_q <= allzero_cnt_d;
-  end
-
-  // break_err edges in same cycle as event_rx_frame_err edges ; that way the
-  // reset-on-read works the same way for break and frame error interrupts.
-
-  always_comb begin
-    unique case (reg2hw.ctrl.rxblvl.q)
-      2'h0:    break_err = allzero_cnt_d >= 5'd2;
-      2'h1:    break_err = allzero_cnt_d >= 5'd4;
-      2'h2:    break_err = allzero_cnt_d >= 5'd8;
-      default: break_err = allzero_cnt_d >= 5'd16;
-    endcase
-  end
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) break_st_q <= BRK_CHK;
-    else begin
-      unique case (break_st_q)
-        BRK_CHK: begin
-          if (event_rx_break_err) break_st_q <= BRK_WAIT;
-        end
-
-        BRK_WAIT: begin
-          if (rx_in) break_st_q <= BRK_CHK;
-        end
-
-        default: begin
-          break_st_q <= BRK_CHK;
-        end
-      endcase
-    end
-  end
-
-  assign hw2reg.val.d  = rx_val_q;
-
-  assign hw2reg.rdata.d = uart_rdata;
-
-  assign hw2reg.status.rxempty.d     = ~rx_fifo_rvalid;
-  assign hw2reg.status.rxidle.d      = rx_uart_idle;
-  assign hw2reg.status.txidle.d      = tx_uart_idle & ~tx_fifo_rvalid;
-  assign hw2reg.status.txempty.d     = ~tx_fifo_rvalid;
-  assign hw2reg.status.rxfull.d      = ~rx_fifo_wready;
-  assign hw2reg.status.txfull.d      = ~tx_fifo_wready;
-
-  assign hw2reg.fifo_status.txlvl.d  = tx_fifo_depth;
-  assign hw2reg.fifo_status.rxlvl.d  = rx_fifo_depth;
-
-  // resets are self-clearing, so need to update FIFO_CTRL
-  assign hw2reg.fifo_ctrl.rxilvl.de = 1'b0;
-  assign hw2reg.fifo_ctrl.rxilvl.d  = 3'h0;
-  assign hw2reg.fifo_ctrl.txilvl.de = 1'b0;
-  assign hw2reg.fifo_ctrl.txilvl.d  = 2'h0;
-
-  //              NCO 16x Baud Generator
-  // output clock rate is:
-  //      Fin * (NCO/2**NcoWidth)
-  logic   [NcoWidth:0]     nco_sum_q; // extra bit to get the carry
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      nco_sum_q <= 17'h0;
-    end else if (tx_enable || rx_enable) begin
-      nco_sum_q <= {1'b0,nco_sum_q[NcoWidth-1:0]} + {1'b0,reg2hw.ctrl.nco.q[NcoWidth-1:0]};
-    end
-  end
-
-  assign tick_baud_x16 = nco_sum_q[16];
-
-  //////////////
-  // TX Logic //
-  //////////////
-
-  assign tx_fifo_rready = tx_uart_idle & tx_fifo_rvalid & tx_enable;
-
-  fifo_sync #(
-    .Width   (8),
-    .Pass    (1'b0),
-    .Depth   (32)
-  ) u_uart_txfifo (
-    .clk_i,
-    .rst_ni,
-    .clr_i   (uart_fifo_txrst),
-    .wvalid_i(reg2hw.wdata.qe),
-    .wready_o(tx_fifo_wready),
-    .wdata_i (reg2hw.wdata.q),
-    .depth_o (tx_fifo_depth),
-    .rvalid_o(tx_fifo_rvalid),
-    .rready_i(tx_fifo_rready),
-    .rdata_o (tx_fifo_data)
-  );
-
-  uart_tx uart_tx (
-    .clk_i,
-    .rst_ni,
-    .tx_enable,
-    .tick_baud_x16,
-    .parity_enable  (reg2hw.ctrl.parity_en.q),
-    .wr             (tx_fifo_rready),
-    .wr_parity      ((^tx_fifo_data) ^ reg2hw.ctrl.parity_odd.q),
-    .wr_data        (tx_fifo_data),
-    .idle           (tx_uart_idle),
-    .tx             (tx_out)
-  );
-
-  assign tx = line_loopback ? rx : tx_out_q ;
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      tx_out_q <= 1'b1;
-    end else if (ovrd_tx_en) begin
-      tx_out_q <= ovrd_tx_val ;
-    end else if (sys_loopback) begin
-      tx_out_q <= 1'b1;
-    end else begin
-      tx_out_q <= tx_out;
-    end
-  end
-
-  //////////////
-  // RX Logic //
-  //////////////
-
-  //      sync the incoming data
-  prim_generic_flop_2sync #(
-    .Width(1),
-    .ResetValue(1'b1)
-  ) sync_rx (
-    .clk_i,
-    .rst_ni,
-    .d_i(rx),
-    .q_o(rx_sync)
-  );
-
-  // Based on: en.wikipedia.org/wiki/Repetition_code mentions the use of a majority filter
-  // in UART to ignore brief noise spikes
-  logic   rx_sync_q1, rx_sync_q2, rx_in_mx, rx_in_maj;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      rx_sync_q1 <= 1'b1;
-      rx_sync_q2 <= 1'b1;
-    end else begin
-      rx_sync_q1 <= rx_sync;
-      rx_sync_q2 <= rx_sync_q1;
-    end
-  end
-
-  assign rx_in_maj = (rx_sync    & rx_sync_q1) |
-                     (rx_sync    & rx_sync_q2) |
-                     (rx_sync_q1 & rx_sync_q2);
-  assign rx_in_mx  = rxnf_enable ? rx_in_maj : rx_sync;
-
-  assign rx_in =  sys_loopback ? tx_out   :
-                  line_loopback ? 1'b1 :
-                  rx_in_mx;
-
-  uart_rx uart_rx (
-    .clk_i          (clk_i),
-    .rst_ni         (rst_ni),
-    .rx_enable      (rx_enable),
-    .tick_baud_x16  (tick_baud_x16),
-    .parity_enable  (reg2hw.ctrl.parity_en.q),
-    .parity_odd     (reg2hw.ctrl.parity_odd.q),
-    .tick_baud      (rx_tick_baud),
-    .rx_valid       (rx_valid),
-    .rx_data        (rx_fifo_data),
-    .idle           (rx_uart_idle),
-    .frame_err      (event_rx_frame_err),
-    .rx             (rx_in),
-    .rx_parity_err  (event_rx_parity_err)
-  );
-
-  assign rx_fifo_wvalid = rx_valid & ~event_rx_frame_err & ~event_rx_parity_err;
-
-  fifo_sync #(
-    .Width   (8),
-    .Pass    (1'b0),
-    .Depth   (32)
-  ) u_uart_rxfifo (
-    .clk_i,
-    .rst_ni,
-    .clr_i   (uart_fifo_rxrst),
-    .wvalid_i(rx_fifo_wvalid),
-    .wready_o(rx_fifo_wready),
-    .wdata_i (rx_fifo_data),
-    .depth_o (rx_fifo_depth),
-    .rvalid_o(rx_fifo_rvalid),
-    .rready_i(reg2hw.rdata.re),
-    .rdata_o (uart_rdata)
-  );
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni)            rx_val_q <= 16'h0;
-    else if (tick_baud_x16) rx_val_q <= {rx_val_q[14:0], rx_in};
-  end
-
-  ////////////////////////
-  // Interrupt & Status //
-  ////////////////////////
-
-  always_comb begin
-    unique case(uart_fifo_txilvl)
-      2'h0:    tx_watermark_d = (tx_fifo_depth < 6'd2);
-      2'h1:    tx_watermark_d = (tx_fifo_depth < 6'd4);
-      2'h2:    tx_watermark_d = (tx_fifo_depth < 6'd8);
-      default: tx_watermark_d = (tx_fifo_depth < 6'd16);
-    endcase
-  end
-
-  assign event_tx_watermark = tx_watermark_d & ~tx_watermark_prev_q;
-
-  // The empty condition handling is a bit different.
-  // If empty rising conditions were detected directly, then every first write of a burst
-  // would trigger an empty.  This is due to the fact that the uart_tx fsm immediately
-  // withdraws the content and asserts "empty".
-  // To guard against this false trigger, empty is qualified with idle to extend the window
-  // in which software has an opportunity to deposit new data.
-  // However, if software deposit speed is TOO slow, this would still be an issue.
-  //
-  // The alternative software fix is to disable tx_enable until it has a chance to
-  // burst in the desired amount of data.
-  assign event_tx_empty     = ~tx_fifo_rvalid & ~tx_uart_idle_q & tx_uart_idle;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      tx_watermark_prev_q  <= 1'b1; // by default watermark condition is true
-      rx_watermark_prev_q  <= 1'b0; // by default watermark condition is false
-      tx_uart_idle_q       <= 1'b1;
-    end else begin
-      tx_watermark_prev_q  <= tx_watermark_d;
-      rx_watermark_prev_q  <= rx_watermark_d;
-      tx_uart_idle_q       <= tx_uart_idle;
-    end
-  end
-
-  always_comb begin
-    unique case(uart_fifo_rxilvl)
-      3'h0:    rx_watermark_d = (rx_fifo_depth >= 6'd1);
-      3'h1:    rx_watermark_d = (rx_fifo_depth >= 6'd4);
-      3'h2:    rx_watermark_d = (rx_fifo_depth >= 6'd8);
-      3'h3:    rx_watermark_d = (rx_fifo_depth >= 6'd16);
-      3'h4:    rx_watermark_d = (rx_fifo_depth >= 6'd30);
-      default: rx_watermark_d = 1'b0;
-    endcase
-  end
-
-  assign event_rx_watermark = rx_watermark_d & ~rx_watermark_prev_q;
-
-  // rx timeout interrupt
-  assign uart_rxto_en  = reg2hw.timeout_ctrl.en.q;
-  assign uart_rxto_val = reg2hw.timeout_ctrl.val.q;
-
-  assign rx_fifo_depth_changed = (rx_fifo_depth != rx_fifo_depth_prev_q);
-
-  assign rx_timeout_count_d =
-              // don't count if timeout feature not enabled ;
-              // will never reach timeout val + lower power
-              (uart_rxto_en == 1'b0)              ? 24'd0 :
-              // reset count if timeout interrupt is set
-              event_rx_timeout                    ? 24'd0 :
-              // reset count upon change in fifo level: covers both read and receiving a new byte
-              rx_fifo_depth_changed               ? 24'd0 :
-              // reset count if no bytes are pending
-              (rx_fifo_depth == 5'd0)             ? 24'd0 :
-              // stop the count at timeout value (this will set the interrupt)
-              //   Removed below line as when the timeout reaches the value,
-              //   event occured, and timeout value reset to 0h.
-              //(rx_timeout_count_q == uart_rxto_val) ? rx_timeout_count_q :
-              // increment if at rx baud tick
-              rx_tick_baud                        ? (rx_timeout_count_q + 24'd1) :
-              rx_timeout_count_q;
-
-  assign event_rx_timeout = (rx_timeout_count_q == uart_rxto_val) & uart_rxto_en;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      rx_timeout_count_q   <= 24'd0;
-      rx_fifo_depth_prev_q <= 6'd0;
-    end else begin
-      rx_timeout_count_q    <= rx_timeout_count_d;
-      rx_fifo_depth_prev_q  <= rx_fifo_depth;
-    end
-  end
-
-  assign event_rx_overflow  = rx_fifo_wvalid & ~rx_fifo_wready;
-  assign event_rx_break_err = break_err & (break_st_q == BRK_CHK);
-
-  // instantiate interrupt hardware primitives
-
-  prim_intr_hw #(.Width(1)) intr_hw_tx_watermark (
-    .clk_i,
-    .rst_ni,
-    .event_intr_i           (event_tx_watermark),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_watermark.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.tx_watermark.q),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.tx_watermark.qe),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.tx_watermark.q),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_watermark.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.tx_watermark.d),
-    .intr_o                 (intr_tx_watermark_o)
-  );
-
-  prim_intr_hw #(.Width(1)) intr_hw_rx_watermark (
-    .clk_i,
-    .rst_ni,
-    .event_intr_i           (event_rx_watermark),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_watermark.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_watermark.q),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_watermark.qe),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_watermark.q),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_watermark.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_watermark.d),
-    .intr_o                 (intr_rx_watermark_o)
-  );
-
-  prim_intr_hw #(.Width(1)) intr_hw_tx_empty (
-    .clk_i,
-    .rst_ni,
-    .event_intr_i           (event_tx_empty),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_empty.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.tx_empty.q),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.tx_empty.qe),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.tx_empty.q),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_empty.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.tx_empty.d),
-    .intr_o                 (intr_tx_empty_o)
-  );
-
-  prim_intr_hw #(.Width(1)) intr_hw_rx_overflow (
-    .clk_i,
-    .rst_ni,
-    .event_intr_i           (event_rx_overflow),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_overflow.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_overflow.q),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_overflow.qe),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_overflow.q),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_overflow.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_overflow.d),
-    .intr_o                 (intr_rx_overflow_o)
-  );
-
-  prim_intr_hw #(.Width(1)) intr_hw_rx_frame_err (
-    .clk_i,
-    .rst_ni,
-    .event_intr_i           (event_rx_frame_err),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_frame_err.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_frame_err.q),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_frame_err.qe),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_frame_err.q),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_frame_err.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_frame_err.d),
-    .intr_o                 (intr_rx_frame_err_o)
-  );
-
-  prim_intr_hw #(.Width(1)) intr_hw_rx_break_err (
-    .clk_i,
-    .rst_ni,
-    .event_intr_i           (event_rx_break_err),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_break_err.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_break_err.q),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_break_err.qe),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_break_err.q),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_break_err.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_break_err.d),
-    .intr_o                 (intr_rx_break_err_o)
-  );
-
-  prim_intr_hw #(.Width(1)) intr_hw_rx_timeout (
-    .clk_i,
-    .rst_ni,
-    .event_intr_i           (event_rx_timeout),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_timeout.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_timeout.q),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_timeout.qe),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_timeout.q),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_timeout.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_timeout.d),
-    .intr_o                 (intr_rx_timeout_o)
-  );
-
-  prim_intr_hw #(.Width(1)) intr_hw_rx_parity_err (
-    .clk_i,
-    .rst_ni,
-    .event_intr_i           (event_rx_parity_err),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_parity_err.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_parity_err.q),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_parity_err.qe),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_parity_err.q),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_parity_err.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_parity_err.d),
-    .intr_o                 (intr_rx_parity_err_o)
-  );
-
-endmodule
diff --git a/hw/ip/uart/rtl/uart_core.v b/hw/ip/uart/rtl/uart_core.v
new file mode 100644
index 00000000..47986be2
--- /dev/null
+++ b/hw/ip/uart/rtl/uart_core.v
@@ -0,0 +1,102 @@
+
+module uart_core (
+    input  clk_i,
+    input  rst_ni,
+    
+    input  ren,
+    input  we,
+    input  [31:0] wdata,
+    output [31:0] rdata,
+    input  [7:0]  addr,    
+    output tx_o,
+    input  rx_i,
+    
+    output intr_tx
+);
+    
+    localparam ADDR_CTRL = 0;
+    localparam ADDR_TX   = 4;
+    localparam ADDR_RX   = 8;
+    localparam RX_EN     = 12;
+    localparam TX_EN     = 16;
+    localparam RX_STATUS = 20;
+    localparam RX_SC     = 24;
+    
+    reg [15:0] control;
+    reg [7:0]  tx;
+    wire [7:0] rx;
+    reg  [7:0] rx_reg;
+    reg        rx_en;
+    reg        tx_en;
+    reg        rx_status;
+    reg        rx_clr;
+    wire       rx_done;
+    
+always @(posedge clk_i or negedge rst_ni) begin
+  if(~rst_ni) begin
+    control <= 16'b0;
+    tx      <= 8'b0;
+    rx_en   <= 1'b0;
+    tx_en   <= 1'b0;
+	rx_clr  <= 1'b1;
+  end else begin
+    if(~ren & we) begin
+      if(addr == ADDR_CTRL) begin
+        control  <= wdata[15:0];
+      end else if (addr == ADDR_TX) begin
+        tx  <= wdata[7:0];
+      end else if (addr == RX_EN) begin
+        rx_en <= wdata[0];
+      end else if(addr == TX_EN) begin
+        tx_en <= wdata[0];
+      end else if(addr == RX_SC) begin
+	    rx_clr <= wdata[0];
+      end else begin
+        control <= 16'b0;
+        tx      <= 8'b0;
+        rx_en   <= 1'b0;
+        tx_en   <= 1'b0;
+		rx_clr  <= 1'b1;
+      end
+    end 
+  end     
+end
+    
+    
+uart_tx u_tx (
+   .clk_i       (clk_i),
+   .rst_ni      (rst_ni),
+   .tx_en       (tx_en),
+   .i_TX_Byte   (tx), 
+   .CLKS_PER_BIT(control),
+   .o_TX_Serial (tx_o),
+   .o_TX_Done   (intr_tx)
+);
+    
+uart_rx u_rx(
+  .clk_i        (clk_i),
+  .rst_ni       (rst_ni),
+  .i_Rx_Serial  (rx_en? rx_i: 1'b1),
+  .o_Rx_DV      (rx_done),
+  .CLKS_PER_BIT (control),
+  .o_Rx_Byte    (rx)
+);
+
+always @(posedge clk_i or negedge rst_ni) begin
+  if(!rst_ni) begin
+     rx_status <= 1'b0;
+	 rx_reg    <= 8'b0;
+  end else begin        
+    if (rx_done) begin
+	  rx_reg  <= rx;
+	  rx_status <= 1'b1;	
+    end else if(!rx_clr) begin
+	  rx_status <= 1'b0;	
+    end
+  end
+end
+  
+ assign rdata = (addr == 20)? rx_status : (addr == 8)? rx_reg : 0;   
+      
+   
+endmodule
diff --git a/hw/ip/uart/rtl/uart_reg_pkg.sv b/hw/ip/uart/rtl/uart_reg_pkg.sv
deleted file mode 100644
index 22ae7ac1..00000000
--- a/hw/ip/uart/rtl/uart_reg_pkg.sv
+++ /dev/null
@@ -1,369 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Register Package auto-generated by `reggen` containing data structure
-
-package uart_reg_pkg;
-
-  // Address width within the block
-  parameter int BlockAw = 6;
-
-  ////////////////////////////
-  // Typedefs for registers //
-  ////////////////////////////
-  typedef struct packed {
-    struct packed {
-      logic        q;
-    } tx_watermark;
-    struct packed {
-      logic        q;
-    } rx_watermark;
-    struct packed {
-      logic        q;
-    } tx_empty;
-    struct packed {
-      logic        q;
-    } rx_overflow;
-    struct packed {
-      logic        q;
-    } rx_frame_err;
-    struct packed {
-      logic        q;
-    } rx_break_err;
-    struct packed {
-      logic        q;
-    } rx_timeout;
-    struct packed {
-      logic        q;
-    } rx_parity_err;
-  } uart_reg2hw_intr_state_reg_t;
-
-  typedef struct packed {
-    struct packed {
-      logic        q;
-    } tx_watermark;
-    struct packed {
-      logic        q;
-    } rx_watermark;
-    struct packed {
-      logic        q;
-    } tx_empty;
-    struct packed {
-      logic        q;
-    } rx_overflow;
-    struct packed {
-      logic        q;
-    } rx_frame_err;
-    struct packed {
-      logic        q;
-    } rx_break_err;
-    struct packed {
-      logic        q;
-    } rx_timeout;
-    struct packed {
-      logic        q;
-    } rx_parity_err;
-  } uart_reg2hw_intr_enable_reg_t;
-
-  typedef struct packed {
-    struct packed {
-      logic        q;
-      logic        qe;
-    } tx_watermark;
-    struct packed {
-      logic        q;
-      logic        qe;
-    } rx_watermark;
-    struct packed {
-      logic        q;
-      logic        qe;
-    } tx_empty;
-    struct packed {
-      logic        q;
-      logic        qe;
-    } rx_overflow;
-    struct packed {
-      logic        q;
-      logic        qe;
-    } rx_frame_err;
-    struct packed {
-      logic        q;
-      logic        qe;
-    } rx_break_err;
-    struct packed {
-      logic        q;
-      logic        qe;
-    } rx_timeout;
-    struct packed {
-      logic        q;
-      logic        qe;
-    } rx_parity_err;
-  } uart_reg2hw_intr_test_reg_t;
-
-  typedef struct packed {
-    struct packed {
-      logic        q;
-    } tx;
-    struct packed {
-      logic        q;
-    } rx;
-    struct packed {
-      logic        q;
-    } nf;
-    struct packed {
-      logic        q;
-    } slpbk;
-    struct packed {
-      logic        q;
-    } llpbk;
-    struct packed {
-      logic        q;
-    } parity_en;
-    struct packed {
-      logic        q;
-    } parity_odd;
-    struct packed {
-      logic [1:0]  q;
-    } rxblvl;
-    struct packed {
-      logic [15:0] q;
-    } nco;
-  } uart_reg2hw_ctrl_reg_t;
-
-  typedef struct packed {
-    struct packed {
-      logic        q;
-      logic        re;
-    } txfull;
-    struct packed {
-      logic        q;
-      logic        re;
-    } rxfull;
-    struct packed {
-      logic        q;
-      logic        re;
-    } txempty;
-    struct packed {
-      logic        q;
-      logic        re;
-    } txidle;
-    struct packed {
-      logic        q;
-      logic        re;
-    } rxidle;
-    struct packed {
-      logic        q;
-      logic        re;
-    } rxempty;
-  } uart_reg2hw_status_reg_t;
-
-  typedef struct packed {
-    logic [7:0]  q;
-    logic        re;
-  } uart_reg2hw_rdata_reg_t;
-
-  typedef struct packed {
-    logic [7:0]  q;
-    logic        qe;
-  } uart_reg2hw_wdata_reg_t;
-
-  typedef struct packed {
-    struct packed {
-      logic        q;
-      logic        qe;
-    } rxrst;
-    struct packed {
-      logic        q;
-      logic        qe;
-    } txrst;
-    struct packed {
-      logic [2:0]  q;
-      logic        qe;
-    } rxilvl;
-    struct packed {
-      logic [1:0]  q;
-      logic        qe;
-    } txilvl;
-  } uart_reg2hw_fifo_ctrl_reg_t;
-
-  typedef struct packed {
-    struct packed {
-      logic        q;
-    } txen;
-    struct packed {
-      logic        q;
-    } txval;
-  } uart_reg2hw_ovrd_reg_t;
-
-  typedef struct packed {
-    struct packed {
-      logic [23:0] q;
-    } val;
-    struct packed {
-      logic        q;
-    } en;
-  } uart_reg2hw_timeout_ctrl_reg_t;
-
-
-  typedef struct packed {
-    struct packed {
-      logic        d;
-      logic        de;
-    } tx_watermark;
-    struct packed {
-      logic        d;
-      logic        de;
-    } rx_watermark;
-    struct packed {
-      logic        d;
-      logic        de;
-    } tx_empty;
-    struct packed {
-      logic        d;
-      logic        de;
-    } rx_overflow;
-    struct packed {
-      logic        d;
-      logic        de;
-    } rx_frame_err;
-    struct packed {
-      logic        d;
-      logic        de;
-    } rx_break_err;
-    struct packed {
-      logic        d;
-      logic        de;
-    } rx_timeout;
-    struct packed {
-      logic        d;
-      logic        de;
-    } rx_parity_err;
-  } uart_hw2reg_intr_state_reg_t;
-
-  typedef struct packed {
-    struct packed {
-      logic        d;
-    } txfull;
-    struct packed {
-      logic        d;
-    } rxfull;
-    struct packed {
-      logic        d;
-    } txempty;
-    struct packed {
-      logic        d;
-    } txidle;
-    struct packed {
-      logic        d;
-    } rxidle;
-    struct packed {
-      logic        d;
-    } rxempty;
-  } uart_hw2reg_status_reg_t;
-
-  typedef struct packed {
-    logic [7:0]  d;
-  } uart_hw2reg_rdata_reg_t;
-
-  typedef struct packed {
-    struct packed {
-      logic [2:0]  d;
-      logic        de;
-    } rxilvl;
-    struct packed {
-      logic [1:0]  d;
-      logic        de;
-    } txilvl;
-  } uart_hw2reg_fifo_ctrl_reg_t;
-
-  typedef struct packed {
-    struct packed {
-      logic [5:0]  d;
-    } txlvl;
-    struct packed {
-      logic [5:0]  d;
-    } rxlvl;
-  } uart_hw2reg_fifo_status_reg_t;
-
-  typedef struct packed {
-    logic [15:0] d;
-  } uart_hw2reg_val_reg_t;
-
-
-  ///////////////////////////////////////
-  // Register to internal design logic //
-  ///////////////////////////////////////
-  typedef struct packed {
-    uart_reg2hw_intr_state_reg_t intr_state; // [124:117]
-    uart_reg2hw_intr_enable_reg_t intr_enable; // [116:109]
-    uart_reg2hw_intr_test_reg_t intr_test; // [108:93]
-    uart_reg2hw_ctrl_reg_t ctrl; // [92:68]
-    uart_reg2hw_status_reg_t status; // [67:56]
-    uart_reg2hw_rdata_reg_t rdata; // [55:47]
-    uart_reg2hw_wdata_reg_t wdata; // [46:38]
-    uart_reg2hw_fifo_ctrl_reg_t fifo_ctrl; // [37:27]
-    uart_reg2hw_ovrd_reg_t ovrd; // [26:25]
-    uart_reg2hw_timeout_ctrl_reg_t timeout_ctrl; // [24:0]
-  } uart_reg2hw_t;
-
-  ///////////////////////////////////////
-  // Internal design logic to register //
-  ///////////////////////////////////////
-  typedef struct packed {
-    uart_hw2reg_intr_state_reg_t intr_state; // [64:49]
-    uart_hw2reg_status_reg_t status; // [48:43]
-    uart_hw2reg_rdata_reg_t rdata; // [42:35]
-    uart_hw2reg_fifo_ctrl_reg_t fifo_ctrl; // [34:28]
-    uart_hw2reg_fifo_status_reg_t fifo_status; // [27:16]
-    uart_hw2reg_val_reg_t val; // [15:0]
-  } uart_hw2reg_t;
-
-  // Register Address
-  parameter logic [BlockAw-1:0] UART_INTR_STATE_OFFSET = 6'h 0;
-  parameter logic [BlockAw-1:0] UART_INTR_ENABLE_OFFSET = 6'h 4;
-  parameter logic [BlockAw-1:0] UART_INTR_TEST_OFFSET = 6'h 8;
-  parameter logic [BlockAw-1:0] UART_CTRL_OFFSET = 6'h c;
-  parameter logic [BlockAw-1:0] UART_STATUS_OFFSET = 6'h 10;
-  parameter logic [BlockAw-1:0] UART_RDATA_OFFSET = 6'h 14;
-  parameter logic [BlockAw-1:0] UART_WDATA_OFFSET = 6'h 18;
-  parameter logic [BlockAw-1:0] UART_FIFO_CTRL_OFFSET = 6'h 1c;
-  parameter logic [BlockAw-1:0] UART_FIFO_STATUS_OFFSET = 6'h 20;
-  parameter logic [BlockAw-1:0] UART_OVRD_OFFSET = 6'h 24;
-  parameter logic [BlockAw-1:0] UART_VAL_OFFSET = 6'h 28;
-  parameter logic [BlockAw-1:0] UART_TIMEOUT_CTRL_OFFSET = 6'h 2c;
-
-
-  // Register Index
-  typedef enum int {
-    UART_INTR_STATE,
-    UART_INTR_ENABLE,
-    UART_INTR_TEST,
-    UART_CTRL,
-    UART_STATUS,
-    UART_RDATA,
-    UART_WDATA,
-    UART_FIFO_CTRL,
-    UART_FIFO_STATUS,
-    UART_OVRD,
-    UART_VAL,
-    UART_TIMEOUT_CTRL
-  } uart_id_e;
-
-  // Register width information to check illegal writes
-  parameter logic [3:0] UART_PERMIT [12] = '{
-    4'b 0001, // index[ 0] UART_INTR_STATE
-    4'b 0001, // index[ 1] UART_INTR_ENABLE
-    4'b 0001, // index[ 2] UART_INTR_TEST
-    4'b 1111, // index[ 3] UART_CTRL
-    4'b 0001, // index[ 4] UART_STATUS
-    4'b 0001, // index[ 5] UART_RDATA
-    4'b 0001, // index[ 6] UART_WDATA
-    4'b 0001, // index[ 7] UART_FIFO_CTRL
-    4'b 0111, // index[ 8] UART_FIFO_STATUS
-    4'b 0001, // index[ 9] UART_OVRD
-    4'b 0011, // index[10] UART_VAL
-    4'b 1111  // index[11] UART_TIMEOUT_CTRL
-  };
-endpackage
-
diff --git a/hw/ip/uart/rtl/uart_reg_top.sv b/hw/ip/uart/rtl/uart_reg_top.sv
deleted file mode 100644
index 4342e2a2..00000000
--- a/hw/ip/uart/rtl/uart_reg_top.sv
+++ /dev/null
@@ -1,1677 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Register Top module auto-generated by `reggen`
-
-// `include "prim_assert.sv"
-
-module uart_reg_top (
-  input clk_i,
-  input rst_ni,
-
-  // Below Regster interface can be changed
-  input  tlul_pkg::tl_h2d_t tl_i,
-  output tlul_pkg::tl_d2h_t tl_o,
-  // To HW
-  output uart_reg_pkg::uart_reg2hw_t reg2hw, // Write
-  input  uart_reg_pkg::uart_hw2reg_t hw2reg, // Read
-
-  // Config
-  input devmode_i // If 1, explicit error return for unmapped register access
-);
-
-  import uart_reg_pkg::* ;
-
-  localparam int AW = 6;
-  localparam int DW = 32;
-  localparam int DBW = DW/8;                    // Byte Width
-
-  // register signals
-  logic           reg_we;
-  logic           reg_re;
-  logic [AW-1:0]  reg_addr;
-  logic [DW-1:0]  reg_wdata;
-  logic [DBW-1:0] reg_be;
-  logic [DW-1:0]  reg_rdata;
-  logic           reg_error;
-
-  logic          addrmiss, wr_err;
-
-  logic [DW-1:0] reg_rdata_next;
-
-  tlul_pkg::tl_h2d_t tl_reg_h2d;
-  tlul_pkg::tl_d2h_t tl_reg_d2h;
-
-  assign tl_reg_h2d = tl_i;
-  assign tl_o       = tl_reg_d2h;
-
-  tlul_adapter_reg #(
-    .RegAw(AW),
-    .RegDw(DW)
-  ) u_reg_if (
-    .clk_i,
-    .rst_ni,
-
-    .tl_i (tl_reg_h2d),
-    .tl_o (tl_reg_d2h),
-
-    .we_o    (reg_we),
-    .re_o    (reg_re),
-    .addr_o  (reg_addr),
-    .wdata_o (reg_wdata),
-    .be_o    (reg_be),
-    .rdata_i (reg_rdata),
-    .error_i (reg_error)
-  );
-
-  assign reg_rdata = reg_rdata_next ;
-  assign reg_error = (devmode_i & addrmiss) | wr_err ;
-
-  // Define SW related signals
-  // Format: <reg>_<field>_{wd|we|qs}
-  //        or <reg>_{wd|we|qs} if field == 1 or 0
-  logic intr_state_tx_watermark_qs;
-  logic intr_state_tx_watermark_wd;
-  logic intr_state_tx_watermark_we;
-  logic intr_state_rx_watermark_qs;
-  logic intr_state_rx_watermark_wd;
-  logic intr_state_rx_watermark_we;
-  logic intr_state_tx_empty_qs;
-  logic intr_state_tx_empty_wd;
-  logic intr_state_tx_empty_we;
-  logic intr_state_rx_overflow_qs;
-  logic intr_state_rx_overflow_wd;
-  logic intr_state_rx_overflow_we;
-  logic intr_state_rx_frame_err_qs;
-  logic intr_state_rx_frame_err_wd;
-  logic intr_state_rx_frame_err_we;
-  logic intr_state_rx_break_err_qs;
-  logic intr_state_rx_break_err_wd;
-  logic intr_state_rx_break_err_we;
-  logic intr_state_rx_timeout_qs;
-  logic intr_state_rx_timeout_wd;
-  logic intr_state_rx_timeout_we;
-  logic intr_state_rx_parity_err_qs;
-  logic intr_state_rx_parity_err_wd;
-  logic intr_state_rx_parity_err_we;
-  logic intr_enable_tx_watermark_qs;
-  logic intr_enable_tx_watermark_wd;
-  logic intr_enable_tx_watermark_we;
-  logic intr_enable_rx_watermark_qs;
-  logic intr_enable_rx_watermark_wd;
-  logic intr_enable_rx_watermark_we;
-  logic intr_enable_tx_empty_qs;
-  logic intr_enable_tx_empty_wd;
-  logic intr_enable_tx_empty_we;
-  logic intr_enable_rx_overflow_qs;
-  logic intr_enable_rx_overflow_wd;
-  logic intr_enable_rx_overflow_we;
-  logic intr_enable_rx_frame_err_qs;
-  logic intr_enable_rx_frame_err_wd;
-  logic intr_enable_rx_frame_err_we;
-  logic intr_enable_rx_break_err_qs;
-  logic intr_enable_rx_break_err_wd;
-  logic intr_enable_rx_break_err_we;
-  logic intr_enable_rx_timeout_qs;
-  logic intr_enable_rx_timeout_wd;
-  logic intr_enable_rx_timeout_we;
-  logic intr_enable_rx_parity_err_qs;
-  logic intr_enable_rx_parity_err_wd;
-  logic intr_enable_rx_parity_err_we;
-  logic intr_test_tx_watermark_wd;
-  logic intr_test_tx_watermark_we;
-  logic intr_test_rx_watermark_wd;
-  logic intr_test_rx_watermark_we;
-  logic intr_test_tx_empty_wd;
-  logic intr_test_tx_empty_we;
-  logic intr_test_rx_overflow_wd;
-  logic intr_test_rx_overflow_we;
-  logic intr_test_rx_frame_err_wd;
-  logic intr_test_rx_frame_err_we;
-  logic intr_test_rx_break_err_wd;
-  logic intr_test_rx_break_err_we;
-  logic intr_test_rx_timeout_wd;
-  logic intr_test_rx_timeout_we;
-  logic intr_test_rx_parity_err_wd;
-  logic intr_test_rx_parity_err_we;
-  logic ctrl_tx_qs;
-  logic ctrl_tx_wd;
-  logic ctrl_tx_we;
-  logic ctrl_rx_qs;
-  logic ctrl_rx_wd;
-  logic ctrl_rx_we;
-  logic ctrl_nf_qs;
-  logic ctrl_nf_wd;
-  logic ctrl_nf_we;
-  logic ctrl_slpbk_qs;
-  logic ctrl_slpbk_wd;
-  logic ctrl_slpbk_we;
-  logic ctrl_llpbk_qs;
-  logic ctrl_llpbk_wd;
-  logic ctrl_llpbk_we;
-  logic ctrl_parity_en_qs;
-  logic ctrl_parity_en_wd;
-  logic ctrl_parity_en_we;
-  logic ctrl_parity_odd_qs;
-  logic ctrl_parity_odd_wd;
-  logic ctrl_parity_odd_we;
-  logic [1:0] ctrl_rxblvl_qs;
-  logic [1:0] ctrl_rxblvl_wd;
-  logic ctrl_rxblvl_we;
-  logic [15:0] ctrl_nco_qs;
-  logic [15:0] ctrl_nco_wd;
-  logic ctrl_nco_we;
-  logic status_txfull_qs;
-  logic status_txfull_re;
-  logic status_rxfull_qs;
-  logic status_rxfull_re;
-  logic status_txempty_qs;
-  logic status_txempty_re;
-  logic status_txidle_qs;
-  logic status_txidle_re;
-  logic status_rxidle_qs;
-  logic status_rxidle_re;
-  logic status_rxempty_qs;
-  logic status_rxempty_re;
-  logic [7:0] rdata_qs;
-  logic rdata_re;
-  logic [7:0] wdata_wd;
-  logic wdata_we;
-  logic fifo_ctrl_rxrst_wd;
-  logic fifo_ctrl_rxrst_we;
-  logic fifo_ctrl_txrst_wd;
-  logic fifo_ctrl_txrst_we;
-  logic [2:0] fifo_ctrl_rxilvl_qs;
-  logic [2:0] fifo_ctrl_rxilvl_wd;
-  logic fifo_ctrl_rxilvl_we;
-  logic [1:0] fifo_ctrl_txilvl_qs;
-  logic [1:0] fifo_ctrl_txilvl_wd;
-  logic fifo_ctrl_txilvl_we;
-  logic [5:0] fifo_status_txlvl_qs;
-  logic fifo_status_txlvl_re;
-  logic [5:0] fifo_status_rxlvl_qs;
-  logic fifo_status_rxlvl_re;
-  logic ovrd_txen_qs;
-  logic ovrd_txen_wd;
-  logic ovrd_txen_we;
-  logic ovrd_txval_qs;
-  logic ovrd_txval_wd;
-  logic ovrd_txval_we;
-  logic [15:0] val_qs;
-  logic val_re;
-  logic [23:0] timeout_ctrl_val_qs;
-  logic [23:0] timeout_ctrl_val_wd;
-  logic timeout_ctrl_val_we;
-  logic timeout_ctrl_en_qs;
-  logic timeout_ctrl_en_wd;
-  logic timeout_ctrl_en_we;
-
-  // Register instances
-  // R[intr_state]: V(False)
-
-  //   F[tx_watermark]: 0:0
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("W1C"),
-    .RESVAL  (1'h0)
-  ) u_intr_state_tx_watermark (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_state_tx_watermark_we),
-    .wd     (intr_state_tx_watermark_wd),
-
-    // from internal hardware
-    .de     (hw2reg.intr_state.tx_watermark.de),
-    .d      (hw2reg.intr_state.tx_watermark.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_state.tx_watermark.q ),
-
-    // to register interface (read)
-    .qs     (intr_state_tx_watermark_qs)
-  );
-
-
-  //   F[rx_watermark]: 1:1
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("W1C"),
-    .RESVAL  (1'h0)
-  ) u_intr_state_rx_watermark (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_state_rx_watermark_we),
-    .wd     (intr_state_rx_watermark_wd),
-
-    // from internal hardware
-    .de     (hw2reg.intr_state.rx_watermark.de),
-    .d      (hw2reg.intr_state.rx_watermark.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_state.rx_watermark.q ),
-
-    // to register interface (read)
-    .qs     (intr_state_rx_watermark_qs)
-  );
-
-
-  //   F[tx_empty]: 2:2
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("W1C"),
-    .RESVAL  (1'h0)
-  ) u_intr_state_tx_empty (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_state_tx_empty_we),
-    .wd     (intr_state_tx_empty_wd),
-
-    // from internal hardware
-    .de     (hw2reg.intr_state.tx_empty.de),
-    .d      (hw2reg.intr_state.tx_empty.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_state.tx_empty.q ),
-
-    // to register interface (read)
-    .qs     (intr_state_tx_empty_qs)
-  );
-
-
-  //   F[rx_overflow]: 3:3
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("W1C"),
-    .RESVAL  (1'h0)
-  ) u_intr_state_rx_overflow (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_state_rx_overflow_we),
-    .wd     (intr_state_rx_overflow_wd),
-
-    // from internal hardware
-    .de     (hw2reg.intr_state.rx_overflow.de),
-    .d      (hw2reg.intr_state.rx_overflow.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_state.rx_overflow.q ),
-
-    // to register interface (read)
-    .qs     (intr_state_rx_overflow_qs)
-  );
-
-
-  //   F[rx_frame_err]: 4:4
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("W1C"),
-    .RESVAL  (1'h0)
-  ) u_intr_state_rx_frame_err (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_state_rx_frame_err_we),
-    .wd     (intr_state_rx_frame_err_wd),
-
-    // from internal hardware
-    .de     (hw2reg.intr_state.rx_frame_err.de),
-    .d      (hw2reg.intr_state.rx_frame_err.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_state.rx_frame_err.q ),
-
-    // to register interface (read)
-    .qs     (intr_state_rx_frame_err_qs)
-  );
-
-
-  //   F[rx_break_err]: 5:5
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("W1C"),
-    .RESVAL  (1'h0)
-  ) u_intr_state_rx_break_err (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_state_rx_break_err_we),
-    .wd     (intr_state_rx_break_err_wd),
-
-    // from internal hardware
-    .de     (hw2reg.intr_state.rx_break_err.de),
-    .d      (hw2reg.intr_state.rx_break_err.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_state.rx_break_err.q ),
-
-    // to register interface (read)
-    .qs     (intr_state_rx_break_err_qs)
-  );
-
-
-  //   F[rx_timeout]: 6:6
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("W1C"),
-    .RESVAL  (1'h0)
-  ) u_intr_state_rx_timeout (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_state_rx_timeout_we),
-    .wd     (intr_state_rx_timeout_wd),
-
-    // from internal hardware
-    .de     (hw2reg.intr_state.rx_timeout.de),
-    .d      (hw2reg.intr_state.rx_timeout.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_state.rx_timeout.q ),
-
-    // to register interface (read)
-    .qs     (intr_state_rx_timeout_qs)
-  );
-
-
-  //   F[rx_parity_err]: 7:7
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("W1C"),
-    .RESVAL  (1'h0)
-  ) u_intr_state_rx_parity_err (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_state_rx_parity_err_we),
-    .wd     (intr_state_rx_parity_err_wd),
-
-    // from internal hardware
-    .de     (hw2reg.intr_state.rx_parity_err.de),
-    .d      (hw2reg.intr_state.rx_parity_err.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_state.rx_parity_err.q ),
-
-    // to register interface (read)
-    .qs     (intr_state_rx_parity_err_qs)
-  );
-
-
-  // R[intr_enable]: V(False)
-
-  //   F[tx_watermark]: 0:0
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_intr_enable_tx_watermark (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_enable_tx_watermark_we),
-    .wd     (intr_enable_tx_watermark_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_enable.tx_watermark.q ),
-
-    // to register interface (read)
-    .qs     (intr_enable_tx_watermark_qs)
-  );
-
-
-  //   F[rx_watermark]: 1:1
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_intr_enable_rx_watermark (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_enable_rx_watermark_we),
-    .wd     (intr_enable_rx_watermark_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_enable.rx_watermark.q ),
-
-    // to register interface (read)
-    .qs     (intr_enable_rx_watermark_qs)
-  );
-
-
-  //   F[tx_empty]: 2:2
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_intr_enable_tx_empty (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_enable_tx_empty_we),
-    .wd     (intr_enable_tx_empty_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_enable.tx_empty.q ),
-
-    // to register interface (read)
-    .qs     (intr_enable_tx_empty_qs)
-  );
-
-
-  //   F[rx_overflow]: 3:3
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_intr_enable_rx_overflow (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_enable_rx_overflow_we),
-    .wd     (intr_enable_rx_overflow_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_enable.rx_overflow.q ),
-
-    // to register interface (read)
-    .qs     (intr_enable_rx_overflow_qs)
-  );
-
-
-  //   F[rx_frame_err]: 4:4
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_intr_enable_rx_frame_err (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_enable_rx_frame_err_we),
-    .wd     (intr_enable_rx_frame_err_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_enable.rx_frame_err.q ),
-
-    // to register interface (read)
-    .qs     (intr_enable_rx_frame_err_qs)
-  );
-
-
-  //   F[rx_break_err]: 5:5
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_intr_enable_rx_break_err (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_enable_rx_break_err_we),
-    .wd     (intr_enable_rx_break_err_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_enable.rx_break_err.q ),
-
-    // to register interface (read)
-    .qs     (intr_enable_rx_break_err_qs)
-  );
-
-
-  //   F[rx_timeout]: 6:6
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_intr_enable_rx_timeout (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_enable_rx_timeout_we),
-    .wd     (intr_enable_rx_timeout_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_enable.rx_timeout.q ),
-
-    // to register interface (read)
-    .qs     (intr_enable_rx_timeout_qs)
-  );
-
-
-  //   F[rx_parity_err]: 7:7
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_intr_enable_rx_parity_err (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (intr_enable_rx_parity_err_we),
-    .wd     (intr_enable_rx_parity_err_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.intr_enable.rx_parity_err.q ),
-
-    // to register interface (read)
-    .qs     (intr_enable_rx_parity_err_qs)
-  );
-
-
-  // R[intr_test]: V(True)
-
-  //   F[tx_watermark]: 0:0
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_intr_test_tx_watermark (
-    .re     (1'b0),
-    .we     (intr_test_tx_watermark_we),
-    .wd     (intr_test_tx_watermark_wd),
-    .d      ('0),
-    .qre    (),
-    .qe     (reg2hw.intr_test.tx_watermark.qe),
-    .q      (reg2hw.intr_test.tx_watermark.q ),
-    .qs     ()
-  );
-
-
-  //   F[rx_watermark]: 1:1
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_intr_test_rx_watermark (
-    .re     (1'b0),
-    .we     (intr_test_rx_watermark_we),
-    .wd     (intr_test_rx_watermark_wd),
-    .d      ('0),
-    .qre    (),
-    .qe     (reg2hw.intr_test.rx_watermark.qe),
-    .q      (reg2hw.intr_test.rx_watermark.q ),
-    .qs     ()
-  );
-
-
-  //   F[tx_empty]: 2:2
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_intr_test_tx_empty (
-    .re     (1'b0),
-    .we     (intr_test_tx_empty_we),
-    .wd     (intr_test_tx_empty_wd),
-    .d      ('0),
-    .qre    (),
-    .qe     (reg2hw.intr_test.tx_empty.qe),
-    .q      (reg2hw.intr_test.tx_empty.q ),
-    .qs     ()
-  );
-
-
-  //   F[rx_overflow]: 3:3
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_intr_test_rx_overflow (
-    .re     (1'b0),
-    .we     (intr_test_rx_overflow_we),
-    .wd     (intr_test_rx_overflow_wd),
-    .d      ('0),
-    .qre    (),
-    .qe     (reg2hw.intr_test.rx_overflow.qe),
-    .q      (reg2hw.intr_test.rx_overflow.q ),
-    .qs     ()
-  );
-
-
-  //   F[rx_frame_err]: 4:4
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_intr_test_rx_frame_err (
-    .re     (1'b0),
-    .we     (intr_test_rx_frame_err_we),
-    .wd     (intr_test_rx_frame_err_wd),
-    .d      ('0),
-    .qre    (),
-    .qe     (reg2hw.intr_test.rx_frame_err.qe),
-    .q      (reg2hw.intr_test.rx_frame_err.q ),
-    .qs     ()
-  );
-
-
-  //   F[rx_break_err]: 5:5
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_intr_test_rx_break_err (
-    .re     (1'b0),
-    .we     (intr_test_rx_break_err_we),
-    .wd     (intr_test_rx_break_err_wd),
-    .d      ('0),
-    .qre    (),
-    .qe     (reg2hw.intr_test.rx_break_err.qe),
-    .q      (reg2hw.intr_test.rx_break_err.q ),
-    .qs     ()
-  );
-
-
-  //   F[rx_timeout]: 6:6
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_intr_test_rx_timeout (
-    .re     (1'b0),
-    .we     (intr_test_rx_timeout_we),
-    .wd     (intr_test_rx_timeout_wd),
-    .d      ('0),
-    .qre    (),
-    .qe     (reg2hw.intr_test.rx_timeout.qe),
-    .q      (reg2hw.intr_test.rx_timeout.q ),
-    .qs     ()
-  );
-
-
-  //   F[rx_parity_err]: 7:7
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_intr_test_rx_parity_err (
-    .re     (1'b0),
-    .we     (intr_test_rx_parity_err_we),
-    .wd     (intr_test_rx_parity_err_wd),
-    .d      ('0),
-    .qre    (),
-    .qe     (reg2hw.intr_test.rx_parity_err.qe),
-    .q      (reg2hw.intr_test.rx_parity_err.q ),
-    .qs     ()
-  );
-
-
-  // R[ctrl]: V(False)
-
-  //   F[tx]: 0:0
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_ctrl_tx (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ctrl_tx_we),
-    .wd     (ctrl_tx_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ctrl.tx.q ),
-
-    // to register interface (read)
-    .qs     (ctrl_tx_qs)
-  );
-
-
-  //   F[rx]: 1:1
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_ctrl_rx (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ctrl_rx_we),
-    .wd     (ctrl_rx_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ctrl.rx.q ),
-
-    // to register interface (read)
-    .qs     (ctrl_rx_qs)
-  );
-
-
-  //   F[nf]: 2:2
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_ctrl_nf (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ctrl_nf_we),
-    .wd     (ctrl_nf_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ctrl.nf.q ),
-
-    // to register interface (read)
-    .qs     (ctrl_nf_qs)
-  );
-
-
-  //   F[slpbk]: 4:4
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_ctrl_slpbk (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ctrl_slpbk_we),
-    .wd     (ctrl_slpbk_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ctrl.slpbk.q ),
-
-    // to register interface (read)
-    .qs     (ctrl_slpbk_qs)
-  );
-
-
-  //   F[llpbk]: 5:5
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_ctrl_llpbk (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ctrl_llpbk_we),
-    .wd     (ctrl_llpbk_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ctrl.llpbk.q ),
-
-    // to register interface (read)
-    .qs     (ctrl_llpbk_qs)
-  );
-
-
-  //   F[parity_en]: 6:6
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_ctrl_parity_en (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ctrl_parity_en_we),
-    .wd     (ctrl_parity_en_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ctrl.parity_en.q ),
-
-    // to register interface (read)
-    .qs     (ctrl_parity_en_qs)
-  );
-
-
-  //   F[parity_odd]: 7:7
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_ctrl_parity_odd (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ctrl_parity_odd_we),
-    .wd     (ctrl_parity_odd_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ctrl.parity_odd.q ),
-
-    // to register interface (read)
-    .qs     (ctrl_parity_odd_qs)
-  );
-
-
-  //   F[rxblvl]: 9:8
-  prim_subreg #(
-    .DW      (2),
-    .SWACCESS("RW"),
-    .RESVAL  (2'h0)
-  ) u_ctrl_rxblvl (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ctrl_rxblvl_we),
-    .wd     (ctrl_rxblvl_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ctrl.rxblvl.q ),
-
-    // to register interface (read)
-    .qs     (ctrl_rxblvl_qs)
-  );
-
-
-  //   F[nco]: 31:16
-  prim_subreg #(
-    .DW      (16),
-    .SWACCESS("RW"),
-    .RESVAL  (16'h0)
-  ) u_ctrl_nco (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ctrl_nco_we),
-    .wd     (ctrl_nco_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ctrl.nco.q ),
-
-    // to register interface (read)
-    .qs     (ctrl_nco_qs)
-  );
-
-
-  // R[status]: V(True)
-
-  //   F[txfull]: 0:0
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_status_txfull (
-    .re     (status_txfull_re),
-    .we     (1'b0),
-    .wd     ('0),
-    .d      (hw2reg.status.txfull.d),
-    .qre    (reg2hw.status.txfull.re),
-    .qe     (),
-    .q      (reg2hw.status.txfull.q ),
-    .qs     (status_txfull_qs)
-  );
-
-
-  //   F[rxfull]: 1:1
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_status_rxfull (
-    .re     (status_rxfull_re),
-    .we     (1'b0),
-    .wd     ('0),
-    .d      (hw2reg.status.rxfull.d),
-    .qre    (reg2hw.status.rxfull.re),
-    .qe     (),
-    .q      (reg2hw.status.rxfull.q ),
-    .qs     (status_rxfull_qs)
-  );
-
-
-  //   F[txempty]: 2:2
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_status_txempty (
-    .re     (status_txempty_re),
-    .we     (1'b0),
-    .wd     ('0),
-    .d      (hw2reg.status.txempty.d),
-    .qre    (reg2hw.status.txempty.re),
-    .qe     (),
-    .q      (reg2hw.status.txempty.q ),
-    .qs     (status_txempty_qs)
-  );
-
-
-  //   F[txidle]: 3:3
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_status_txidle (
-    .re     (status_txidle_re),
-    .we     (1'b0),
-    .wd     ('0),
-    .d      (hw2reg.status.txidle.d),
-    .qre    (reg2hw.status.txidle.re),
-    .qe     (),
-    .q      (reg2hw.status.txidle.q ),
-    .qs     (status_txidle_qs)
-  );
-
-
-  //   F[rxidle]: 4:4
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_status_rxidle (
-    .re     (status_rxidle_re),
-    .we     (1'b0),
-    .wd     ('0),
-    .d      (hw2reg.status.rxidle.d),
-    .qre    (reg2hw.status.rxidle.re),
-    .qe     (),
-    .q      (reg2hw.status.rxidle.q ),
-    .qs     (status_rxidle_qs)
-  );
-
-
-  //   F[rxempty]: 5:5
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_status_rxempty (
-    .re     (status_rxempty_re),
-    .we     (1'b0),
-    .wd     ('0),
-    .d      (hw2reg.status.rxempty.d),
-    .qre    (reg2hw.status.rxempty.re),
-    .qe     (),
-    .q      (reg2hw.status.rxempty.q ),
-    .qs     (status_rxempty_qs)
-  );
-
-
-  // R[rdata]: V(True)
-
-  prim_subreg_ext #(
-    .DW    (8)
-  ) u_rdata (
-    .re     (rdata_re),
-    .we     (1'b0),
-    .wd     ('0),
-    .d      (hw2reg.rdata.d),
-    .qre    (reg2hw.rdata.re),
-    .qe     (),
-    .q      (reg2hw.rdata.q ),
-    .qs     (rdata_qs)
-  );
-
-
-  // R[wdata]: V(False)
-
-  prim_subreg #(
-    .DW      (8),
-    .SWACCESS("WO"),
-    .RESVAL  (8'h0)
-  ) u_wdata (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (wdata_we),
-    .wd     (wdata_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (reg2hw.wdata.qe),
-    .q      (reg2hw.wdata.q ),
-
-    .qs     ()
-  );
-
-
-  // R[fifo_ctrl]: V(False)
-
-  //   F[rxrst]: 0:0
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("WO"),
-    .RESVAL  (1'h0)
-  ) u_fifo_ctrl_rxrst (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (fifo_ctrl_rxrst_we),
-    .wd     (fifo_ctrl_rxrst_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (reg2hw.fifo_ctrl.rxrst.qe),
-    .q      (reg2hw.fifo_ctrl.rxrst.q ),
-
-    .qs     ()
-  );
-
-
-  //   F[txrst]: 1:1
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("WO"),
-    .RESVAL  (1'h0)
-  ) u_fifo_ctrl_txrst (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (fifo_ctrl_txrst_we),
-    .wd     (fifo_ctrl_txrst_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (reg2hw.fifo_ctrl.txrst.qe),
-    .q      (reg2hw.fifo_ctrl.txrst.q ),
-
-    .qs     ()
-  );
-
-
-  //   F[rxilvl]: 4:2
-  prim_subreg #(
-    .DW      (3),
-    .SWACCESS("RW"),
-    .RESVAL  (3'h0)
-  ) u_fifo_ctrl_rxilvl (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (fifo_ctrl_rxilvl_we),
-    .wd     (fifo_ctrl_rxilvl_wd),
-
-    // from internal hardware
-    .de     (hw2reg.fifo_ctrl.rxilvl.de),
-    .d      (hw2reg.fifo_ctrl.rxilvl.d ),
-
-    // to internal hardware
-    .qe     (reg2hw.fifo_ctrl.rxilvl.qe),
-    .q      (reg2hw.fifo_ctrl.rxilvl.q ),
-
-    // to register interface (read)
-    .qs     (fifo_ctrl_rxilvl_qs)
-  );
-
-
-  //   F[txilvl]: 6:5
-  prim_subreg #(
-    .DW      (2),
-    .SWACCESS("RW"),
-    .RESVAL  (2'h0)
-  ) u_fifo_ctrl_txilvl (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (fifo_ctrl_txilvl_we),
-    .wd     (fifo_ctrl_txilvl_wd),
-
-    // from internal hardware
-    .de     (hw2reg.fifo_ctrl.txilvl.de),
-    .d      (hw2reg.fifo_ctrl.txilvl.d ),
-
-    // to internal hardware
-    .qe     (reg2hw.fifo_ctrl.txilvl.qe),
-    .q      (reg2hw.fifo_ctrl.txilvl.q ),
-
-    // to register interface (read)
-    .qs     (fifo_ctrl_txilvl_qs)
-  );
-
-
-  // R[fifo_status]: V(True)
-
-  //   F[txlvl]: 5:0
-  prim_subreg_ext #(
-    .DW    (6)
-  ) u_fifo_status_txlvl (
-    .re     (fifo_status_txlvl_re),
-    .we     (1'b0),
-    .wd     ('0),
-    .d      (hw2reg.fifo_status.txlvl.d),
-    .qre    (),
-    .qe     (),
-    .q      (),
-    .qs     (fifo_status_txlvl_qs)
-  );
-
-
-  //   F[rxlvl]: 21:16
-  prim_subreg_ext #(
-    .DW    (6)
-  ) u_fifo_status_rxlvl (
-    .re     (fifo_status_rxlvl_re),
-    .we     (1'b0),
-    .wd     ('0),
-    .d      (hw2reg.fifo_status.rxlvl.d),
-    .qre    (),
-    .qe     (),
-    .q      (),
-    .qs     (fifo_status_rxlvl_qs)
-  );
-
-
-  // R[ovrd]: V(False)
-
-  //   F[txen]: 0:0
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_ovrd_txen (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ovrd_txen_we),
-    .wd     (ovrd_txen_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ovrd.txen.q ),
-
-    // to register interface (read)
-    .qs     (ovrd_txen_qs)
-  );
-
-
-  //   F[txval]: 1:1
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_ovrd_txval (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (ovrd_txval_we),
-    .wd     (ovrd_txval_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ovrd.txval.q ),
-
-    // to register interface (read)
-    .qs     (ovrd_txval_qs)
-  );
-
-
-  // R[val]: V(True)
-
-  prim_subreg_ext #(
-    .DW    (16)
-  ) u_val (
-    .re     (val_re),
-    .we     (1'b0),
-    .wd     ('0),
-    .d      (hw2reg.val.d),
-    .qre    (),
-    .qe     (),
-    .q      (),
-    .qs     (val_qs)
-  );
-
-
-  // R[timeout_ctrl]: V(False)
-
-  //   F[val]: 23:0
-  prim_subreg #(
-    .DW      (24),
-    .SWACCESS("RW"),
-    .RESVAL  (24'h0)
-  ) u_timeout_ctrl_val (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (timeout_ctrl_val_we),
-    .wd     (timeout_ctrl_val_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.timeout_ctrl.val.q ),
-
-    // to register interface (read)
-    .qs     (timeout_ctrl_val_qs)
-  );
-
-
-  //   F[en]: 31:31
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_timeout_ctrl_en (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (timeout_ctrl_en_we),
-    .wd     (timeout_ctrl_en_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.timeout_ctrl.en.q ),
-
-    // to register interface (read)
-    .qs     (timeout_ctrl_en_qs)
-  );
-
-
-
-
-  logic [11:0] addr_hit;
-  always_comb begin
-    addr_hit = '0;
-    addr_hit[ 0] = (reg_addr == UART_INTR_STATE_OFFSET);
-    addr_hit[ 1] = (reg_addr == UART_INTR_ENABLE_OFFSET);
-    addr_hit[ 2] = (reg_addr == UART_INTR_TEST_OFFSET);
-    addr_hit[ 3] = (reg_addr == UART_CTRL_OFFSET);
-    addr_hit[ 4] = (reg_addr == UART_STATUS_OFFSET);
-    addr_hit[ 5] = (reg_addr == UART_RDATA_OFFSET);
-    addr_hit[ 6] = (reg_addr == UART_WDATA_OFFSET);
-    addr_hit[ 7] = (reg_addr == UART_FIFO_CTRL_OFFSET);
-    addr_hit[ 8] = (reg_addr == UART_FIFO_STATUS_OFFSET);
-    addr_hit[ 9] = (reg_addr == UART_OVRD_OFFSET);
-    addr_hit[10] = (reg_addr == UART_VAL_OFFSET);
-    addr_hit[11] = (reg_addr == UART_TIMEOUT_CTRL_OFFSET);
-  end
-
-  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-
-  // Check sub-word write is permitted
-  always_comb begin
-    wr_err = 1'b0;
-    if (addr_hit[ 0] && reg_we && (UART_PERMIT[ 0] != (UART_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 1] && reg_we && (UART_PERMIT[ 1] != (UART_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 2] && reg_we && (UART_PERMIT[ 2] != (UART_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 3] && reg_we && (UART_PERMIT[ 3] != (UART_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 4] && reg_we && (UART_PERMIT[ 4] != (UART_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 5] && reg_we && (UART_PERMIT[ 5] != (UART_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 6] && reg_we && (UART_PERMIT[ 6] != (UART_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 7] && reg_we && (UART_PERMIT[ 7] != (UART_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 8] && reg_we && (UART_PERMIT[ 8] != (UART_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[ 9] && reg_we && (UART_PERMIT[ 9] != (UART_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[10] && reg_we && (UART_PERMIT[10] != (UART_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
-    if (addr_hit[11] && reg_we && (UART_PERMIT[11] != (UART_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
-  end
-
-  assign intr_state_tx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
-  assign intr_state_tx_watermark_wd = reg_wdata[0];
-
-  assign intr_state_rx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
-  assign intr_state_rx_watermark_wd = reg_wdata[1];
-
-  assign intr_state_tx_empty_we = addr_hit[0] & reg_we & ~wr_err;
-  assign intr_state_tx_empty_wd = reg_wdata[2];
-
-  assign intr_state_rx_overflow_we = addr_hit[0] & reg_we & ~wr_err;
-  assign intr_state_rx_overflow_wd = reg_wdata[3];
-
-  assign intr_state_rx_frame_err_we = addr_hit[0] & reg_we & ~wr_err;
-  assign intr_state_rx_frame_err_wd = reg_wdata[4];
-
-  assign intr_state_rx_break_err_we = addr_hit[0] & reg_we & ~wr_err;
-  assign intr_state_rx_break_err_wd = reg_wdata[5];
-
-  assign intr_state_rx_timeout_we = addr_hit[0] & reg_we & ~wr_err;
-  assign intr_state_rx_timeout_wd = reg_wdata[6];
-
-  assign intr_state_rx_parity_err_we = addr_hit[0] & reg_we & ~wr_err;
-  assign intr_state_rx_parity_err_wd = reg_wdata[7];
-
-  assign intr_enable_tx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
-  assign intr_enable_tx_watermark_wd = reg_wdata[0];
-
-  assign intr_enable_rx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
-  assign intr_enable_rx_watermark_wd = reg_wdata[1];
-
-  assign intr_enable_tx_empty_we = addr_hit[1] & reg_we & ~wr_err;
-  assign intr_enable_tx_empty_wd = reg_wdata[2];
-
-  assign intr_enable_rx_overflow_we = addr_hit[1] & reg_we & ~wr_err;
-  assign intr_enable_rx_overflow_wd = reg_wdata[3];
-
-  assign intr_enable_rx_frame_err_we = addr_hit[1] & reg_we & ~wr_err;
-  assign intr_enable_rx_frame_err_wd = reg_wdata[4];
-
-  assign intr_enable_rx_break_err_we = addr_hit[1] & reg_we & ~wr_err;
-  assign intr_enable_rx_break_err_wd = reg_wdata[5];
-
-  assign intr_enable_rx_timeout_we = addr_hit[1] & reg_we & ~wr_err;
-  assign intr_enable_rx_timeout_wd = reg_wdata[6];
-
-  assign intr_enable_rx_parity_err_we = addr_hit[1] & reg_we & ~wr_err;
-  assign intr_enable_rx_parity_err_wd = reg_wdata[7];
-
-  assign intr_test_tx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
-  assign intr_test_tx_watermark_wd = reg_wdata[0];
-
-  assign intr_test_rx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
-  assign intr_test_rx_watermark_wd = reg_wdata[1];
-
-  assign intr_test_tx_empty_we = addr_hit[2] & reg_we & ~wr_err;
-  assign intr_test_tx_empty_wd = reg_wdata[2];
-
-  assign intr_test_rx_overflow_we = addr_hit[2] & reg_we & ~wr_err;
-  assign intr_test_rx_overflow_wd = reg_wdata[3];
-
-  assign intr_test_rx_frame_err_we = addr_hit[2] & reg_we & ~wr_err;
-  assign intr_test_rx_frame_err_wd = reg_wdata[4];
-
-  assign intr_test_rx_break_err_we = addr_hit[2] & reg_we & ~wr_err;
-  assign intr_test_rx_break_err_wd = reg_wdata[5];
-
-  assign intr_test_rx_timeout_we = addr_hit[2] & reg_we & ~wr_err;
-  assign intr_test_rx_timeout_wd = reg_wdata[6];
-
-  assign intr_test_rx_parity_err_we = addr_hit[2] & reg_we & ~wr_err;
-  assign intr_test_rx_parity_err_wd = reg_wdata[7];
-
-  assign ctrl_tx_we = addr_hit[3] & reg_we & ~wr_err;
-  assign ctrl_tx_wd = reg_wdata[0];
-
-  assign ctrl_rx_we = addr_hit[3] & reg_we & ~wr_err;
-  assign ctrl_rx_wd = reg_wdata[1];
-
-  assign ctrl_nf_we = addr_hit[3] & reg_we & ~wr_err;
-  assign ctrl_nf_wd = reg_wdata[2];
-
-  assign ctrl_slpbk_we = addr_hit[3] & reg_we & ~wr_err;
-  assign ctrl_slpbk_wd = reg_wdata[4];
-
-  assign ctrl_llpbk_we = addr_hit[3] & reg_we & ~wr_err;
-  assign ctrl_llpbk_wd = reg_wdata[5];
-
-  assign ctrl_parity_en_we = addr_hit[3] & reg_we & ~wr_err;
-  assign ctrl_parity_en_wd = reg_wdata[6];
-
-  assign ctrl_parity_odd_we = addr_hit[3] & reg_we & ~wr_err;
-  assign ctrl_parity_odd_wd = reg_wdata[7];
-
-  assign ctrl_rxblvl_we = addr_hit[3] & reg_we & ~wr_err;
-  assign ctrl_rxblvl_wd = reg_wdata[9:8];
-
-  assign ctrl_nco_we = addr_hit[3] & reg_we & ~wr_err;
-  assign ctrl_nco_wd = reg_wdata[31:16];
-
-  assign status_txfull_re = addr_hit[4] && reg_re;
-
-  assign status_rxfull_re = addr_hit[4] && reg_re;
-
-  assign status_txempty_re = addr_hit[4] && reg_re;
-
-  assign status_txidle_re = addr_hit[4] && reg_re;
-
-  assign status_rxidle_re = addr_hit[4] && reg_re;
-
-  assign status_rxempty_re = addr_hit[4] && reg_re;
-
-  assign rdata_re = addr_hit[5] && reg_re;
-
-  assign wdata_we = addr_hit[6] & reg_we & ~wr_err;
-  assign wdata_wd = reg_wdata[7:0];
-
-  assign fifo_ctrl_rxrst_we = addr_hit[7] & reg_we & ~wr_err;
-  assign fifo_ctrl_rxrst_wd = reg_wdata[0];
-
-  assign fifo_ctrl_txrst_we = addr_hit[7] & reg_we & ~wr_err;
-  assign fifo_ctrl_txrst_wd = reg_wdata[1];
-
-  assign fifo_ctrl_rxilvl_we = addr_hit[7] & reg_we & ~wr_err;
-  assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2];
-
-  assign fifo_ctrl_txilvl_we = addr_hit[7] & reg_we & ~wr_err;
-  assign fifo_ctrl_txilvl_wd = reg_wdata[6:5];
-
-  assign fifo_status_txlvl_re = addr_hit[8] && reg_re;
-
-  assign fifo_status_rxlvl_re = addr_hit[8] && reg_re;
-
-  assign ovrd_txen_we = addr_hit[9] & reg_we & ~wr_err;
-  assign ovrd_txen_wd = reg_wdata[0];
-
-  assign ovrd_txval_we = addr_hit[9] & reg_we & ~wr_err;
-  assign ovrd_txval_wd = reg_wdata[1];
-
-  assign val_re = addr_hit[10] && reg_re;
-
-  assign timeout_ctrl_val_we = addr_hit[11] & reg_we & ~wr_err;
-  assign timeout_ctrl_val_wd = reg_wdata[23:0];
-
-  assign timeout_ctrl_en_we = addr_hit[11] & reg_we & ~wr_err;
-  assign timeout_ctrl_en_wd = reg_wdata[31];
-
-  // Read data return
-  always_comb begin
-    reg_rdata_next = '0;
-    unique case (1'b1)
-      addr_hit[0]: begin
-        reg_rdata_next[0] = intr_state_tx_watermark_qs;
-        reg_rdata_next[1] = intr_state_rx_watermark_qs;
-        reg_rdata_next[2] = intr_state_tx_empty_qs;
-        reg_rdata_next[3] = intr_state_rx_overflow_qs;
-        reg_rdata_next[4] = intr_state_rx_frame_err_qs;
-        reg_rdata_next[5] = intr_state_rx_break_err_qs;
-        reg_rdata_next[6] = intr_state_rx_timeout_qs;
-        reg_rdata_next[7] = intr_state_rx_parity_err_qs;
-      end
-
-      addr_hit[1]: begin
-        reg_rdata_next[0] = intr_enable_tx_watermark_qs;
-        reg_rdata_next[1] = intr_enable_rx_watermark_qs;
-        reg_rdata_next[2] = intr_enable_tx_empty_qs;
-        reg_rdata_next[3] = intr_enable_rx_overflow_qs;
-        reg_rdata_next[4] = intr_enable_rx_frame_err_qs;
-        reg_rdata_next[5] = intr_enable_rx_break_err_qs;
-        reg_rdata_next[6] = intr_enable_rx_timeout_qs;
-        reg_rdata_next[7] = intr_enable_rx_parity_err_qs;
-      end
-
-      addr_hit[2]: begin
-        reg_rdata_next[0] = '0;
-        reg_rdata_next[1] = '0;
-        reg_rdata_next[2] = '0;
-        reg_rdata_next[3] = '0;
-        reg_rdata_next[4] = '0;
-        reg_rdata_next[5] = '0;
-        reg_rdata_next[6] = '0;
-        reg_rdata_next[7] = '0;
-      end
-
-      addr_hit[3]: begin
-        reg_rdata_next[0] = ctrl_tx_qs;
-        reg_rdata_next[1] = ctrl_rx_qs;
-        reg_rdata_next[2] = ctrl_nf_qs;
-        reg_rdata_next[4] = ctrl_slpbk_qs;
-        reg_rdata_next[5] = ctrl_llpbk_qs;
-        reg_rdata_next[6] = ctrl_parity_en_qs;
-        reg_rdata_next[7] = ctrl_parity_odd_qs;
-        reg_rdata_next[9:8] = ctrl_rxblvl_qs;
-        reg_rdata_next[31:16] = ctrl_nco_qs;
-      end
-
-      addr_hit[4]: begin
-        reg_rdata_next[0] = status_txfull_qs;
-        reg_rdata_next[1] = status_rxfull_qs;
-        reg_rdata_next[2] = status_txempty_qs;
-        reg_rdata_next[3] = status_txidle_qs;
-        reg_rdata_next[4] = status_rxidle_qs;
-        reg_rdata_next[5] = status_rxempty_qs;
-      end
-
-      addr_hit[5]: begin
-        reg_rdata_next[7:0] = rdata_qs;
-      end
-
-      addr_hit[6]: begin
-        reg_rdata_next[7:0] = '0;
-      end
-
-      addr_hit[7]: begin
-        reg_rdata_next[0] = '0;
-        reg_rdata_next[1] = '0;
-        reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs;
-        reg_rdata_next[6:5] = fifo_ctrl_txilvl_qs;
-      end
-
-      addr_hit[8]: begin
-        reg_rdata_next[5:0] = fifo_status_txlvl_qs;
-        reg_rdata_next[21:16] = fifo_status_rxlvl_qs;
-      end
-
-      addr_hit[9]: begin
-        reg_rdata_next[0] = ovrd_txen_qs;
-        reg_rdata_next[1] = ovrd_txval_qs;
-      end
-
-      addr_hit[10]: begin
-        reg_rdata_next[15:0] = val_qs;
-      end
-
-      addr_hit[11]: begin
-        reg_rdata_next[23:0] = timeout_ctrl_val_qs;
-        reg_rdata_next[31] = timeout_ctrl_en_qs;
-      end
-
-      default: begin
-        reg_rdata_next = '1;
-      end
-    endcase
-  end
-
-  // // Assertions for Register Interface
-  // `ASSERT_PULSE(wePulse, reg_we)
-  // `ASSERT_PULSE(rePulse, reg_re)
-
-  // `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
-
-  // `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
-
-  // // this is formulated as an assumption such that the FPV testbenches do disprove this
-  // // property by mistake
-  // `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
-
-endmodule
diff --git a/hw/ip/uart/rtl/uart_rx.sv b/hw/ip/uart/rtl/uart_rx.sv
deleted file mode 100644
index 829895a8..00000000
--- a/hw/ip/uart/rtl/uart_rx.sv
+++ /dev/null
@@ -1,105 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Description: UART Receive Module
-//
-
-module uart_rx (
-  input           clk_i,
-  input           rst_ni,
-
-  input           rx_enable,
-  input           tick_baud_x16,
-  input           parity_enable,
-  input           parity_odd,
-
-  output logic    tick_baud,
-  output logic    rx_valid,
-  output [7:0]    rx_data,
-  output logic    idle,
-  output          frame_err,
-  output          rx_parity_err,
-
-  input           rx
-);
-
-  logic            rx_valid_q;
-  logic   [10:0]   sreg_q, sreg_d;
-  logic    [3:0]   bit_cnt_q, bit_cnt_d;
-  logic    [3:0]   baud_div_q, baud_div_d;
-  logic            tick_baud_d, tick_baud_q;
-  logic            idle_d, idle_q;
-
-  assign tick_baud = tick_baud_q;
-  assign idle      = idle_q;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      sreg_q      <= 11'h0;
-      bit_cnt_q   <= 4'h0;
-      baud_div_q  <= 4'h0;
-      tick_baud_q <= 1'b0;
-      idle_q      <= 1'b1;
-    end else begin
-      sreg_q      <= sreg_d;
-      bit_cnt_q   <= bit_cnt_d;
-      baud_div_q  <= baud_div_d;
-      tick_baud_q <= tick_baud_d;
-      idle_q      <= idle_d;
-    end
-  end
-
-  always_comb begin
-    if (!rx_enable) begin
-      sreg_d      = 11'h0;
-      bit_cnt_d   = 4'h0;
-      baud_div_d  = 4'h0;
-      tick_baud_d = 1'b0;
-      idle_d      = 1'b1;
-    end else begin
-      tick_baud_d = 1'b0;
-      sreg_d      = sreg_q;
-      bit_cnt_d   = bit_cnt_q;
-      baud_div_d  = baud_div_q;
-      idle_d      = idle_q;
-      if (tick_baud_x16) begin
-        {tick_baud_d, baud_div_d} = {1'b0,baud_div_q} + 5'h1;
-      end
-
-      if (idle_q && !rx) begin
-        // start of char, sample in the middle of the bit time
-        baud_div_d  = 4'd8;
-        tick_baud_d = 1'b0;
-        bit_cnt_d   = (parity_enable ? 4'd11 : 4'd10);
-        sreg_d      = 11'h0;
-        idle_d      = 1'b0;
-      end else if (!idle_q && tick_baud_q) begin
-        if ((bit_cnt_q == (parity_enable ? 4'd11 : 4'd10)) && rx) begin
-          // must have been a glitch on the input, start bit is not set
-          // in the middle of the bit time, abort
-          idle_d    = 1'b1;
-          bit_cnt_d = 4'h0;
-        end else begin
-          sreg_d    = {rx, sreg_q[10:1]};
-          bit_cnt_d = bit_cnt_q - 4'h1;
-          idle_d    = (bit_cnt_q == 4'h1);
-        end
-      end
-    end
-  end
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) rx_valid_q <= 1'b0;
-    else         rx_valid_q <= tick_baud_q & (bit_cnt_q == 4'h1);
-
-  end
-
-  assign rx_valid      = rx_valid_q;
-  assign rx_data       = parity_enable ? sreg_q[8:1] : sreg_q[9:2];
-  //    (rx_parity     = sreg_q[9])
-  assign frame_err     = rx_valid_q & ~sreg_q[10];
-  assign rx_parity_err = parity_enable & rx_valid_q &
-                         (^{sreg_q[9:1],parity_odd});
-
-endmodule
diff --git a/hw/ip/uart/rtl/uart_rx.v b/hw/ip/uart/rtl/uart_rx.v
new file mode 100644
index 00000000..80a7928d
--- /dev/null
+++ b/hw/ip/uart/rtl/uart_rx.v
@@ -0,0 +1,157 @@
+`timescale 1ns / 1ps
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Set Parameter CLKS_PER_BIT as follows:
+// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
+// Example: 10 MHz Clock, 115200 baud UART
+// (10000000)/(115200) = 87
+  
+module uart_rx (
+   input  wire       clk_i,
+   input  wire       rst_ni,
+   input  wire       i_Rx_Serial,
+   input  wire [15:0] CLKS_PER_BIT,
+   output wire        o_Rx_DV,
+   output wire  [7:0] o_Rx_Byte
+   );
+    
+  parameter s_IDLE         = 3'b000;
+  parameter s_RX_START_BIT = 3'b001;
+  parameter s_RX_DATA_BITS = 3'b010;
+  parameter s_RX_STOP_BIT  = 3'b011;
+  parameter s_CLEANUP      = 3'b100;
+   
+  reg           r_Rx_Data_R ;
+  reg           r_Rx_Data   ;
+   
+  reg [15:0]     r_Clock_Count ;
+  reg [2:0]     r_Bit_Index  ; //8 bits total
+  reg [7:0]     r_Rx_Byte   ;
+  reg           r_Rx_DV     ;
+  reg [2:0]     r_SM_Main   ;
+   
+  // Purpose: Double-register the incoming data.
+  // This allows it to be used in the UART RX Clock Domain.
+  // (It removes problems caused by metastability)
+  always @(posedge clk_i)
+    begin
+    if (~rst_ni) begin
+      r_Rx_Data_R <= 1'b1;
+      r_Rx_Data   <= 1'b1;
+    end else begin
+      r_Rx_Data_R <= i_Rx_Serial;
+      r_Rx_Data   <= r_Rx_Data_R;
+    end
+  end
+   
+   
+  // Purpose: Control RX state machine
+  always @(posedge clk_i or negedge rst_ni)
+    begin
+      if (~rst_ni) begin
+        r_SM_Main <= s_IDLE;
+        r_Rx_DV       <= 1'b0;
+        r_Clock_Count <= 16'b0;
+        r_Bit_Index   <= 3'b0;
+	r_Rx_Byte     <= 8'b0;
+      end else begin       
+      case (r_SM_Main)
+        s_IDLE :
+          begin
+            r_Rx_DV       <= 1'b0;
+            r_Clock_Count <= 16'b0;
+            r_Bit_Index   <= 3'b0;
+            r_Rx_Byte     <= 8'b0; 
+            if (r_Rx_Data == 1'b0)          // Start bit detected
+              r_SM_Main <= s_RX_START_BIT;
+            else
+              r_SM_Main <= s_IDLE;
+          end
+         
+        // Check middle of start bit to make sure it's still low
+        s_RX_START_BIT :
+          begin
+            if (r_Clock_Count == ((CLKS_PER_BIT-1)>>1))
+              begin
+                if (r_Rx_Data == 1'b0)
+                  begin
+                    r_Clock_Count <= 16'b0;  // reset counter, found the middle
+                    r_SM_Main     <= s_RX_DATA_BITS;
+                  end
+                else
+                  r_SM_Main <= s_IDLE;
+              end
+            else
+              begin
+                r_Clock_Count <= r_Clock_Count + 16'b1;
+                r_SM_Main     <= s_RX_START_BIT;
+              end
+          end // case: s_RX_START_BIT
+         
+         
+        // Wait CLKS_PER_BIT-1 clock cycles to sample serial data
+        s_RX_DATA_BITS :
+          begin
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 16'b1;
+                r_SM_Main     <= s_RX_DATA_BITS;
+              end
+            else
+              begin
+                r_Clock_Count          <= 16'b0;
+                r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
+                 
+                // Check if we have received all bits
+                if (r_Bit_Index < 7)
+                  begin
+                    r_Bit_Index <= r_Bit_Index + 3'b1;
+                    r_SM_Main   <= s_RX_DATA_BITS;
+                  end
+                else
+                  begin
+                    r_Bit_Index <= 3'b0;
+                    r_SM_Main   <= s_RX_STOP_BIT;
+                  end
+              end
+          end // case: s_RX_DATA_BITS
+     
+     
+        // Receive Stop bit.  Stop bit = 1
+        s_RX_STOP_BIT :
+          begin
+            // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 16'b1;
+                r_SM_Main     <= s_RX_STOP_BIT;
+              end
+            else
+              begin
+                r_Rx_DV       <= 1'b1;
+                r_Clock_Count <= 16'b0;
+                r_SM_Main     <= s_CLEANUP;
+              end
+          end // case: s_RX_STOP_BIT
+     
+         
+        // Stay here 1 clock
+        s_CLEANUP :
+          begin
+            r_SM_Main <= s_IDLE;
+            r_Rx_DV   <= 1'b0;
+          end
+         
+         
+        default :
+          r_SM_Main <= s_IDLE;
+         
+      endcase
+      end
+    end   
+   
+  assign o_Rx_DV   = r_Rx_DV;
+  assign o_Rx_Byte = r_Rx_Byte;
+   
+endmodule // uart_rx
diff --git a/hw/ip/uart/rtl/uart_top.sv b/hw/ip/uart/rtl/uart_top.sv
new file mode 100644
index 00000000..cd2c9e76
--- /dev/null
+++ b/hw/ip/uart/rtl/uart_top.sv
@@ -0,0 +1,64 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: UART top level wrapper file
+
+// `include "prim_assert.sv"
+
+module uart_top (
+    input logic clk_i,
+    input logic rst_ni,
+
+  // Bus Interface
+    input  tlul_pkg::tl_h2d_t tl_i,
+    output tlul_pkg::tl_d2h_t tl_o,
+   
+    output logic tx_o,
+    input  logic rx_i,
+    
+    output logic intr_tx
+);
+    
+    logic [31:0] wdata;
+    logic [7:0] addr;
+    logic        we;
+    logic        re;
+    logic [31:0] rdata;
+    logic [3:0]  be;
+    
+uart_core u_uart_core(
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+    
+    .ren     (re),
+    .we      (we),
+    .wdata   (wdata),
+    .rdata   (rdata),
+    .addr    (addr),    
+    .tx_o    (tx_o),
+    .rx_i    (rx_i),
+    
+    .intr_tx (intr_tx)
+);
+
+    
+ tlul_adapter_reg #(
+    .RegAw(8),
+    .RegDw(32)
+ ) u_reg_if (
+   .clk_i,
+   .rst_ni,
+    
+   .tl_i (tl_i),
+   .tl_o (tl_o),
+    
+   .we_o    (we),
+   .re_o    (re),
+   .addr_o  (addr),
+   .wdata_o (wdata),
+   .be_o    (be),
+   .rdata_i (rdata),
+   .error_i (1'b0)
+);
+endmodule
diff --git a/hw/ip/uart/rtl/uart_tx.sv b/hw/ip/uart/rtl/uart_tx.sv
deleted file mode 100644
index d10d16a6..00000000
--- a/hw/ip/uart/rtl/uart_tx.sv
+++ /dev/null
@@ -1,79 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Description: UART Transmit Module
-//
-
-module uart_tx (
-  input               clk_i,
-  input               rst_ni,
-
-  input               tx_enable,
-  input               tick_baud_x16,
-  input  logic        parity_enable,
-
-  input               wr,
-  input  logic        wr_parity,
-  input   [7:0]       wr_data,
-  output              idle,
-
-  output logic        tx
-);
-
-
-  logic    [3:0] baud_div_q;
-  logic          tick_baud_q;
-
-  logic    [3:0] bit_cnt_q, bit_cnt_d;
-  logic   [10:0] sreg_q, sreg_d;
-  logic          tx_q, tx_d;
-
-  assign tx = tx_q;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      baud_div_q  <= 4'h0;
-      tick_baud_q <= 1'b0;
-    end else if (tick_baud_x16) begin
-      {tick_baud_q, baud_div_q} <= {1'b0,baud_div_q} + 5'h1;
-    end else begin
-      tick_baud_q <= 1'b0;
-    end
-  end
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      bit_cnt_q <= 4'h0;
-      sreg_q    <= 11'h7ff;
-      tx_q      <= 1'b1;
-    end else begin
-      bit_cnt_q <= bit_cnt_d;
-      sreg_q    <= sreg_d;
-      tx_q      <= tx_d;
-    end
-  end
-
-  always_comb begin
-    if (!tx_enable) begin
-      bit_cnt_d = 4'h0;
-      sreg_d    = 11'h7ff;
-      tx_d      = 1'b1;
-    end else begin
-      bit_cnt_d = bit_cnt_q;
-      sreg_d    = sreg_q;
-      tx_d      = tx_q;
-      if (wr) begin
-        sreg_d    = {1'b1, (parity_enable ? wr_parity : 1'b1), wr_data, 1'b0};
-        bit_cnt_d = (parity_enable ? 4'd11 : 4'd10);
-      end else if (tick_baud_q && (bit_cnt_q != 4'h0)) begin
-        sreg_d    = {1'b1, sreg_q[10:1]};
-        tx_d      = sreg_q[0];
-        bit_cnt_d = bit_cnt_q - 4'h1;
-      end
-    end
-  end
-
-  assign idle = (tx_enable) ? (bit_cnt_q == 4'h0) : 1'b1;
-
-endmodule
diff --git a/hw/ip/uart/rtl/uart_tx.v b/hw/ip/uart/rtl/uart_tx.v
new file mode 100644
index 00000000..3230a2a5
--- /dev/null
+++ b/hw/ip/uart/rtl/uart_tx.v
@@ -0,0 +1,142 @@
+module uart_tx (
+   input wire      clk_i,
+   input wire      rst_ni,
+   input wire      tx_en,
+   input wire [7:0] i_TX_Byte, 
+   input wire [15:0]CLKS_PER_BIT,
+   //output      o_TX_Active,
+   output reg  o_TX_Serial,
+   output wire     o_TX_Done
+   );
+ 
+  localparam IDLE         = 3'b000;
+  localparam TX_START_BIT = 3'b001;
+  localparam TX_DATA_BITS = 3'b010;
+  localparam TX_STOP_BIT  = 3'b011;
+  localparam CLEANUP      = 3'b100;
+  
+  reg [2:0] r_SM_Main     ;
+  reg [15:0] r_Clock_Count ;
+  reg [2:0] r_Bit_Index   ;
+  reg [7:0] r_TX_Data     ;
+  reg       r_TX_Done     ;
+//  reg       r_TX_Active   ;
+    
+  always @(posedge clk_i)
+  begin
+    if(~rst_ni) begin
+        r_SM_Main     <= 3'b0;
+        r_Clock_Count <= 16'b0;
+        r_Bit_Index   <= 3'b0;
+        r_TX_Data     <= 8'b0;
+        r_TX_Done     <= 1'b0;
+       // r_TX_Active   = 0;
+    end else begin
+    case (r_SM_Main)
+      IDLE :
+        begin
+          o_TX_Serial   <= 1'b1;         // Drive Line High for Idle
+          r_TX_Done     <= 1'b0;
+          r_Clock_Count <= 16'b0;
+          r_Bit_Index   <= 3'b0;
+          
+          if (tx_en == 1'b1)
+          begin
+           // r_TX_Active <= 1'b1;
+            r_TX_Data   <= i_TX_Byte;
+            r_SM_Main   <= TX_START_BIT;
+          end
+          else
+            r_SM_Main <= IDLE;
+        end // case: IDLE
+      
+      
+      // Send out Start Bit. Start bit = 0
+      TX_START_BIT :
+        begin
+          o_TX_Serial <= 1'b0;
+          
+          // Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
+          if (r_Clock_Count < CLKS_PER_BIT-1)
+          begin
+            r_Clock_Count <= r_Clock_Count + 16'b1;
+            r_SM_Main     <= TX_START_BIT;
+          end
+          else
+          begin
+            r_Clock_Count <= 16'b0;
+            r_SM_Main     <= TX_DATA_BITS;
+          end
+        end // case: TX_START_BIT
+      
+      
+      // Wait CLKS_PER_BIT-1 clock cycles for data bits to finish         
+      TX_DATA_BITS :
+        begin
+          o_TX_Serial <= r_TX_Data[r_Bit_Index];
+          
+          if (r_Clock_Count < CLKS_PER_BIT-16'b1)
+          begin
+            r_Clock_Count <= r_Clock_Count + 16'b1;
+            r_SM_Main     <= TX_DATA_BITS;
+          end
+          else
+          begin
+            r_Clock_Count <= 3'b0;
+            
+            // Check if we have sent out all bits
+            if (r_Bit_Index < 7)
+            begin
+              r_Bit_Index <= r_Bit_Index + 3'b1;
+              r_SM_Main   <= TX_DATA_BITS;
+            end
+            else
+            begin
+              r_Bit_Index <= 3'b0;
+              r_SM_Main   <= TX_STOP_BIT;
+            end
+          end 
+        end // case: TX_DATA_BITS
+      
+      
+      // Send out Stop bit.  Stop bit = 1
+      TX_STOP_BIT :
+        begin
+          o_TX_Serial <= 1'b1;
+          
+          // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
+          if (r_Clock_Count < CLKS_PER_BIT- 16'b1)
+          begin
+            r_Clock_Count <= r_Clock_Count + 16'b1;
+            r_SM_Main     <= TX_STOP_BIT;
+          end
+          else
+          begin
+            r_TX_Done     <= 1'b1;
+            r_Clock_Count <= 16'b0;
+            r_SM_Main     <= CLEANUP;
+           // r_TX_Active   <= 1'b0;
+          end 
+        end // case: TX_STOP_BIT
+      
+      
+      // Stay here 1 clock
+      CLEANUP :
+        begin
+          r_TX_Done <= 1'b1;
+          r_SM_Main <= IDLE;
+        end
+      
+      
+      default :
+        r_SM_Main <= IDLE;
+      
+    endcase
+    end 
+  end
+  
+  //assign o_TX_Active = r_TX_Active;
+  assign o_TX_Done   = r_TX_Done;
+  
+endmodule
+