diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson index 103cd817148bc..cae890d7a0491 100644 --- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson +++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson @@ -172,6 +172,21 @@ package: "flash_ctrl_pkg" } + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + act: "rcv", + package: "ast_pkg" + } + + { struct: "logic", + type: "uni", + name: "fla_obs", + act: "req", + width: "8", + package: "" + } + ], countermeasures: [ { name: "BUS.INTEGRITY", diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl index 41a9c997819b3..6204e70c706a2 100644 --- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl +++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl @@ -179,6 +179,21 @@ package: "flash_ctrl_pkg" } + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + act: "rcv", + package: "ast_pkg" + } + + { struct: "logic", + type: "uni", + name: "fla_obs", + act: "req", + width: "8", + package: "" + } + ], countermeasures: [ { name: "BUS.INTEGRITY", diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl index 47659d40f4b0b..ea88fd2b6e5ee 100644 --- a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl +++ b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl @@ -72,6 +72,10 @@ module flash_ctrl input prim_alert_pkg::alert_rx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_rx_i, output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o, + // Observability + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + output logic [7:0] fla_obs_o, + // Flash test interface input scan_en_i, input prim_mubi_pkg::mubi4_t scanmode_i, @@ -1162,6 +1166,8 @@ module flash_ctrl .flash_ctrl_o (flash_phy_rsp), .tl_i (prim_tl_i), .tl_o (prim_tl_o), + .obs_ctrl_i, + .fla_obs_o, .lc_nvm_debug_en_i, .flash_bist_enable_i, .flash_power_down_h_i, diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv index 9dde39025b4e3..71a87eafd69ef 100644 --- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv +++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv @@ -72,6 +72,10 @@ module flash_ctrl input prim_alert_pkg::alert_rx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_rx_i, output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o, + // Observability + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + output logic [7:0] fla_obs_o, + // Flash test interface input scan_en_i, input prim_mubi_pkg::mubi4_t scanmode_i, @@ -1163,6 +1167,8 @@ module flash_ctrl .flash_ctrl_o (flash_phy_rsp), .tl_i (prim_tl_i), .tl_o (prim_tl_o), + .obs_ctrl_i, + .fla_obs_o, .lc_nvm_debug_en_i, .flash_bist_enable_i, .flash_power_down_h_i, diff --git a/hw/ip/flash_ctrl/rtl/flash_phy.sv b/hw/ip/flash_ctrl/rtl/flash_phy.sv index be0e28c805e3d..05b1542dab3f4 100644 --- a/hw/ip/flash_ctrl/rtl/flash_phy.sv +++ b/hw/ip/flash_ctrl/rtl/flash_phy.sv @@ -38,6 +38,8 @@ module flash_phy inout flash_test_voltage_h_io, input prim_mubi_pkg::mubi4_t flash_bist_enable_i, input lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i, + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + output logic [7:0] fla_obs_o, output ast_pkg::ast_dif_t flash_alert_o ); @@ -302,6 +304,8 @@ module flash_phy .tms_i(flash_ctrl_i.jtag_req.tms & (lc_nvm_debug_en[FlashLcTmsSel] == lc_ctrl_pkg::On)), .tdo_o(tdo), .bist_enable_i(bist_enable_qual), + .obs_ctrl_i, + .fla_obs_o, .scanmode_i, .scan_en_i, .scan_rst_ni, diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson b/hw/ip/otp_ctrl/data/otp_ctrl.hjson index 36b6da6fe3357..9fe47834f1653 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson +++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson @@ -897,6 +897,21 @@ default: "'0" package: "otp_ctrl_part_pkg" } + // AST observability control + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + act: "rcv", + package: "ast_pkg" + } + // prim otp observe bus + { struct: "logic", + type: "uni", + name: "otp_obs", + act: "req", + width: "8", + package: "" + } ] // inter_signal_list ///////////////////// diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl index ecbae2dfd101e..d20cd95786f62 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl +++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl @@ -326,6 +326,21 @@ default: "'0" package: "otp_ctrl_part_pkg" } + // AST observability control + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + act: "rcv", + package: "ast_pkg" + } + // prim otp observe bus + { struct: "logic", + type: "uni", + name: "otp_obs", + act: "req", + width: "8", + package: "" + } ] // inter_signal_list ///////////////////// diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv index 3280cf54ea9cc..fcaf5d8e9ffc9 100644 --- a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv +++ b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv @@ -40,6 +40,9 @@ module otp_ctrl // Alerts input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // Observability to AST + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + output logic [7:0] otp_obs_o, // Macro-specific power sequencing signals to/from AST. output otp_ast_req_t otp_ast_pwr_seq_o, input otp_ast_rsp_t otp_ast_pwr_seq_h_i, @@ -747,6 +750,9 @@ module otp_ctrl ) u_otp ( .clk_i, .rst_ni, + // Observability controls to/from AST + .obs_ctrl_i, + .otp_obs_o, // Power sequencing signals to/from AST .pwr_seq_o ( otp_ast_pwr_seq_o.pwr_seq ), .pwr_seq_h_i ( otp_ast_pwr_seq_h_i.pwr_seq_h ), diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash.sv b/hw/ip/prim_generic/rtl/prim_generic_flash.sv index d2233d7ea3102..9a221327b1cfb 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flash.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flash.sv @@ -37,6 +37,9 @@ module prim_generic_flash #( output ast_pkg::ast_dif_t fl_alert_src_o, input tlul_pkg::tl_h2d_t tl_i, output tlul_pkg::tl_d2h_t tl_o, + // Observability + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + output logic [7:0] fla_obs_o, input devmode_i ); @@ -175,7 +178,9 @@ module prim_generic_flash #( // default alert assignments assign fl_alert_src_o = '{p: '0, n: '1}; - + logic unused_obs; + assign unused_obs = |obs_ctrl_i; + assign fla_obs_o = '0; endmodule // prim_generic_flash diff --git a/hw/ip/prim_generic/rtl/prim_generic_otp.sv b/hw/ip/prim_generic/rtl/prim_generic_otp.sv index 882fe0be55afa..5ed2191b27b7c 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_otp.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_otp.sv @@ -30,6 +30,9 @@ module prim_generic_otp ) ( input clk_i, input rst_ni, + // Observability + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + output logic [7:0] otp_obs_o, // Macro-specific power sequencing signals to/from AST output logic [PwrSeqWidth-1:0] pwr_seq_o, input [PwrSeqWidth-1:0] pwr_seq_h_i, @@ -72,6 +75,10 @@ module prim_generic_otp assign unused_pwr_seq_h = pwr_seq_h_i; assign pwr_seq_o = '0; + logic unused_obs; + assign unused_obs = |obs_ctrl_i; + assign otp_obs_o = '0; + wire unused_ext_voltage; assign unused_ext_voltage = ext_voltage_io; logic unused_test_ctrl_i; diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 4624edd17e061..28ff5d4d8d7f3 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -1578,6 +1578,31 @@ top_signame: otp_ctrl_otp_hw_cfg index: -1 } + { + name: obs_ctrl + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: otp_ctrl + default: "" + top_signame: ast_obs_ctrl + index: -1 + } + { + name: otp_obs + struct: logic + type: uni + act: req + width: 8 + inst_name: otp_ctrl + default: "" + package: "" + external: true + top_signame: otp_obs + index: -1 + } { name: core_tl struct: tl @@ -4462,6 +4487,31 @@ top_signame: flash_ctrl_keymgr index: -1 } + { + name: obs_ctrl + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_ctrl + default: "" + top_signame: ast_obs_ctrl + index: -1 + } + { + name: fla_obs + struct: logic + type: uni + act: req + width: 8 + inst_name: flash_ctrl + default: "" + package: "" + external: true + top_signame: flash_obs + index: -1 + } { name: core_tl struct: tl @@ -7226,6 +7276,21 @@ index: -1 external: true } + { + struct: ast_obs_ctrl + type: uni + name: obs_ctrl + act: rcv + package: ast_pkg + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_obs_ctrl + index: -1 + external: true + } ] } ] @@ -7233,6 +7298,11 @@ { connect: { + ast.obs_ctrl: + [ + flash_ctrl.obs_ctrl + otp_ctrl.obs_ctrl + ] ast.ram_1p_cfg: [ otbn.ram_cfg @@ -7817,6 +7887,7 @@ adc_ctrl_aon.adc: adc ast.edn: "" ast.lc_dft_en: "" + ast.obs_ctrl: obs_ctrl ast.ram_1p_cfg: ram_1p_cfg ast.ram_2p_cfg: ram_2p_cfg ast.rom_cfg: rom_cfg @@ -7831,7 +7902,8 @@ flash_ctrl.flash_power_down_h: flash_power_down_h flash_ctrl.flash_power_ready_h: flash_power_ready_h flash_ctrl.flash_test_mode_a: flash_test_mode_a - "flash_ctrl.flash_test_voltage_h ": flash_test_voltage_h + flash_ctrl.flash_test_voltage_h: flash_test_voltage_h + flash_ctrl.fla_obs: flash_obs entropy_src.entropy_src_rng: es_rng entropy_src.rng_fips: es_rng_fips peri.tl_ast: ast_tl @@ -7842,6 +7914,7 @@ otp_ctrl.otp_ast_pwr_seq_h: "" otp_ctrl.otp_ext_voltage_h: otp_ext_voltage_h otp_ctrl.otp_alert: otp_alert + otp_ctrl.otp_obs: otp_obs rstmgr_aon.por_n: por_n sensor_ctrl.ast_alert: sensor_ctrl_ast_alert sensor_ctrl.ast_status: sensor_ctrl_ast_status @@ -14737,6 +14810,31 @@ top_signame: otp_ctrl_otp_hw_cfg index: -1 } + { + name: obs_ctrl + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: otp_ctrl + default: "" + top_signame: ast_obs_ctrl + index: -1 + } + { + name: otp_obs + struct: logic + type: uni + act: req + width: 8 + inst_name: otp_ctrl + default: "" + package: "" + external: true + top_signame: otp_obs + index: -1 + } { name: core_tl struct: tl @@ -16643,6 +16741,31 @@ top_signame: flash_ctrl_keymgr index: -1 } + { + name: obs_ctrl + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_ctrl + default: "" + top_signame: ast_obs_ctrl + index: -1 + } + { + name: fla_obs + struct: logic + type: uni + act: req + width: 8 + inst_name: flash_ctrl + default: "" + package: "" + external: true + top_signame: flash_obs + index: -1 + } { name: core_tl struct: tl @@ -18705,6 +18828,21 @@ index: -1 external: true } + { + struct: ast_obs_ctrl + type: uni + name: obs_ctrl + act: rcv + package: ast_pkg + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_obs_ctrl + index: -1 + external: true + } ] external: [ @@ -18768,6 +18906,18 @@ index: -1 netname: lc_ctrl_lc_dft_en } + { + package: ast_pkg + struct: ast_obs_ctrl + signame: obs_ctrl_i + width: 1 + type: uni + default: "" + direction: in + conn_type: true + index: -1 + netname: ast_obs_ctrl + } { package: prim_ram_1p_pkg struct: ram_1p_cfg @@ -18948,6 +19098,18 @@ index: -1 netname: flash_test_voltage_h } + { + package: "" + struct: logic + signame: flash_obs_o + width: 8 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: flash_obs + } { package: entropy_src_pkg struct: entropy_src_rng_req @@ -19104,6 +19266,18 @@ index: -1 netname: otp_alert } + { + package: "" + struct: logic + signame: otp_obs_o + width: 8 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: otp_obs + } { package: "" struct: logic @@ -19215,6 +19389,17 @@ ] definitions: [ + { + package: ast_pkg + struct: ast_obs_ctrl + signame: ast_obs_ctrl + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: ast_pkg::AST_OBS_CTRL_DEFAULT + } { package: prim_ram_1p_pkg struct: ram_1p_cfg diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 4b43dacd44894..80d3f0ca11543 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -774,6 +774,15 @@ // what the external module actually needs. act: "rcv" } + + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "rcv", + package: "ast_pkg", + }, ] }, ] @@ -786,6 +795,8 @@ // e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl] inter_module: { 'connect': { + 'ast.obs_ctrl' : ['flash_ctrl.obs_ctrl', + 'otp_ctrl.obs_ctrl'] 'ast.ram_1p_cfg' : ['otbn.ram_cfg', 'sram_ctrl_main.cfg', 'sram_ctrl_ret_aon.cfg', @@ -983,6 +994,7 @@ 'adc_ctrl_aon.adc' : 'adc' 'ast.edn' : '', 'ast.lc_dft_en' : '', + 'ast.obs_ctrl' : 'obs_ctrl', 'ast.ram_1p_cfg' : 'ram_1p_cfg', 'ast.ram_2p_cfg' : 'ram_2p_cfg', 'ast.rom_cfg' : 'rom_cfg', @@ -997,7 +1009,8 @@ 'flash_ctrl.flash_power_down_h' : 'flash_power_down_h', 'flash_ctrl.flash_power_ready_h' : 'flash_power_ready_h', 'flash_ctrl.flash_test_mode_a' : 'flash_test_mode_a', - 'flash_ctrl.flash_test_voltage_h ': 'flash_test_voltage_h', + 'flash_ctrl.flash_test_voltage_h' : 'flash_test_voltage_h', + 'flash_ctrl.fla_obs' : 'flash_obs', 'entropy_src.entropy_src_rng' : 'es_rng', 'entropy_src.rng_fips' : 'es_rng_fips', 'peri.tl_ast' : 'ast_tl', @@ -1008,6 +1021,7 @@ 'otp_ctrl.otp_ast_pwr_seq_h' : '', 'otp_ctrl.otp_ext_voltage_h' : 'otp_ext_voltage_h', 'otp_ctrl.otp_alert' : 'otp_alert', + 'otp_ctrl.otp_obs' : 'otp_obs', 'rstmgr_aon.por_n' : 'por_n' 'sensor_ctrl.ast_alert' : 'sensor_ctrl_ast_alert', 'sensor_ctrl.ast_status' : 'sensor_ctrl_ast_status', diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson index 7b2c0a0205558..48ffef160c63d 100644 --- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson +++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson @@ -178,6 +178,21 @@ package: "flash_ctrl_pkg" } + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + act: "rcv", + package: "ast_pkg" + } + + { struct: "logic", + type: "uni", + name: "fla_obs", + act: "req", + width: "8", + package: "" + } + ], countermeasures: [ { name: "BUS.INTEGRITY", diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv index d018f5f75f2b9..6d691b3d3de24 100644 --- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv +++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv @@ -78,6 +78,10 @@ module flash_ctrl input prim_alert_pkg::alert_rx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_rx_i, output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o, + // Observability + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + output logic [7:0] fla_obs_o, + // Flash test interface input scan_en_i, input prim_mubi_pkg::mubi4_t scanmode_i, @@ -1169,6 +1173,8 @@ module flash_ctrl .flash_ctrl_o (flash_phy_rsp), .tl_i (prim_tl_i), .tl_o (prim_tl_o), + .obs_ctrl_i, + .fla_obs_o, .lc_nvm_debug_en_i, .flash_bist_enable_i, .flash_power_down_h_i, diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index 4e0adc5ba31cd..b6f93b61e0153 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv @@ -708,13 +708,10 @@ module chip_earlgrey_asic ( logic sck_monitor; // observe interface - logic [8-1:0] fla_obs; - logic [8-1:0] otp_obs; + logic [7:0] fla_obs; + logic [7:0] otp_obs; ast_pkg::ast_obs_ctrl_t obs_ctrl; - assign fla_obs = 8'h00; - assign otp_obs = 8'h00; - // otp power sequence otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq; otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h; @@ -1144,13 +1141,16 @@ module chip_earlgrey_asic ( .adc_rsp_i ( adc_rsp ), .ast_edn_req_i ( ast_edn_edn_req ), .ast_edn_rsp_o ( ast_edn_edn_rsp ), + .obs_ctrl_i ( obs_ctrl ), .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), .otp_alert_o ( otp_alert ), + .otp_obs_o ( otp_obs ), .flash_bist_enable_i ( flash_bist_enable ), .flash_power_down_h_i ( flash_power_down_h ), .flash_power_ready_h_i ( flash_power_ready_h ), .flash_alert_o ( flash_alert ), + .flash_obs_o ( fla_obs ), .es_rng_req_o ( es_rng_req ), .es_rng_rsp_i ( es_rng_rsp ), .es_rng_fips_o ( es_rng_fips ), diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv index 976eea6f9522c..66b0fc1c6294b 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv @@ -678,13 +678,10 @@ module chip_earlgrey_cw310 #( logic sck_monitor; // observe interface - logic [8-1:0] fla_obs; - logic [8-1:0] otp_obs; + logic [7:0] fla_obs; + logic [7:0] otp_obs; ast_pkg::ast_obs_ctrl_t obs_ctrl; - assign fla_obs = 8'h00; - assign otp_obs = 8'h00; - // otp power sequence otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq; otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h; @@ -1016,9 +1013,11 @@ module chip_earlgrey_cw310 #( .usbdev_usb_ref_pulse_o ( usb_ref_pulse ), .ast_edn_req_i ( ast_edn_edn_req ), .ast_edn_rsp_o ( ast_edn_edn_rsp ), + .obs_ctrl_i ( obs_ctrl ), .flash_bist_enable_i ( flash_bist_enable ), .flash_power_down_h_i ( 1'b0 ), .flash_power_ready_h_i ( 1'b1 ), + .flash_obs_o ( flash_obs ), .io_clk_byp_req_o ( io_clk_byp_req ), .io_clk_byp_ack_i ( io_clk_byp_ack ), .all_clk_byp_req_o ( all_clk_byp_req ), @@ -1032,6 +1031,7 @@ module chip_earlgrey_cw310 #( .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), .otp_alert_o ( otp_alert ), + .otp_obs_o ( otp_obs ), .sensor_ctrl_ast_alert_req_i ( ast_alert_req ), .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ), .sensor_ctrl_ast_status_i ( ast_pwst.io_pok ), diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv index 6852132cdb3f8..48943f62a8f4b 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv @@ -683,13 +683,10 @@ module chip_earlgrey_nexysvideo #( logic sck_monitor; // observe interface - logic [8-1:0] fla_obs; - logic [8-1:0] otp_obs; + logic [7:0] fla_obs; + logic [7:0] otp_obs; ast_pkg::ast_obs_ctrl_t obs_ctrl; - assign fla_obs = 8'h00; - assign otp_obs = 8'h00; - // otp power sequence otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq; otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h; @@ -1021,9 +1018,11 @@ module chip_earlgrey_nexysvideo #( .usbdev_usb_ref_pulse_o ( usb_ref_pulse ), .ast_edn_req_i ( ast_edn_edn_req ), .ast_edn_rsp_o ( ast_edn_edn_rsp ), + .obs_ctrl_i ( obs_ctrl ), .flash_bist_enable_i ( flash_bist_enable ), .flash_power_down_h_i ( 1'b0 ), .flash_power_ready_h_i ( 1'b1 ), + .flash_obs_o ( flash_obs ), .io_clk_byp_req_o ( io_clk_byp_req ), .io_clk_byp_ack_i ( io_clk_byp_ack ), .all_clk_byp_req_o ( all_clk_byp_req ), @@ -1037,6 +1036,7 @@ module chip_earlgrey_nexysvideo #( .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), .otp_alert_o ( otp_alert ), + .otp_obs_o ( otp_obs ), .sensor_ctrl_ast_alert_req_i ( ast_alert_req ), .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ), .sensor_ctrl_ast_status_i ( ast_pwst.io_pok ), diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 85f24051dd1ef..4496b52cae7a6 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -121,6 +121,7 @@ module top_earlgrey #( input edn_pkg::edn_req_t ast_edn_req_i, output edn_pkg::edn_rsp_t ast_edn_rsp_o, output lc_ctrl_pkg::lc_tx_t ast_lc_dft_en_o, + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, input prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg_i, input prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg_i, input prim_rom_pkg::rom_cfg_t rom_cfg_i, @@ -136,6 +137,7 @@ module top_earlgrey #( input logic flash_power_ready_h_i, inout [1:0] flash_test_mode_a_io, inout flash_test_voltage_h_io, + output logic [7:0] flash_obs_o, output entropy_src_pkg::entropy_src_rng_req_t es_rng_req_o, input entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp_i, output logic es_rng_fips_o, @@ -149,6 +151,7 @@ module top_earlgrey #( input otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h_i, inout otp_ext_voltage_h_io, output ast_pkg::ast_dif_t otp_alert_o, + output logic [7:0] otp_obs_o, input logic [1:0] por_n_i, input ast_pkg::ast_alert_req_t sensor_ctrl_ast_alert_req_i, output ast_pkg::ast_alert_rsp_t sensor_ctrl_ast_alert_rsp_o, @@ -525,6 +528,7 @@ module top_earlgrey #( // define inter-module signals + ast_pkg::ast_obs_ctrl_t ast_obs_ctrl; prim_ram_1p_pkg::ram_1p_cfg_t ast_ram_1p_cfg; prim_ram_2p_pkg::ram_2p_cfg_t ast_ram_2p_cfg; prim_rom_pkg::rom_cfg_t ast_rom_cfg; @@ -745,6 +749,7 @@ module top_earlgrey #( assign edn0_edn_req[2] = ast_edn_req_i; assign ast_edn_rsp_o = edn0_edn_rsp[2]; assign ast_lc_dft_en_o = lc_ctrl_lc_dft_en; + assign ast_obs_ctrl = obs_ctrl_i; assign ast_ram_1p_cfg = ram_1p_cfg_i; assign ast_ram_2p_cfg = ram_2p_cfg_i; assign ast_rom_cfg = rom_cfg_i; @@ -1489,6 +1494,8 @@ module top_earlgrey #( .otbn_otp_key_i(otp_ctrl_otbn_otp_key_req), .otbn_otp_key_o(otp_ctrl_otbn_otp_key_rsp), .otp_hw_cfg_o(otp_ctrl_otp_hw_cfg), + .obs_ctrl_i(ast_obs_ctrl), + .otp_obs_o(otp_obs_o), .core_tl_i(otp_ctrl_core_tl_req), .core_tl_o(otp_ctrl_core_tl_rsp), .prim_tl_i(otp_ctrl_prim_tl_req), @@ -2071,6 +2078,8 @@ module top_earlgrey #( .rma_seed_i(flash_ctrl_rma_seed), .pwrmgr_o(pwrmgr_aon_pwr_flash), .keymgr_o(flash_ctrl_keymgr), + .obs_ctrl_i(ast_obs_ctrl), + .fla_obs_o(flash_obs_o), .core_tl_i(flash_ctrl_core_tl_req), .core_tl_o(flash_ctrl_core_tl_rsp), .prim_tl_i(flash_ctrl_prim_tl_req), diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson index 2682afef480a5..b03c894ca6588 100644 --- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson +++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson @@ -538,7 +538,7 @@ // The activity direction for a port inter-signal is "opposite" of // what the external module actually needs. act: "rcv" - } + }, ] }, ] @@ -652,10 +652,12 @@ 'clkmgr_aon.all_clk_byp_ack' : 'all_clk_byp_ack', 'clkmgr_aon.io_clk_byp_req' : 'io_clk_byp_req', 'clkmgr_aon.io_clk_byp_ack' : 'io_clk_byp_ack', - 'flash_ctrl.flash_alert' : 'flash_alert', - 'flash_ctrl.flash_bist_enable' : 'flash_bist_enable', - 'flash_ctrl.flash_power_down_h' : 'flash_power_down_h', - 'flash_ctrl.flash_power_ready_h' : 'flash_power_ready_h', + 'flash_ctrl.flash_alert' : 'flash_alert', + 'flash_ctrl.flash_bist_enable' : 'flash_bist_enable', + 'flash_ctrl.flash_power_down_h' : 'flash_power_down_h', + 'flash_ctrl.flash_power_ready_h' : 'flash_power_ready_h', + 'flash_ctrl.obs_ctrl' : 'obs_ctrl', + 'flash_ctrl.fla_obs' : 'flash_obs', # 'entropy_src.entropy_src_rng' : '', # 'entropy_src.rng_fips' : '', 'peri.tl_ast' : 'ast_tl', diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl index 0da685d70223d..49376a3781c29 100644 --- a/util/topgen/templates/chiplevel.sv.tpl +++ b/util/topgen/templates/chiplevel.sv.tpl @@ -630,13 +630,10 @@ module chip_${top["name"]}_${target["name"]} ( logic sck_monitor; // observe interface - logic [8-1:0] fla_obs; - logic [8-1:0] otp_obs; + logic [7:0] fla_obs; + logic [7:0] otp_obs; ast_pkg::ast_obs_ctrl_t obs_ctrl; - assign fla_obs = 8'h00; - assign otp_obs = 8'h00; - // otp power sequence otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq; otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h; @@ -1119,13 +1116,16 @@ module chip_${top["name"]}_${target["name"]} ( .adc_rsp_i ( adc_rsp ), .ast_edn_req_i ( ast_edn_edn_req ), .ast_edn_rsp_o ( ast_edn_edn_rsp ), + .obs_ctrl_i ( obs_ctrl ), .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), .otp_alert_o ( otp_alert ), + .otp_obs_o ( otp_obs ), .flash_bist_enable_i ( flash_bist_enable ), .flash_power_down_h_i ( flash_power_down_h ), .flash_power_ready_h_i ( flash_power_ready_h ), .flash_alert_o ( flash_alert ), + .flash_obs_o ( fla_obs ), .es_rng_req_o ( es_rng_req ), .es_rng_rsp_i ( es_rng_rsp ), .es_rng_fips_o ( es_rng_fips ), @@ -1189,6 +1189,11 @@ module chip_${top["name"]}_${target["name"]} ( assign manual_out_io_jsrst_n = 1'b0; assign manual_oe_io_jsrst_n = 1'b0; + % if target["name"] == "cw305": + // TODO: follow-up later and hardwire all ast connects that do not + // exist for this target + assign otp_obs_o = '0; + % endif ////////////////////// // Top-level design // @@ -1263,9 +1268,11 @@ module chip_${top["name"]}_${target["name"]} ( .usbdev_usb_ref_pulse_o ( usb_ref_pulse ), .ast_edn_req_i ( ast_edn_edn_req ), .ast_edn_rsp_o ( ast_edn_edn_rsp ), + .obs_ctrl_i ( obs_ctrl ), .flash_bist_enable_i ( flash_bist_enable ), .flash_power_down_h_i ( 1'b0 ), .flash_power_ready_h_i ( 1'b1 ), + .flash_obs_o ( flash_obs ), .io_clk_byp_req_o ( io_clk_byp_req ), .io_clk_byp_ack_i ( io_clk_byp_ack ), .all_clk_byp_req_o ( all_clk_byp_req ), @@ -1280,6 +1287,7 @@ module chip_${top["name"]}_${target["name"]} ( .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), .otp_alert_o ( otp_alert ), + .otp_obs_o ( otp_obs ), .sensor_ctrl_ast_alert_req_i ( ast_alert_req ), .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ), .sensor_ctrl_ast_status_i ( ast_pwst.io_pok ),