Mininum delay value in LUT SDC

[AndreaMazzan]

Describe the bug
When creating and running the task using the following commands:

create-task my_task template_tasks/fabric_netlist_gen_template
run-task my_task

OpenFPGA generates a Verilog netlist and several SDC files. I am using these files in Fusion Compiler to generate the layout for the netlist, specifically by creating hard macros for every block starting from the CLBs.

While the netlist generation appears to be functioning as expected, I have encountered issues with the SDC files, specifically:

• Minor Issue with set_max_delay for FLEs:
  In the SDC file logical_tile_clb_mode_default__fle_mode_physical__ble6_mode_default__lut6.sdc and logical_tile_clb_mode_clb_.sdc, the path specified for the maximum delay (set_max_delay) is only applied to FLE0, and not the other FLEs (1-9). This seems to be a minor bug, which I have addressed by manually editing the SDC file to apply the same constraints to all FLEs.

• Main Issue:
  In the logical_tile_clb_mode_default__fle_mode_physical__ble6_mode_default__lut6.sdc file, every path has both set_max_delay and set_min_delay commands. However, the values for both delays are identical (261ps in this case), which is problematic because delays are going to vary across different corner cases. Having the same value for both set_max_delay and set_min_delay seems unrealistic, and in fact, leads to hold violation in the best-case corner during the digital flow with Fusion Compiler.
  Note that a set_min_delay is necessary to ensure hold time analysis is performed correctly (or at all). This is because other SDC files (disable_configurable_memory_outputs.sdc, disable_routing_multiplexer_outputs.sdc, and disable_configure_ports.sdc) are used to break combinatorial loops in the netlist. These files effectively interrupt the connections between flip-flops in the CLBs, which means that hold timing analysis is performed only for the paths with a set_min_delay value. I understand that the delay values are derived as an average from the Stratix IV architecture (as clearly explained in the file k6_N10_tileable_40nm.xml). However, my concern is whether it is really important for the delay to be fixed to an exact value. Given the variability that exists across different corners, I believe that the delay should exist within a range of values.
  Is it mandatory for the delay to be an exact value for the LUT? if it isn't, is there a way to estimate a "sensible" value for the minimum delay, which would leave more room for fixing timing violations to Fusion Compiler?
  Thanks!