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Sipeed Tang Mega 138k : SDRAM test failed. #549

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agv100 opened this issue Nov 22, 2023 · 7 comments
Open

Sipeed Tang Mega 138k : SDRAM test failed. #549

agv100 opened this issue Nov 22, 2023 · 7 comments
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new-feature question

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@agv100
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agv100 commented Nov 22, 2023

Hello,
I'm trying to build litex bytestream with DDR3 support.
Previously, on-board DDR3 wa checked with GAO/simple example in sipeed github examples, so, should be operational.

But, when I load litex bitstream, build with --with-ddr3 support, I see, initially ddr3 could be seen:

      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov 21 2023 15:36:50
 BIOS CRC passed (dabbc66a)

 LiteX git sha1: 02277680

--=============== SoC ==================--
CPU:            VexRiscv @ 50MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128.0KiB
SRAM:           8.0KiB
SDRAM:          1.0GiB 32-bit @ 200MT/s (CL-6 CWL-5)
MAIN-RAM:       1.0GiB

--========== Initialization ============--

But it's tests are failed:

litex> sdram_init
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000| delays: -
  m0, b01: |00000000| delays: -
  m0, b02: |00000000| delays: -
  m0, b03: |00000000| delays: -
  best: m0, b00 delays: -
  m1, b00: |00000000| delays: -
  m1, b01: |00000000| delays: -
  m1, b02: |00000000| delays: -
  m1, b03: |00000000| delays: -
  best: m1, b00 delays: -
  m2, b00: |00000000| delays: -
  m2, b01: |00000000| delays: -
  m2, b02: |00000000| delays: -
  m2, b03: |00000000| delays: -
  best: m2, b00 delays: -
  m3, b00: |00000000| delays: -
  m3, b01: |00000000| delays: -
  m3, b02: |00000000| delays: -
  m3, b03: |00000000| delays: -
  best: m3, b00 delays: -
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
  bus errors:  256/256
  addr errors: 0/8192
  data errors: 524288/524288
Memtest KO

And, when I try to access memory manually, it looks not working:

litex> mem_write 0x40000010 0xff 1

litex> mem_read 0x40000010 1
Memory dump:
0x40000010  00

What could be a problem?
@trabucayre
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Hello,
Yes DDR3 is not working and is a WIP.
Sipeed example uses Gowin's DDR3 encrypted IP. But since Gowin doesn't provides real documentation about primitives required to add this support it's more difficult/long to have a working support.
If you need SDRAM it's possible to plug a Mister SDRAM extension into SDRAM dock's connector.

@enjoy-digital
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@agv100: We've planned some to work on this in the following weeks/months. This will probably happen soon but we are working on others features in priority on other features for now.

@enjoy-digital enjoy-digital mentioned this issue Jan 12, 2024
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@enjoy-digital
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While continuing this work, it could be worth checking if a specific LOC constraint is required to get the DDR3 working, as it is for the AE350 SOC:

@agv100
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agv100 commented Aug 22, 2024

Hello,
Just found new commit, adding both sipeed and mister SDRAMs.
So, if I build (without today commit on litedram/litedram/frontend/wishbone.py as it fails on assertion assert wishbone.addressing == "byte" ), with options:



I still can see sdram init failed, but, when I manually read-write upto 4-byte words, it works well:


Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
  bus errors:  128/256
  addr errors: 0/8192
  data errors: 524288/524288
Memtest KO

litex> mem_write 0x40100000 0xabcd

litex> mem_read 0x40100000
Memory dump:
0x40100000  cd ab 00 00                                      ....

litex>



Anything I have to do to get it fully working?

      		
    

  





        


            

            

              
            

        

      


      

            
  

    
  
    
    

  

  



    












      

  
      



  

  @TONYHEGUAGUA





  


    

      

  

    

        
    
    

  


      
          
  
      
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Hello, I'm trying to build litex bytestream with DDR3 support. Previously, on-board DDR3 wa checked with GAO/simple example in sipeed github examples, so, should be operational.


But, when I load litex bitstream, build with --with-ddr3 support, I see, initially ddr3 could be seen:


      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov 21 2023 15:36:50
 BIOS CRC passed (dabbc66a)

 LiteX git sha1: 02277680

--=============== SoC ==================--
CPU:            VexRiscv @ 50MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128.0KiB
SRAM:           8.0KiB
SDRAM:          1.0GiB 32-bit @ 200MT/s (CL-6 CWL-5)
MAIN-RAM:       1.0GiB

--========== Initialization ============--



But it's tests are failed:


litex> sdram_init
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000| delays: -
  m0, b01: |00000000| delays: -
  m0, b02: |00000000| delays: -
  m0, b03: |00000000| delays: -
  best: m0, b00 delays: -
  m1, b00: |00000000| delays: -
  m1, b01: |00000000| delays: -
  m1, b02: |00000000| delays: -
  m1, b03: |00000000| delays: -
  best: m1, b00 delays: -
  m2, b00: |00000000| delays: -
  m2, b01: |00000000| delays: -
  m2, b02: |00000000| delays: -
  m2, b03: |00000000| delays: -
  best: m2, b00 delays: -
  m3, b00: |00000000| delays: -
  m3, b01: |00000000| delays: -
  m3, b02: |00000000| delays: -
  m3, b03: |00000000| delays: -
  best: m3, b00 delays: -
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
  bus errors:  256/256
  addr errors: 0/8192
  data errors: 524288/524288
Memtest KO



And, when I try to access memory manually, it looks not working:


litex> mem_write 0x40000010 0xff 1

litex> mem_read 0x40000010 1
Memory dump:
0x40000010  00   



What could be a problem?




hello ,i recently try to run litex on sipeed tang mega 138k pro ,  i'm now facing the exact same problem as you do . Have you figured out how to solve this problem yet ?


github photo1

github photo2

      		
    

  





        


            

            

              
            

        

      


      

            
  

    
  
    
    

  

  



    












      

  
      



  

  @quanweizhang





  


    

      

  

    

        
    
    

  


      
          
  
      
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您好，请问你们怎么解决这个问题的呢？

      		
    

  





        


            

            

              
            

        

      


      

            
  

    
  
    
    

  

  



    












      

  
      



  

  @2jack5657





  


    

      

  

    

        
    
    

  


      
          
  
      
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Hello, 你好 Yes DDR3 is not working and is a WIP.是的，DDR3 不工作，是一个 WIP。 Sipeed example uses Gowin's DDR3 encrypted IP. But since Gowin doesn't provides real documentation about primitives required to add this support it's more difficult/long to have a working support.Sipeed 示例使用 Gowin 的 DDR3 加密 IP。但是由于 Gowin 没有提供有关添加此支持所需的原始变量的真实文档，因此拥有工作支持更加困难/漫长。 If you need SDRAM it's possible to plug a Mister SDRAM extension into SDRAM dock's connector.如果您需要 SDRAM，可以将 Mister SDRAM 扩展插入 SDRAM 扩展坞的连接器。




I recently bought sipeed SDRAM Plugin,but when i plug in ,my Soc seems not to reconize the RAM storage correctly. The mod is 32MiB*2 ,but it only can be recognized 32MiB,and sdram_init is also fail. I use Tang mega 138k, the platform and target profile are changed from Tang mega 138k pro.

屏幕截图 2024-10-30 164425

屏幕截图 2024-10-30 164459

      		
    

  





        


            

            

              
            

        

      


      

            
  

    
  
    
    

  

  



    
















  
  

    

      

  





  




  
  

              

  
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      6 participants
    

    

        
          @enjoy-digital 
        
          @trabucayre 
        
          @agv100 
        
          @quanweizhang 
        
          @2jack5657 
        
          @TONYHEGUAGUA