From 6858b197ce5ed05bf7807c8d7fed9ba58339e8a5 Mon Sep 17 00:00:00 2001 From: lcgamboa Date: Sat, 16 Nov 2024 19:25:27 -0300 Subject: [PATCH] fix: Fix BluePill board PWM outputs --- VERSION | 2 +- src/boards/board_Blue_Pill.cc | 46 ++++++++++++--------------------- src/boards/board_C3_DevKitC.cc | 1 + src/boards/board_DevKitC.cc | 1 + src/boards/board_STM32_H103.cc | 42 ++++++++++-------------------- src/boards/bsim_qemu.cc | 2 +- src/devices/bitbang_pwm.cc | 5 ++++ src/devices/bitbang_pwm.h | 2 ++ src/parts/virtual_VCD_Dump_an.h | 1 - 9 files changed, 41 insertions(+), 61 deletions(-) diff --git a/VERSION b/VERSION index ce8ea0c3..49b0a4a7 100644 --- a/VERSION +++ b/VERSION @@ -2,5 +2,5 @@ PACKAGE=picsimlab MAINVER=0 MINORVER=9 VERSION=0.9.2 -DATE=241005 +DATE=241116 VERSION_STABLE=0.9.2 diff --git a/src/boards/board_Blue_Pill.cc b/src/boards/board_Blue_Pill.cc index efbd2fb7..1e865751 100644 --- a/src/boards/board_Blue_Pill.cc +++ b/src/boards/board_Blue_Pill.cc @@ -944,7 +944,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_uart[1].tx_pin = iopin(A, 2); master_uart[1].rx_pin = iopin(A, 3); master_uart[1].ctrl_on = 1; - break; } // tim2 ch3 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2); @@ -959,7 +958,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_uart[1].tx_pin = iopin(A, 2); master_uart[1].rx_pin = iopin(A, 3); master_uart[1].ctrl_on = 1; - break; } // tim2 ch4 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2); @@ -987,7 +985,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_spi[0].copi_pin = iopin(A, 7); master_spi[0].cipo_pin = iopin(A, 6); master_spi[0].ctrl_on = 1; - break; } // tim3 ch1 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3); @@ -1003,13 +1000,11 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_spi[0].copi_pin = iopin(A, 7); master_spi[0].cipo_pin = iopin(A, 6); master_spi[0].ctrl_on = 1; - break; } // tim1_ch1n (alt) afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 0, iopin(A, 7)); - break; } // tim3 ch2 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3); @@ -1031,7 +1026,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_uart[0].tx_pin = iopin(A, 9); master_uart[0].rx_pin = iopin(A, 10); master_uart[0].ctrl_on = 1; - break; } // tim1 ch2 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1); @@ -1046,7 +1040,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_uart[0].tx_pin = iopin(A, 9); master_uart[0].rx_pin = iopin(A, 10); master_uart[0].ctrl_on = 1; - break; } // tim1 ch3 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1); @@ -1078,7 +1071,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 1, iopin(B, 0)); - break; } // tim3_ch3 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3); @@ -1091,14 +1083,12 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 2, iopin(B, 1)); - break; } // tim3_ch4 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3); if (*afio == 0) { bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 3, iopin(B, 1)); } - break; case 2: break; @@ -1107,15 +1097,15 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 1, iopin(B, 3)); - break; } + break; case 4: // tim3_ch1n (alt) afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3); if (*afio == 2) { bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 0, iopin(B, 4)); - break; } + break; case 5: // spi1 (alt) afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI1); @@ -1124,13 +1114,11 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_spi[0].copi_pin = iopin(B, 5); master_spi[0].cipo_pin = iopin(B, 4); master_spi[0].ctrl_on = 1; - break; } // tim3_ch2n (alt) afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3); if (*afio == 2) { bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 1, iopin(B, 5)); - break; } break; case 6: @@ -1140,7 +1128,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_uart[0].tx_pin = iopin(B, 6); master_uart[0].rx_pin = iopin(B, 7); master_uart[0].ctrl_on = 1; - break; } // i2c afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1); @@ -1148,7 +1135,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_i2c[0].scl_pin = iopin(B, 6); master_i2c[0].sda_pin = iopin(B, 7); master_i2c[0].ctrl_on = 1; - break; } // tim4 ch1 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4); @@ -1163,7 +1149,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_uart[0].tx_pin = iopin(B, 6); master_uart[0].rx_pin = iopin(B, 7); master_uart[0].ctrl_on = 1; - break; } // i2c0 afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1); @@ -1171,7 +1156,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_i2c[0].scl_pin = iopin(B, 6); master_i2c[0].sda_pin = iopin(B, 7); master_i2c[0].ctrl_on = 1; - break; } // tim4 ch2 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4); @@ -1186,13 +1170,13 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_i2c[0].scl_pin = iopin(B, 8); master_i2c[0].sda_pin = iopin(B, 9); master_i2c[0].ctrl_on = 1; - break; } // tim4 ch3 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4); if (*afio == 0) { bitbang_pwm_set_pin(&pwm_out, (3 << 2) + 2, iopin(B, 8)); } + break; case 9: // i2c0 (alt) afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1); @@ -1200,7 +1184,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_i2c[0].scl_pin = iopin(B, 8); master_i2c[0].sda_pin = iopin(B, 9); master_i2c[0].ctrl_on = 1; - break; } // tim4 ch4 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4); @@ -1213,7 +1196,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 2, iopin(B, 10)); - break; } /* // uart3 @@ -1232,7 +1214,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_i2c[1].scl_pin = iopin(B, 10); master_i2c[1].sda_pin = iopin(B, 11); master_i2c[1].ctrl_on = 1; - break; } break; case 11: @@ -1240,7 +1221,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 3, iopin(B, 10)); - break; } /* // uart3 @@ -1259,7 +1239,6 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { master_i2c[1].scl_pin = iopin(B, 10); master_i2c[1].sda_pin = iopin(B, 11); master_i2c[1].ctrl_on = 1; - break; } break; case 12: @@ -1303,17 +1282,24 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) { int duty = (cfg & 0xFFFF0) >> 4; int chn = (cfg & 0x000C) >> 2; int timer = cfg & 0x0003; - // printf("TIM %i chn %i dut set to %i\n", timer + - // 1, chn + 1, duty); + // printf("TIM %i chn %i dut set to %i\n", timer + 1, chn + 1, duty); bitbang_pwm_set_duty(&pwm_out, (timer << 2) + chn, duty); } else if ((cfg & 0xF00000) == 0xD00000) { // timer frequency int freq = (cfg & 0xFFFFC) >> 2; int timer = cfg & 0x0003; // printf("TIM %i freq set to %i\n", timer + 1, freq); - bitbang_pwm_set_freq(&pwm_out, timer + 0, freq); - bitbang_pwm_set_freq(&pwm_out, timer + 1, freq); - bitbang_pwm_set_freq(&pwm_out, timer + 2, freq); - bitbang_pwm_set_freq(&pwm_out, timer + 3, freq); + bitbang_pwm_set_freq(&pwm_out, (timer << 2) + 0, freq); + bitbang_pwm_set_freq(&pwm_out, (timer << 2) + 1, freq); + bitbang_pwm_set_freq(&pwm_out, (timer << 2) + 2, freq); + bitbang_pwm_set_freq(&pwm_out, (timer << 2) + 3, freq); + } else if ((cfg & 0xF00000) == 0xE00000) { // timer enable output + int ccer = (cfg & 0xFFFFC) >> 2; + int timer = cfg & 0x0003; + // printf("TIM %i ccer 0x%04X\n", timer + 1, ccer); + bitbang_pwm_set_enable(&pwm_out, (timer << 2) + 0, (ccer & 0x0005) > 0); + bitbang_pwm_set_enable(&pwm_out, (timer << 2) + 1, (ccer & 0x0050) > 0); + bitbang_pwm_set_enable(&pwm_out, (timer << 2) + 2, (ccer & 0x0500) > 0); + bitbang_pwm_set_enable(&pwm_out, (timer << 2) + 3, (ccer & 0x5000) > 0); } } diff --git a/src/boards/board_C3_DevKitC.cc b/src/boards/board_C3_DevKitC.cc index b95f0f56..c466e03a 100644 --- a/src/boards/board_C3_DevKitC.cc +++ b/src/boards/board_C3_DevKitC.cc @@ -950,6 +950,7 @@ void cboard_C3_DevKitC::PinsExtraConfig(int cfg) { case 50: // ledc_ls_sig_out5 // printf("LEDC channel %i in GPIO %i\n", function - 45, gpio); bitbang_pwm_set_pin(&pwm_out, function - 45, io2pin(gpio)); + bitbang_pwm_set_enable(&pwm_out, function - 45, 1); break; case 51: // rmt_sig_out0 case 52: // rmt_sig_out1 diff --git a/src/boards/board_DevKitC.cc b/src/boards/board_DevKitC.cc index ee3a55cf..bbad0756 100644 --- a/src/boards/board_DevKitC.cc +++ b/src/boards/board_DevKitC.cc @@ -1010,6 +1010,7 @@ void cboard_DevKitC::PinsExtraConfig(int cfg) { case 86: // ledc_ls_sig_out7 // printf("LEDC channel %i in GPIO %i\n",function - 71, gpio); bitbang_pwm_set_pin(&pwm_out, function - 71, io2pin(gpio)); + bitbang_pwm_set_enable(&pwm_out, function - 71, 1); break; case 87: // rmt_sig_out0 // case 88: // rmt_sig_out1 //FIXME only channel 0 enabled diff --git a/src/boards/board_STM32_H103.cc b/src/boards/board_STM32_H103.cc index daf076f4..29711706 100644 --- a/src/boards/board_STM32_H103.cc +++ b/src/boards/board_STM32_H103.cc @@ -1088,7 +1088,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_uart[1].tx_pin = iopin(A, 2); master_uart[1].rx_pin = iopin(A, 3); master_uart[1].ctrl_on = 1; - break; } // tim2 // ch3 @@ -1104,7 +1103,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_uart[1].tx_pin = iopin(A, 2); master_uart[1].rx_pin = iopin(A, 3); master_uart[1].ctrl_on = 1; - break; } // tim2 // ch4 @@ -1133,7 +1131,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_spi[0].copi_pin = iopin(A, 7); master_spi[0].cipo_pin = iopin(A, 6); master_spi[0].ctrl_on = 1; - break; } // tim3 // ch1 @@ -1150,14 +1147,12 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_spi[0].copi_pin = iopin(A, 7); master_spi[0].cipo_pin = iopin(A, 6); master_spi[0].ctrl_on = 1; - break; } // tim1_ch1n // (alt) afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 0, iopin(A, 7)); - break; } // tim3 // ch2 @@ -1181,7 +1176,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_uart[0].tx_pin = iopin(A, 9); master_uart[0].rx_pin = iopin(A, 10); master_uart[0].ctrl_on = 1; - break; } // tim1 // ch2 @@ -1197,7 +1191,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_uart[0].tx_pin = iopin(A, 9); master_uart[0].rx_pin = iopin(A, 10); master_uart[0].ctrl_on = 1; - break; } // tim1 // ch3 @@ -1232,7 +1225,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 1, iopin(B, 0)); - break; } // tim3_ch3 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3); @@ -1246,14 +1238,12 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 2, iopin(B, 1)); - break; } // tim3_ch4 afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3); if (*afio == 0) { bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 3, iopin(B, 1)); } - break; case 2: break; @@ -1263,16 +1253,16 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 1, iopin(B, 3)); - break; } + break; case 4: // tim3_ch1n // (alt) afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3); if (*afio == 2) { bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 0, iopin(B, 4)); - break; } + break; case 5: // spi1 // (alt) @@ -1282,14 +1272,12 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_spi[0].copi_pin = iopin(B, 5); master_spi[0].cipo_pin = iopin(B, 4); master_spi[0].ctrl_on = 1; - break; } // tim3_ch2n // (alt) afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3); if (*afio == 2) { bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 1, iopin(B, 5)); - break; } break; case 6: @@ -1300,7 +1288,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_uart[0].tx_pin = iopin(B, 6); master_uart[0].rx_pin = iopin(B, 7); master_uart[0].ctrl_on = 1; - break; } // i2c afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1); @@ -1308,7 +1295,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_i2c[0].scl_pin = iopin(B, 6); master_i2c[0].sda_pin = iopin(B, 7); master_i2c[0].ctrl_on = 1; - break; } // tim4 // ch1 @@ -1325,7 +1311,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_uart[0].tx_pin = iopin(B, 6); master_uart[0].rx_pin = iopin(B, 7); master_uart[0].ctrl_on = 1; - break; } // i2c0 afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1); @@ -1333,7 +1318,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_i2c[0].scl_pin = iopin(B, 6); master_i2c[0].sda_pin = iopin(B, 7); master_i2c[0].ctrl_on = 1; - break; } // tim4 // ch2 @@ -1350,7 +1334,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_i2c[0].scl_pin = iopin(B, 8); master_i2c[0].sda_pin = iopin(B, 9); master_i2c[0].ctrl_on = 1; - break; } // tim4 // ch3 @@ -1366,7 +1349,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_i2c[0].scl_pin = iopin(B, 8); master_i2c[0].sda_pin = iopin(B, 9); master_i2c[0].ctrl_on = 1; - break; } // tim4 // ch4 @@ -1381,7 +1363,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 2, iopin(B, 10)); - break; } /* // uart3 @@ -1412,7 +1393,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_i2c[1].scl_pin = iopin(B, 10); master_i2c[1].sda_pin = iopin(B, 11); master_i2c[1].ctrl_on = 1; - break; } break; case 11: @@ -1421,7 +1401,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2); if (*afio == 1) { bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 3, iopin(B, 10)); - break; } /* // uart3 @@ -1452,7 +1431,6 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { master_i2c[1].scl_pin = iopin(B, 10); master_i2c[1].sda_pin = iopin(B, 11); master_i2c[1].ctrl_on = 1; - break; } break; case 12: @@ -1507,10 +1485,18 @@ void cboard_STM32_H103::PinsExtraConfig(int cfg) { int freq = (cfg & 0xFFFFC) >> 2; int timer = cfg & 0x0003; // printf("TIM %i freq set to %i\n", timer + 1, freq); - bitbang_pwm_set_freq(&pwm_out, timer + 0, freq); - bitbang_pwm_set_freq(&pwm_out, timer + 1, freq); - bitbang_pwm_set_freq(&pwm_out, timer + 2, freq); - bitbang_pwm_set_freq(&pwm_out, timer + 3, freq); + bitbang_pwm_set_freq(&pwm_out, (timer << 2) + 0, freq); + bitbang_pwm_set_freq(&pwm_out, (timer << 2) + 1, freq); + bitbang_pwm_set_freq(&pwm_out, (timer << 2) + 2, freq); + bitbang_pwm_set_freq(&pwm_out, (timer << 2) + 3, freq); + } else if ((cfg & 0xF00000) == 0xE00000) { // timer enable output + int ccer = (cfg & 0xFFFFC) >> 2; + int timer = cfg & 0x0003; + // printf("TIM %i ccer 0x%04X\n", timer + 1, ccer); + bitbang_pwm_set_enable(&pwm_out, (timer << 2) + 0, (ccer & 0x0005) > 0); + bitbang_pwm_set_enable(&pwm_out, (timer << 2) + 1, (ccer & 0x0050) > 0); + bitbang_pwm_set_enable(&pwm_out, (timer << 2) + 2, (ccer & 0x0500) > 0); + bitbang_pwm_set_enable(&pwm_out, (timer << 2) + 3, (ccer & 0x5000) > 0); } } diff --git a/src/boards/bsim_qemu.cc b/src/boards/bsim_qemu.cc index ec590f2c..bafe93d6 100644 --- a/src/boards/bsim_qemu.cc +++ b/src/boards/bsim_qemu.cc @@ -1251,7 +1251,7 @@ void bsim_qemu::MStep(void) { } } for (int i = 0; i < pwm_out.channels_count; i++) { - if (pwm_out.channels[i].pin) { + if (pwm_out.channels[i].pin && pwm_out.channels[i].enabled) { pins[pwm_out.channels[i].pin - 1].dir = PD_OUT; pins[pwm_out.channels[i].pin - 1].value = pwm_out.channels[i].out; } diff --git a/src/devices/bitbang_pwm.cc b/src/devices/bitbang_pwm.cc index 981fd163..84380cf8 100644 --- a/src/devices/bitbang_pwm.cc +++ b/src/devices/bitbang_pwm.cc @@ -42,6 +42,7 @@ void bitbang_pwm_rst(bitbang_pwm_t* pwm) { pwm->channels[i].duty = 0; pwm->channels[i].out = 0; pwm->channels[i].freq = 0; + pwm->channels[i].enabled = 0; } } @@ -128,4 +129,8 @@ void bitbang_pwm_set_freq(bitbang_pwm_t* pwm, const unsigned char channel, unsig pwm->pboard->TimerChange_us(pwm->channels[channel].TimerID, 10000.0 / (freq * pwm->channels[channel].res)); pwm->channels[channel].freq = freq; } +} + +void bitbang_pwm_set_enable(bitbang_pwm_t* pwm, const unsigned char channel, unsigned char enable) { + pwm->channels[channel].enabled = enable; } \ No newline at end of file diff --git a/src/devices/bitbang_pwm.h b/src/devices/bitbang_pwm.h index 8a82ca84..5220614f 100644 --- a/src/devices/bitbang_pwm.h +++ b/src/devices/bitbang_pwm.h @@ -36,6 +36,7 @@ typedef struct { unsigned char pin; unsigned char out; unsigned char duty; + unsigned char enabled; unsigned int freq; unsigned int res; } channel_pwm_t; @@ -53,5 +54,6 @@ void bitbang_pwm_set_duty(bitbang_pwm_t* pwm, const unsigned char channel, const void bitbang_pwm_set_duty_f(bitbang_pwm_t* pwm, const unsigned char channel, const float duty); void bitbang_pwm_set_pin(bitbang_pwm_t* pwm, const unsigned char channel, const char pin); void bitbang_pwm_set_freq(bitbang_pwm_t* pwm, const unsigned char channel, unsigned int freq); +void bitbang_pwm_set_enable(bitbang_pwm_t* pwm, const unsigned char channel, unsigned char enable); #endif // BITBANG_PWM \ No newline at end of file diff --git a/src/parts/virtual_VCD_Dump_an.h b/src/parts/virtual_VCD_Dump_an.h index 5c3a7267..0f3d432b 100644 --- a/src/parts/virtual_VCD_Dump_an.h +++ b/src/parts/virtual_VCD_Dump_an.h @@ -42,7 +42,6 @@ class cpart_VCD_Dump_an : public part { void PostProcess(void) override; std::string GetPictureFileName(void) override { return "VCD Dump/part.svg"; }; std::string GetMapFile(void) override { return "VCD Dump/part.map"; }; - std::string GetPropertiesWindowFile(void) override { return "VCD Dump/part.lxrad"; }; void OnMouseButtonPress(unsigned int inputId, unsigned int button, unsigned int x, unsigned int y, unsigned int state) override; void ConfigurePropertiesWindow(void) override;