From 2b6341e2ea8b97446b9d94780c619020ab286757 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Fri, 22 Nov 2024 16:10:54 +0200 Subject: [PATCH] platform: intel: ace: remove all unnecessary clk.h definitions Strip all unnecessary definitions from Intel ACE clk.h platform code. Only expose the main DSP clock via the SOF clk.h layer, as required by cpu-clk-manager.c. Signed-off-by: Kai Vehmanen --- src/platform/ace30/include/platform/lib/clk.h | 4 ---- src/platform/intel/ace/include/ace/lib/clk.h | 16 +--------------- src/platform/intel/ace/platform.c | 3 ++- .../lunarlake/include/platform/lib/clk.h | 4 ---- .../meteorlake/include/platform/lib/clk.h | 4 ---- 5 files changed, 3 insertions(+), 28 deletions(-) diff --git a/src/platform/ace30/include/platform/lib/clk.h b/src/platform/ace30/include/platform/lib/clk.h index 85a515f1d559..efba9f8129a0 100644 --- a/src/platform/ace30/include/platform/lib/clk.h +++ b/src/platform/ace30/include/platform/lib/clk.h @@ -26,12 +26,8 @@ #define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX -#define SSP_DEFAULT_IDX 1 - #define NUM_CPU_FREQ 3 -#define NUM_SSP_FREQ 3 - #define PRIMARY_CORE_BASE_CPS_USAGE 20000 #define SECONDARY_CORE_BASE_CPS_USAGE 10000 diff --git a/src/platform/intel/ace/include/ace/lib/clk.h b/src/platform/intel/ace/include/ace/lib/clk.h index 2a4fdfe1495d..b9c7fd0aec8f 100644 --- a/src/platform/intel/ace/include/ace/lib/clk.h +++ b/src/platform/intel/ace/include/ace/lib/clk.h @@ -20,30 +20,16 @@ #include #include -#include -#include -#include struct sof; -/** \brief Core(s) settings, up to CONFIG_CORE_COUNT */ -#define CLK_CPU(x) (x) - -/** \brief SSP clock r-t settings are after the core(s) settings */ -#define CLK_SSP CONFIG_CORE_COUNT - -/* SSP clock run-time data is the last one, so total number is ssp idx +1 */ - /** \brief Total number of clocks */ -#define NUM_CLOCKS (CLK_SSP + 1) +#define NUM_CLOCKS CONFIG_CORE_COUNT extern const struct freq_table *cpu_freq; void platform_clock_init(struct sof *sof); -void platform_clock_on_waiti(void); -void platform_clock_on_wakeup(void); - #endif /* __ACE_LIB_CLK_H__ */ #else diff --git a/src/platform/intel/ace/platform.c b/src/platform/intel/ace/platform.c index 50453bb637b4..9e88861d9a97 100644 --- a/src/platform/intel/ace/platform.c +++ b/src/platform/intel/ace/platform.c @@ -103,7 +103,8 @@ int platform_init(struct sof *sof) scheduler_init_edf(); /* init low latency timer domain and scheduler. Any failure is fatal */ - sof->platform_timer_domain = zephyr_domain_init(PLATFORM_DEFAULT_CLOCK); + /* clk is ignored on Zephyr so pass 0 */ + sof->platform_timer_domain = zephyr_domain_init(0); ret = scheduler_init_ll(sof->platform_timer_domain); if (ret < 0) return ret; diff --git a/src/platform/lunarlake/include/platform/lib/clk.h b/src/platform/lunarlake/include/platform/lib/clk.h index 16311109c727..29b0a6c81686 100644 --- a/src/platform/lunarlake/include/platform/lib/clk.h +++ b/src/platform/lunarlake/include/platform/lib/clk.h @@ -24,12 +24,8 @@ #define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX -#define SSP_DEFAULT_IDX 1 - #define NUM_CPU_FREQ 2 -#define NUM_SSP_FREQ 3 - #define PRIMARY_CORE_BASE_CPS_USAGE 20000 #define SECONDARY_CORE_BASE_CPS_USAGE 10000 diff --git a/src/platform/meteorlake/include/platform/lib/clk.h b/src/platform/meteorlake/include/platform/lib/clk.h index e82c3e47fc61..744ad4b82e79 100644 --- a/src/platform/meteorlake/include/platform/lib/clk.h +++ b/src/platform/meteorlake/include/platform/lib/clk.h @@ -24,12 +24,8 @@ #define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX -#define SSP_DEFAULT_IDX 1 - #define NUM_CPU_FREQ 2 -#define NUM_SSP_FREQ 3 - #define PRIMARY_CORE_BASE_CPS_USAGE 20000 #define SECONDARY_CORE_BASE_CPS_USAGE 10000