README.md

Simply5 is in under construction

This is RISC-V based 64-bit core.

Roadmap

Every modules will be verified by UVM tests.

• ALU
• Instruction Decoder
• Control Unit
• Accumulator
• Core (integration all modules into single core)
• Plug the core into a SoC (haven't decided yet)
• Run it on QEMU
• Run it on a FPGA