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thumbulator.c
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thumbulator.c
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#include <stdio.h>
#include <fcntl.h>
#include <stdlib.h>
#include <string.h>
#include <libelf.h>
#include <gelf.h>
typedef struct {
unsigned long offset;
unsigned long size;
unsigned short *data;
} memory_region_t;
int n_memory_regions;
memory_region_t *memory_regions;
unsigned int read32 ( unsigned int );
unsigned int read_register ( unsigned int );
#define DBUGFETCH 0
#define DBUGRAM 0
#define DBUGRAMW 0
#define DBUGREG 0
#define DBUG 0
#define DISS 1
#define ROMADDMASK 0xFFFFF
#define RAMADDMASK 0xFFFFF
#define ROMSIZE (ROMADDMASK+1)
#define RAMSIZE (RAMADDMASK+1)
// unsigned short rom[ROMSIZE>>1];
// unsigned short ram[RAMSIZE>>1];
#define CPSR_N (1<<31)
#define CPSR_Z (1<<30)
#define CPSR_C (1<<29)
#define CPSR_V (1<<28)
#define CPSR_Q (1<<27)
unsigned int vcdcount;
unsigned int output_vcd;
FILE *fpvcd;
int input_elf = 0;
unsigned long elf_start_address = 0;
unsigned int systick_ctrl;
unsigned int systick_reload;
unsigned int systick_count;
unsigned int systick_calibrate;
unsigned int halfadd;
unsigned int cpsr;
unsigned int handler_mode;
unsigned int reg_norm[16]; //normal execution mode, do not have a thread mode
unsigned long instructions;
unsigned long fetches;
unsigned long reads;
unsigned long writes;
unsigned long systick_ints;
void alloc_memory_regions(int n)
{
n_memory_regions = n;
memory_regions = malloc(sizeof(memory_region_t)*n);
}
void set_memory_region(int i, unsigned long offset, unsigned long size)
{
memory_regions[i].offset = offset;
memory_regions[i].size = size;
memory_regions[i].data = malloc(sizeof(short)*(size>>1));
}
unsigned read_from_memory16(unsigned int addr)
{
for(int i = 0; i < n_memory_regions; ++i)
{
if(addr >= memory_regions[i].offset && addr < memory_regions[i].offset + memory_regions[i].size)
{
return memory_regions[i].data[(addr-memory_regions[i].offset) >> 1];
}
}
fprintf(stderr, "Memory region not mapped (0x%08X). ABORT\n", addr);
exit(1);
}
void write_to_memory16(unsigned int addr, unsigned short data)
{
for(int i = 0; i < n_memory_regions; ++i)
{
if(addr >= memory_regions[i].offset && addr < memory_regions[i].offset + memory_regions[i].size)
{
memory_regions[i].data[(addr-memory_regions[i].offset)>>1] = data;
return;
}
}
fprintf(stderr, "Memory region not mapped (0x%08X). ABORT\n", addr);
exit(1);
}
void reset_memory()
{
for(int i = 0; i < n_memory_regions; ++i)
{
memset(memory_regions[i].data, 0, memory_regions[i].size);
}
}
//-------------------------------------------------------------------
void dump_counters ( void )
{
printf("\n\n");
printf("instructions %lu\n",instructions);
printf("fetches %lu\n",fetches);
printf("reads %lu\n",reads);
printf("writes %lu\n",writes);
printf("memcycles %lu\n",fetches+reads+writes);
printf("systick_ints %lu\n",systick_ints);
}
//-------------------------------------------------------------------
unsigned int fetch16 ( unsigned int addr )
{
unsigned int data;
fetches++;
if(DBUGFETCH) fprintf(stderr,"fetch16(0x%08X)=",addr);
if(DBUG) fprintf(stderr,"fetch16(0x%08X)=",addr);
data = read_from_memory16(addr);
if(DBUGFETCH) fprintf(stderr,"0x%04X\n",data);
if(DBUG) fprintf(stderr,"0x%04X\n",data);
return(data);
}
//-------------------------------------------------------------------
unsigned int fetch32 ( unsigned int addr )
{
unsigned int data;
if(DBUGFETCH) fprintf(stderr,"fetch32(0x%08X)=",addr);
if(DBUG) fprintf(stderr,"fetch32(0x%08X)=",addr);
data=read32(addr);
if(DBUGFETCH) fprintf(stderr,"0x%08X\n",data);
if(DBUG) fprintf(stderr,"0x%08X\n",data);
return(data);
}
//-------------------------------------------------------------------
void write16 ( unsigned int addr, unsigned int data )
{
writes++;
if(DBUG) fprintf(stderr,"write16(0x%08X,0x%04X)\n",addr,data);
write_to_memory16(addr, data);
}
//-------------------------------------------------------------------
void write32 ( unsigned int addr, unsigned int data )
{
if(DBUG) fprintf(stderr,"write32(0x%08X,0x%08X)\n",addr,data);
switch(addr&0xF0000000)
{
case 0xF0000000: //halt
dump_counters();
exit(0);
case 0xE0000000: //periph
switch(addr)
{
case 0xE0000000:
if(DISS) printf("uart: [");
printf("%c",data&0xFF);
if(DISS) printf("]\n");
fflush(stdout);
break;
case 0xE000E010:
{
unsigned int old;
old=systick_ctrl;
systick_ctrl = data&0x00010007;
if(((old&1)==0)&&(systick_ctrl&1))
{
//timer started, load count
systick_count=systick_reload;
}
break;
}
case 0xE000E014:
{
systick_reload=data&0x00FFFFFF;
break;
}
case 0xE000E018:
{
systick_count=data&0x00FFFFFF;
break;
}
case 0xE000E01C:
{
systick_calibrate=data&0x00FFFFFF;
break;
}
}
return;
case 0xD0000000: //debug
switch(addr&0xFF)
{
case 0x00:
{
fprintf(stderr,"[0x%08X][0x%08X] 0x%08X\n",read_register(14),addr,data);
return;
}
case 0x10:
{
printf("0x%08X ",data);
return;
}
case 0x20:
{
printf("0x%08X\n",data);
return;
}
}
}
if(DBUGRAMW) fprintf(stderr,"write32(0x%08X,0x%08X)\n",addr,data);
write16(addr+0,(data>> 0)&0xFFFF);
write16(addr+2,(data>>16)&0xFFFF);
}
//-----------------------------------------------------------------
unsigned int read16 ( unsigned int addr )
{
unsigned int data;
reads++;
if(DBUG) fprintf(stderr,"read16(0x%08X)=",addr);
return read_from_memory16(addr);
}
//-------------------------------------------------------------------
unsigned int read32 ( unsigned int addr )
{
unsigned int data;
if(DBUG) fprintf(stderr,"read32(0x%08X)=",addr);
switch(addr&0xF0000000)
{
case 0xE0000000:
{
switch(addr)
{
case 0xE000E010:
{
data = systick_ctrl;
systick_ctrl&=(~0x00010000);
return(data);
}
case 0xE000E014:
{
data=systick_reload;
return(data);
}
case 0xE000E018:
{
data=systick_count;
return(data);
}
case 0xE000E01C:
{
data=systick_calibrate;
return(data);
}
}
}
}
data = read16(addr+0);
data|=((unsigned int)read16(addr+2))<<16;
return data;
}
//-------------------------------------------------------------------
unsigned int read_register ( unsigned int reg )
{
unsigned int data;
reg&=0xF;
if(DBUG) fprintf(stderr,"read_register(%u)=",reg);
if(DBUGREG) fprintf(stderr,"read_register(%u)=",reg);
data=reg_norm[reg];
if(reg==15) data&=~1;
if(DBUG) fprintf(stderr,"0x%08X\n",data);
if(DBUGREG) fprintf(stderr,"0x%08X\n",data);
return(data);
}
//-------------------------------------------------------------------
void write_register ( unsigned int reg, unsigned int data )
{
reg&=0xF;
if(DBUG) fprintf(stderr,"write_register(%u,0x%08X)\n",reg,data);
if(DBUGREG) fprintf(stderr,"write_register(%u,0x%08X)\n",reg,data);
if(reg==15) data&=~1;
reg_norm[reg]=data;
if(output_vcd)
{
unsigned int vv;
fprintf(fpvcd,"b");
for(vv=0x80000000;vv;vv>>=1)
{
if(vv&data) fprintf(fpvcd,"1"); else fprintf(fpvcd,"0");
}
fprintf(fpvcd," r%u\n",reg);
}
}
//-------------------------------------------------------------------
void do_zflag ( unsigned int x )
{
if(x==0) cpsr|=CPSR_Z; else cpsr&=~CPSR_Z;
}
//-------------------------------------------------------------------
void do_nflag ( unsigned int x )
{
if(x&0x80000000) cpsr|=CPSR_N; else cpsr&=~CPSR_N;
}
//-------------------------------------------------------------------
void do_cflag ( unsigned int a, unsigned int b, unsigned int c )
{
unsigned int rc;
cpsr&=~CPSR_C;
rc=(a&0x7FFFFFFF)+(b&0x7FFFFFFF)+c; //carry in
rc = (rc>>31)+(a>>31)+(b>>31); //carry out
if(rc&2) cpsr|=CPSR_C;
}
//-------------------------------------------------------------------
void do_vflag ( unsigned int a, unsigned int b, unsigned int c )
{
unsigned int rc;
unsigned int rd;
cpsr&=~CPSR_V;
rc=(a&0x7FFFFFFF)+(b&0x7FFFFFFF)+c; //carry in
rc>>=31; //carry in in lsbit
rd=(rc&1)+((a>>31)&1)+((b>>31)&1); //carry out
rd>>=1; //carry out in lsbit
rc=(rc^rd)&1; //if carry in != carry out then signed overflow
if(rc) cpsr|=CPSR_V;
}
//-------------------------------------------------------------------
void do_cflag_bit ( unsigned int x )
{
if(x) cpsr|=CPSR_C; else cpsr&=~CPSR_C;
}
//-------------------------------------------------------------------
void do_vflag_bit ( unsigned int x )
{
if(x) cpsr|=CPSR_V; else cpsr&=~CPSR_V;
}
//-------------------------------------------------------------------
//-------------------------------------------------------------------
//-------------------------------------------------------------------
int execute ( void )
{
unsigned int pc;
unsigned int sp;
unsigned int inst;
unsigned int ra,rb,rc;
unsigned int rm,rd,rn,rs;
unsigned int op;
pc=read_register(15);
if(handler_mode)
{
if((pc&0xF0000000)==0xF0000000)
{
unsigned int sp;
handler_mode = 0;
//fprintf(stderr,"--leaving handler\n");
sp=read_register(13);
write_register(0,read32(sp)); sp+=4;
write_register(1,read32(sp)); sp+=4;
write_register(2,read32(sp)); sp+=4;
write_register(3,read32(sp)); sp+=4;
write_register(12,read32(sp)); sp+=4;
write_register(14,read32(sp)); sp+=4;
pc=read32(sp); sp+=4;
cpsr=read32(sp); sp+=4;
write_register(13,sp);
}
}
if(systick_ctrl&1)
{
if(systick_count)
{
systick_count--;
}
else
{
systick_count=systick_reload;
systick_ctrl|=0x00010000;
}
}
if((systick_ctrl&3)==3)
{
if(systick_ctrl&0x00010000)
{
if(handler_mode==0)
{
unsigned int sp;
systick_ints++;
//fprintf(stderr,"--- enter systick handler\n");
sp=read_register(13);
sp-=4; write32(sp,cpsr);
sp-=4; write32(sp,pc);
sp-=4; write32(sp,read_register(14));
sp-=4; write32(sp,read_register(12));
sp-=4; write32(sp,read_register(3));
sp-=4; write32(sp,read_register(2));
sp-=4; write32(sp,read_register(1));
sp-=4; write32(sp,read_register(0));
write_register(13,sp);
pc=fetch32(0x0000003C); //systick vector
pc+=2;
//write_register(14,0xFFFFFF00);
write_register(14,0xFFFFFFF9);
handler_mode=1;
}
}
}
inst=fetch16(pc-2);
pc+=2;
write_register(15,pc);
if(DISS) fprintf(stderr,"0x%08X: 0x%04X ",(pc-5),inst);
if(inst == 0xE7FE)
{
exit(0);
}
if(output_vcd)
{
unsigned int vv;
fprintf(fpvcd,"b");
for(vv=0x8000;vv;vv>>=1)
{
if(vv&inst) fprintf(fpvcd,"1"); else fprintf(fpvcd,"0");
}
fprintf(fpvcd," inst\n");
}
instructions++;
//ADC
if((inst&0xFFC0)==0x4140)
{
rd=(inst>>0)&0x07;
rm=(inst>>3)&0x07;
if(DISS) fprintf(stderr,"adc r%u,r%u\n",rd,rm);
ra=read_register(rd);
rb=read_register(rm);
rc=ra+rb;
if(cpsr&CPSR_C) rc++;
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
if(cpsr&CPSR_C) { do_cflag(ra,rb,1); do_vflag(ra,rb,1); }
else { do_cflag(ra,rb,0); do_vflag(ra,rb,0); }
return(0);
}
//ADD(1) small immediate two registers
if((inst&0xFE00)==0x1C00)
{
rd=(inst>>0)&0x7;
rn=(inst>>3)&0x7;
rb=(inst>>6)&0x7;
if(rb)
{
if(DISS) fprintf(stderr,"adds r%u,r%u,#0x%X\n",rd,rn,rb);
ra=read_register(rn);
rc=ra+rb;
//fprintf(stderr,"0x%08X = 0x%08X + 0x%08X\n",rc,ra,rb);
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
do_cflag(ra,rb,0);
do_vflag(ra,rb,0);
return(0);
}
else
{
//this is a mov
}
}
//ADD(2) big immediate one register
if((inst&0xF800)==0x3000)
{
rb=(inst>>0)&0xFF;
rd=(inst>>8)&0x7;
if(DISS) fprintf(stderr,"adds r%u,#0x%02X\n",rd,rb);
ra=read_register(rd);
rc=ra+rb;
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
do_cflag(ra,rb,0);
do_vflag(ra,rb,0);
return(0);
}
//ADD(3) three registers
if((inst&0xFE00)==0x1800)
{
rd=(inst>>0)&0x7;
rn=(inst>>3)&0x7;
rm=(inst>>6)&0x7;
if(DISS) fprintf(stderr,"adds r%u,r%u,r%u\n",rd,rn,rm);
ra=read_register(rn);
rb=read_register(rm);
rc=ra+rb;
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
do_cflag(ra,rb,0);
do_vflag(ra,rb,0);
return(0);
}
//ADD(4) two registers one or both high no flags
if((inst&0xFF00)==0x4400)
{
if((inst>>6)&3)
{
//UNPREDICTABLE
}
rd=(inst>>0)&0x7;
rd|=(inst>>4)&0x8;
rm=(inst>>3)&0xF;
if(DISS) fprintf(stderr,"add r%u,r%u\n",rd,rm);
ra=read_register(rd);
rb=read_register(rm);
rc=ra+rb;
if(rd==15)
{
// if((rc&1)==0)
// {
// fprintf(stderr,"add pc,... produced an arm address 0x%08X 0x%08X\n",pc,rc);
// exit(1);
// }
rc&=~1; //write_register may do this as well
rc+=2; //The program counter is special
}
//fprintf(stderr,"0x%08X = 0x%08X + 0x%08X\n",rc,ra,rb);
write_register(rd,rc);
return(0);
}
//ADD(5) rd = pc plus immediate
if((inst&0xF800)==0xA000)
{
rb=(inst>>0)&0xFF;
rd=(inst>>8)&0x7;
rb<<=2;
if(DISS) fprintf(stderr,"add r%u,PC,#0x%02X\n",rd,rb);
ra=read_register(15);
rc=(ra&(~3))+rb;
write_register(rd,rc);
return(0);
}
//ADD(6) rd = sp plus immediate
if((inst&0xF800)==0xA800)
{
rb=(inst>>0)&0xFF;
rd=(inst>>8)&0x7;
rb<<=2;
if(DISS) fprintf(stderr,"add r%u,SP,#0x%02X\n",rd,rb);
ra=read_register(13);
rc=ra+rb;
write_register(rd,rc);
return(0);
}
//ADD(7) sp plus immediate
if((inst&0xFF80)==0xB000)
{
rb=(inst>>0)&0x7F;
rb<<=2;
if(DISS) fprintf(stderr,"add SP,#0x%02X\n",rb);
ra=read_register(13);
rc=ra+rb;
write_register(13,rc);
return(0);
}
//AND
if((inst&0xFFC0)==0x4000)
{
rd=(inst>>0)&0x7;
rm=(inst>>3)&0x7;
if(DISS) fprintf(stderr,"ands r%u,r%u\n",rd,rm);
ra=read_register(rd);
rb=read_register(rm);
rc=ra&rb;
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
return(0);
}
//ASR(1) two register immediate
if((inst&0xF800)==0x1000)
{
rd=(inst>>0)&0x07;
rm=(inst>>3)&0x07;
rb=(inst>>6)&0x1F;
if(DISS) fprintf(stderr,"asrs r%u,r%u,#0x%X\n",rd,rm,rb);
rc=read_register(rm);
if(rb==0)
{
if(rc&0x80000000)
{
do_cflag_bit(1);
rc=~0;
}
else
{
do_cflag_bit(0);
rc=0;
}
}
else
{
do_cflag_bit(rc&(1<<(rb-1)));
ra=rc&0x80000000;
rc>>=rb;
if(ra) //asr, sign is shifted in
{
rc|=(~0)<<(32-rb);
}
}
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
return(0);
}
//ASR(2) two register
if((inst&0xFFC0)==0x4100)
{
rd=(inst>>0)&0x07;
rs=(inst>>3)&0x07;
if(DISS) fprintf(stderr,"asrs r%u,r%u\n",rd,rs);
rc=read_register(rd);
rb=read_register(rs);
rb&=0xFF;
if(rb==0)
{
}
else if(rb<32)
{
do_cflag_bit(rc&(1<<(rb-1)));
ra=rc&0x80000000;
rc>>=rb;
if(ra) //asr, sign is shifted in
{
rc|=(~0)<<(32-rb);
}
}
else
{
if(rc&0x80000000)
{
do_cflag_bit(1);
rc=(~0);
}
else
{
do_cflag_bit(0);
rc=0;
}
}
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
return(0);
}
//B(1) conditional branch
if((inst&0xF000)==0xD000)
{
rb=(inst>>0)&0xFF;
if(rb&0x80) rb|=(~0)<<8;
op=(inst>>8)&0xF;
rb<<=1;
rb+=pc;
rb+=2;
switch(op)
{
case 0x0: //b eq z set
if(DISS) fprintf(stderr,"beq 0x%08X\n",rb-3);
if(cpsr&CPSR_Z)
{
write_register(15,rb);
}
return(0);
case 0x1: //b ne z clear
if(DISS) fprintf(stderr,"bne 0x%08X\n",rb-3);
if(!(cpsr&CPSR_Z))
{
write_register(15,rb);
}
return(0);
case 0x2: //b cs c set
if(DISS) fprintf(stderr,"bcs 0x%08X\n",rb-3);
if(cpsr&CPSR_C)
{
write_register(15,rb);
}
return(0);
case 0x3: //b cc c clear
if(DISS) fprintf(stderr,"bcc 0x%08X\n",rb-3);
if(!(cpsr&CPSR_C))
{
write_register(15,rb);
}
return(0);
case 0x4: //b mi n set
if(DISS) fprintf(stderr,"bmi 0x%08X\n",rb-3);
if(cpsr&CPSR_N)
{
write_register(15,rb);
}
return(0);
case 0x5: //b pl n clear
if(DISS) fprintf(stderr,"bpl 0x%08X\n",rb-3);
if(!(cpsr&CPSR_N))
{
write_register(15,rb);
}
return(0);
case 0x6: //b vs v set
if(DISS) fprintf(stderr,"bvs 0x%08X\n",rb-3);
if(cpsr&CPSR_V)
{
write_register(15,rb);
}
return(0);
case 0x7: //b vc v clear
if(DISS) fprintf(stderr,"bvc 0x%08X\n",rb-3);
if(!(cpsr&CPSR_V))
{
write_register(15,rb);
}
return(0);
case 0x8: //b hi c set z clear
if(DISS) fprintf(stderr,"bhi 0x%08X\n",rb-3);
if((cpsr&CPSR_C)&&(!(cpsr&CPSR_Z)))
{
write_register(15,rb);
}
return(0);
case 0x9: //b ls c clear or z set
if(DISS) fprintf(stderr,"bls 0x%08X\n",rb-3);
if((cpsr&CPSR_Z)||(!(cpsr&CPSR_C)))
{
write_register(15,rb);
}
return(0);
case 0xA: //b ge N == V
if(DISS) fprintf(stderr,"bge 0x%08X\n",rb-3);
ra=0;
if( (cpsr&CPSR_N) && (cpsr&CPSR_V) ) ra++;
if((!(cpsr&CPSR_N))&&(!(cpsr&CPSR_V))) ra++;
if(ra)
{
write_register(15,rb);
}
return(0);
case 0xB: //b lt N != V
if(DISS) fprintf(stderr,"blt 0x%08X\n",rb-3);
ra=0;
if((!(cpsr&CPSR_N))&&(cpsr&CPSR_V)) ra++;
if((!(cpsr&CPSR_V))&&(cpsr&CPSR_N)) ra++;
if(ra)
{
write_register(15,rb);
}
return(0);
case 0xC: //b gt Z==0 and N == V
if(DISS) fprintf(stderr,"bgt 0x%08X\n",rb-3);
ra=0;
if( (cpsr&CPSR_N) && (cpsr&CPSR_V) ) ra++;
if((!(cpsr&CPSR_N))&&(!(cpsr&CPSR_V))) ra++;
if(cpsr&CPSR_Z) ra=0;
if(ra)
{
write_register(15,rb);
}
return(0);
case 0xD: //b le Z==1 or N != V
if(DISS) fprintf(stderr,"ble 0x%08X\n",rb-3);
ra=0;
if((!(cpsr&CPSR_N))&&(cpsr&CPSR_V)) ra++;
if((!(cpsr&CPSR_V))&&(cpsr&CPSR_N)) ra++;
if(cpsr&CPSR_Z) ra++;
if(ra)
{
write_register(15,rb);
}
return(0);
case 0xE:
//undefined instruction
break;
case 0xF:
//swi
break;
}
}
//B(2) unconditional branch
if((inst&0xF800)==0xE000)
{
rb=(inst>>0)&0x7FF;
if(rb&(1<<10)) rb|=(~0)<<11;
rb<<=1;
rb+=pc;
rb+=2;
if(DISS) fprintf(stderr,"B 0x%08X\n",rb-3);
write_register(15,rb);
return(0);
}
//BIC
if((inst&0xFFC0)==0x4380)
{
rd=(inst>>0)&0x7;
rm=(inst>>3)&0x7;
if(DISS) fprintf(stderr,"bics r%u,r%u\n",rd,rm);
ra=read_register(rd);
rb=read_register(rm);
rc=ra&(~rb);
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
return(0);
}
//BKPT
if((inst&0xFF00)==0xBE00)
{
rb=(inst>>0)&0xFF;
fprintf(stderr,"bkpt 0x%02X\n",rb);
return(1);
}
//BL/BLX(1)
if((inst&0xE000)==0xE000) //BL,BLX
{
if((inst&0x1800)==0x1000) //H=b10
{
if(DISS) fprintf(stderr,"\n");
halfadd=inst;
return(0);
}
else
if((inst&0x1800)==0x1800) //H=b11
{
//branch to thumb
rb=halfadd&((1<<11)-1);
if(rb&1<<10) rb|=(~((1<<11)-1)); //sign extend
rb<<=11;
rb|=inst&((1<<11)-1);
rb<<=1;
rb+=pc;
if(DISS) fprintf(stderr,"bl 0x%08X\n",rb-3);
write_register(14,(pc-2)|1);
write_register(15,rb);
return(0);
}
else
if((inst&0x1800)==0x0800) //H=b01
{
//fprintf(stderr,"cannot branch to arm 0x%08X 0x%04X\n",pc,inst);
//return(1);
//branch to thumb
rb=halfadd&((1<<11)-1);
if(rb&1<<10) rb|=(~((1<<11)-1)); //sign extend
rb<<=11;
rb|=inst&((1<<11)-1);
rb<<=1;
rb+=pc;
if(DISS) fprintf(stderr,"bl 0x%08X\n",rb-3);
write_register(14,(pc-2)|1);
write_register(15,rb);
return(0);
}
}
//BLX(2)
if((inst&0xFF87)==0x4780)
{
rm=(inst>>3)&0xF;
if(DISS) fprintf(stderr,"blx r%u\n",rm);
rc=read_register(rm);
//fprintf(stderr,"blx r%u 0x%X 0x%X\n",rm,rc,pc);
rc+=2;
if(rc&1)
{
write_register(14,(pc-2)|1);
write_register(15,rc);
return(0);
}
else
{
fprintf(stderr,"cannot branch to arm 0x%08X 0x%04X\n",pc,inst);
return(1);
}
}
//BX
if((inst&0xFF87)==0x4700)
{
rm=(inst>>3)&0xF;
if(DISS) fprintf(stderr,"bx r%u\n",rm);
rc=read_register(rm);
rc+=2;
//fprintf(stderr,"bx r%u 0x%X 0x%X\n",rm,rc,pc);
if(rc&1)
{
write_register(15,rc);
return(0);
}
else
{
fprintf(stderr,"cannot branch to arm 0x%08X 0x%04X\n",pc,inst);
return(1);
}
}
//CMN
if((inst&0xFFC0)==0x42C0)
{
rn=(inst>>0)&0x7;
rm=(inst>>3)&0x7;
if(DISS) fprintf(stderr,"cmns r%u,r%u\n",rn,rm);
ra=read_register(rn);
rb=read_register(rm);
rc=ra+rb;
do_nflag(rc);
do_zflag(rc);
do_cflag(ra,rb,0);
do_vflag(ra,rb,0);
return(0);
}
//CMP(1) compare immediate