diff --git a/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala b/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala index 27ba41e57..6abb8e474 100644 --- a/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala +++ b/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala @@ -2,144 +2,28 @@ package saxon.board.muselab.ICESugarPro import saxon._ import spinal.core._ -import spinal.core.fiber._ - import spinal.lib.com.uart.UartCtrlMemoryMappedConfig import spinal.lib.bus.bmb._ -import spinal.lib.bus.bsb.{Bsb, BsbInterconnectGenerator, BsbParameter} +import spinal.lib.bus.bsb.BsbInterconnectGenerator import spinal.lib.bus.misc.SizeMapping import spinal.lib.com.jtag.sim.JtagTcp import spinal.lib.com.uart.sim.{UartDecoder, UartEncoder} import spinal.lib.generator._ import spinal.lib.io.{Gpio, InOutWrapper} import spinal.lib.misc.plic.PlicMapping -import spinal.lib.graphic.{RgbConfig} -import spinal.lib.graphic.vga.{Vga,VgaCtrl,BmbVgaCtrlGenerator, BmbVgaCtrlParameter} -import spinal.lib.graphic.{Rgb, RgbConfig} -import spinal.lib.graphic.hdmi.VgaToHdmiEcp5 -import spinal.lib.generator._ -import spinal.lib._ +import spinal.lib.graphic.RgbConfig +import spinal.lib.graphic.vga.{BmbVgaCtrlGenerator, BmbVgaCtrlParameter} import spinal.lib.memory.sdram.sdr._ import spinal.lib.memory.sdram.xdr.CoreParameter import spinal.lib.memory.sdram.xdr.phy.{Ecp5Sdrx2Phy, XilinxS7Phy} import spinal.lib.blackbox.lattice.ecp5.{DCCA, IDDRX1F, ODDRX1F} import spinal.lib.system.dma.sg.{DmaMemoryLayout, DmaSgGenerator} - import vexriscv.VexRiscvBmbGenerator import vexriscv.ip._ import vexriscv._ import vexriscv.plugin._ import spinal.core.fiber._ -//--------------------------------------------------------------------------------- - -object MyBmbVgaCtrl{ - def getBmbCapabilities(accessSource : BmbAccessCapabilities) = BmbSlaveFactory.getBmbCapabilities( - accessSource, - addressWidth = addressWidth, - dataWidth = 32 - ) - def addressWidth = 8 -} - -case class MyBmbVgaCtrl(p : BmbVgaCtrlParameter, - ctrlParameter : BmbParameter, - inputParameter : BsbParameter, - vgaCd : ClockDomain) extends Component{ - - val io = new Bundle{ -// val input = slave(Stream(Fragment(Rgb(p.rgbConfig)))) - val input = slave(Bsb(inputParameter)) - val ctrl = slave(Bmb(ctrlParameter)) - val vga = master(Vga(p.rgbConfig)) - val frameStart = out Bool() - } - - val ctrl = BmbSlaveFactory(io.ctrl) - - val run = ctrl.createReadAndWrite(Bool(),0x00) init(False) - - val vga = new ClockingArea(vgaCd) { - val input = io.input.toStreamFragment(omitMask = true) //TODO - val resized = Stream(Fragment(Bits(16 bits))) - StreamFragmentWidthAdapter(input, resized) - val adapted = Stream(Fragment(Rgb(p.rgbConfig))) - adapted.arbitrationFrom(resized) - adapted.last := resized.last - adapted.r := U(resized.fragment(15-p.rgbConfig.rWidth+1, p.rgbConfig.rWidth bits)) - adapted.g := U(resized.fragment(10-p.rgbConfig.gWidth+1, p.rgbConfig.gWidth bits)) - adapted.b := U(resized.fragment( 4-p.rgbConfig.bWidth+1, p.rgbConfig.bWidth bits)) - - val run = BufferCC(MyBmbVgaCtrl.this.run) - val ctrl = VgaCtrl(p.rgbConfig, p.timingsWidth) - ctrl.feedWith(adapted, resync = run.rise) - io.input.ready setWhen(!run) //Flush - ctrl.io.softReset := !run - - ctrl.io.frameStart <> io.frameStart - ctrl.io.vga <> io.vga - } - - - vga.ctrl.io.timings.driveFrom(ctrl, 0x40) - vga.ctrl.io.timings.addTag(crossClockDomain) -} - -case class MyBmbVgaCtrlGenerator(ctrlOffset : Handle[BigInt] = Unset) - (implicit val interconnect: BmbInterconnectGenerator, val bsbInterconnect : BsbInterconnectGenerator, decoder : BmbImplicitPeripheralDecoder = null) extends Area{ - - val ctrl = Handle(logic.io.ctrl) - val input = Handle(logic.io.input) - val output = Handle(logic.io.vga) - val frameStart = Handle(logic.io.frameStart) - val parameter = Handle[BmbVgaCtrlParameter] - val vgaCd = Handle[ClockDomain] - - val logic : Handle[MyBmbVgaCtrl] = Handle(MyBmbVgaCtrl( - p = parameter, - ctrlParameter = accessRequirements.toBmbParameter(), - inputParameter = BsbParameter( - byteCount = is.byteCount, - sourceWidth = is.sourceWidth, - sinkWidth = is.sinkWidth, - withMask = is.withMask - ), - vgaCd = vgaCd - )) - - val accessSource = Handle[BmbAccessCapabilities] - val accessRequirements = Handle[BmbAccessParameter] - interconnect.addSlave( - accessSource = accessSource, - accessCapabilities = accessSource.derivate(MyBmbVgaCtrl.getBmbCapabilities), - accessRequirements = accessRequirements, - bus = ctrl, - mapping = ctrlOffset.derivate(SizeMapping(_, 1 << MyBmbVgaCtrl.addressWidth)) - ) - if(decoder != null) interconnect.addConnection(decoder.bus, ctrl) - val is = vgaCd on bsbInterconnect.addSlave(input) - is.sinkWidth.load(0) - - def withRegisterPhy(withColorEn : Boolean) = output.produce{ - val reg = out(vgaCd.get(Reg(Vga(output.rgbConfig, false)))) - reg.assignSomeByName(output) - when(!output.colorEn){ - reg.color.clear() - } - reg - } - - def withHdmiEcp5(hdmiCd : Handle[ClockDomain]) = output produce new Area{ - val bridge = VgaToHdmiEcp5(vgaCd, hdmiCd) - bridge.io.vga << output - val gpdi_dp, gpdi_dn = out Bits(4 bits) - gpdi_dp := bridge.io.gpdi_dp - gpdi_dn := bridge.io.gpdi_dn - } -} - -//---------------------------------------------------------------------------- - // Define a SoC abstract enough to be used for simulation class ICESugarProMinimalAbstract extends Area{ @@ -198,7 +82,7 @@ class ICESugarProMinimalAbstract extends Area{ //interconnect.addConnection(dma.readSg, dBus32.bmb) //interconnect.addConnection(dma.writeSg, dBus32.bmb) - val vga = MyBmbVgaCtrlGenerator(0x90000) + val vga = BmbVgaCtrlGenerator(0x90000) bsbInterconnect.connect(dma.vga.stream.output, vga.input) //Interconnect specification @@ -284,9 +168,13 @@ class ICESugarProMinimal extends Component{ val phyA = Ecp5Sdrx2PhyGenerator().connect(sdramA) val hdmiPhy = vga.withHdmiEcp5(hdmiCd.outputClockDomain) - //val vgaPhy = vga.withRegisterPhy(withColorEn = false) + // VGA BUS and timing signal for Overlay Text val vgaBus = Handle(vga.output.toIo) - val frameStart = Handle(vga.frameStart.toIo) + val vga_frameStart = Handle(vga.logic.vga.ctrl.io.frameStart.pull().toIo) + val vga_hctr = Handle(vga.logic.vga.ctrl.h.counter.pull().toIo) + val vga_vctr = Handle(vga.logic.vga.ctrl.v.counter.pull().toIo) + val vga_hstart = Handle(vga.logic.vga.ctrl.io.timings.h.syncStart.pull().toIo) + val vga_vstart = Handle(vga.logic.vga.ctrl.io.timings.v.syncStart.pull().toIo) interconnect.setPipelining(bmbPeripheral.bmb)(cmdHalfRate = true, rspHalfRate = true) interconnect.setPipelining(cpu.dBus)(cmdValid = true)