From d677cd64ef67e85412b30715474c34639faaa52c Mon Sep 17 00:00:00 2001 From: jmio Date: Tue, 19 Oct 2021 19:17:09 +0900 Subject: [PATCH] Bringing the VGA internal signal to the top level (https://github.com/SpinalHDL/SaxonSoc/issues/67#issuecomment-946568303) --- .../saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala b/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala index f2f86699c..618184f5d 100644 --- a/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala +++ b/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala @@ -169,6 +169,7 @@ class ICESugarProMinimal extends Component{ val phyA = Ecp5Sdrx2PhyGenerator().connect(sdramA) val hdmiPhy = vga.withHdmiEcp5(hdmiCd.outputClockDomain) val vgaPhy = vga.withRegisterPhy(withColorEn = false) + val vgaBus = Handle(vga.output.toIo) interconnect.setPipelining(bmbPeripheral.bmb)(cmdHalfRate = true, rspHalfRate = true) interconnect.setPipelining(cpu.dBus)(cmdValid = true)