From a317645d18a0bb545654bd2d7faf67d11a57f808 Mon Sep 17 00:00:00 2001 From: Jean Jonethal Date: Sun, 1 Nov 2015 18:22:53 +0100 Subject: [PATCH] mecrisp-stellaris-ra-1.2 --- CHANGELOG | 4 + README-RA | 17 +- kl25z128-ra/mecrisp-stellaris-kl25z128.bin | Bin 19948 -> 19952 bytes kl25z128/mecrisp-stellaris-kl25z128.srec | 2330 ++++++++--------- linux-ra/mecrisp-stellaris-linux | Bin 320612 -> 320612 bytes lm4f120-ra/mecrisp-stellaris-lm4f120.bin | Bin 19728 -> 19728 bytes .../mecrisp-stellaris-lpc1114fn28.bin | Bin 19512 -> 19516 bytes .../mecrisp-stellaris-lpc1114fn28.hex | 2310 ++++++++-------- mecrisp-stellaris-source/assemble | 8 + mecrisp-stellaris-source/calculatemd5 | 4 + .../common/datastackandmacros.s | 2 +- mecrisp-stellaris-source/common/ra/ra-tools.s | 3 + .../stm32f303-ra/Makefile | 21 + mecrisp-stellaris-source/stm32f303-ra/flash.s | 193 ++ .../stm32f303-ra/interrupts.s | 38 + .../mecrisp-stellaris-stm32f303.s | 80 + mecrisp-stellaris-source/stm32f303-ra/memmap | 13 + .../stm32f303-ra/terminal.s | 172 ++ .../stm32f303-ra/vectors.s | 110 + mecrisp-stellaris-source/stm32f303/flash.s | 4 +- mecrisp-stellaris-source/tidyup | 4 + stm32f303-ra/mecrisp-stellaris-stm32f303.bin | Bin 0 -> 18996 bytes stm32f303-ra/mecrisp-stellaris-stm32f303.hex | 1191 +++++++++ tm4c1294-ra/mecrisp-stellaris-tm4c1294.bin | Bin 20344 -> 20344 bytes 24 files changed, 4178 insertions(+), 2326 deletions(-) create mode 100644 mecrisp-stellaris-source/stm32f303-ra/Makefile create mode 100644 mecrisp-stellaris-source/stm32f303-ra/flash.s create mode 100644 mecrisp-stellaris-source/stm32f303-ra/interrupts.s create mode 100644 mecrisp-stellaris-source/stm32f303-ra/mecrisp-stellaris-stm32f303.s create mode 100644 mecrisp-stellaris-source/stm32f303-ra/memmap create mode 100644 mecrisp-stellaris-source/stm32f303-ra/terminal.s create mode 100644 mecrisp-stellaris-source/stm32f303-ra/vectors.s create mode 100644 stm32f303-ra/mecrisp-stellaris-stm32f303.bin create mode 100644 stm32f303-ra/mecrisp-stellaris-stm32f303.hex diff --git a/CHANGELOG b/CHANGELOG index d7285b0..89e50c3 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -418,3 +418,7 @@ - Merged news from 2.1.6 into this package - Improved tuck + +01.11.2015, Matthias Koch, Mecrisp-Stellaris RA 1.2 + + - Jean Jonethal added STM32F303-RA and fixed a bug. diff --git a/README-RA b/README-RA index b855a4e..6a8b276 100644 --- a/README-RA +++ b/README-RA @@ -13,10 +13,21 @@ This time, it contains an analytical compiler which keeps track of the top five stack elements and maps them to registers whenever possible. -Five targets are available: -KL25Z128 & LPC1114FN28 (Cortex M0), ARM Linux and LM4F120 & TM4C1294 (Cortex M4). +Currently available targets for RA testing: -For M4, you can flash your Stellaris or Tiva Launchpad with the included binary. +Cortex M0: + + KL25Z128 + LPC1114FN28 + +Cortex M4: + + LM4F120 + TM4C1294 + ARM Linux + STM32F303 + +For M4, you can flash your boards with the included binaries. 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zrpj?l0ndWcX`{aPo^#HlbRPs)=?=JCO@6w*u0p3-b@Wv?ap_sQI=xkwu>0-pL1)Zy*I>2KE!x=teyorfm7Z0P0*|mM6`1BsjTpRIKUV>4Vn|8f-#pR%y zgR@eS;#|r0(nilAcMH+_X1E{EcHf)fUYMQXa=`3qzzE&sQHW1@F!R8O$3%xDB92t!ACO!PC_($xP0tiQQ`UfHr_uCNe zbjmOA5OFj(7#!N~8SA7z_FX>FsjL}7%qU;zL@W719FA_Q-s~UV$`|7AW4U4!BXgy& y3UXGe=P^ixhpdLWm2!R`=J#7+-Q2#1-yec)D-~$t*vk8~4hC2KLG mecrisp-stellaris-stm32f303.list + $(ARMGNU)-objcopy mecrisp-stellaris-stm32f303.elf mecrisp-stellaris-stm32f303.bin -O binary + +clean: + rm -f *.bin + rm -f *.o + rm -f *.elf + rm -f *.list diff --git a/mecrisp-stellaris-source/stm32f303-ra/flash.s b/mecrisp-stellaris-source/stm32f303-ra/flash.s new file mode 100644 index 0000000..5e0c53b --- /dev/null +++ b/mecrisp-stellaris-source/stm32f303-ra/flash.s @@ -0,0 +1,193 @@ +@ +@ Mecrisp-Stellaris - A native code Forth implementation for ARM-Cortex M microcontrollers +@ Copyright (C) 2013 Matthias Koch +@ +@ This program is free software: you can redistribute it and/or modify +@ it under the terms of the GNU General Public License as published by +@ the Free Software Foundation, either version 3 of the License, or +@ (at your option) any later version. +@ +@ This program is distributed in the hope that it will be useful, +@ but WITHOUT ANY WARRANTY; without even the implied warranty of +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +@ GNU General Public License for more details. +@ +@ You should have received a copy of the GNU General Public License +@ along with this program. If not, see . +@ + +@ Schreiben und Löschen des Flash-Speichers im STM32F303. + +@ In diesem Chip gibt es Flashschreibzugriffe mit wählbarer Breite - +@ so ist es diesmal ganz komfortabel. Leider gibt es nur weniger große +@ Sektoren, die getrennt gelöscht werden können. + +@ Write and Erase Flash in STM32F303. +@ Porting: Rewrite this ! You need hflash! and - as far as possible - cflash! + + +.equ FLASH_Base, 0x40022000 + +.equ FLASH_ACR, FLASH_Base + 0x00 @ Flash Access Control Register +.equ FLASH_KEYR, FLASH_Base + 0x04 @ Flash Key Register +.equ FLASH_OPTKEYR, FLASH_Base + 0x08 @ Flash Option Key Register +.equ FLASH_SR, FLASH_Base + 0x0C @ Flash Status Register +.equ FLASH_CR, FLASH_Base + 0x10 @ Flash Control Register +.equ FLASH_AR, FLASH_Base + 0x14 @ Flash Address Register +.equ FLASH_OBR, FLASH_Base + 0x1C @ Flash Option Byte Register + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "hflash!" @ ( x Addr -- ) + @ Schreibt an die auf 2 gerade Adresse in den Flash. +h_flashkomma: +@ ----------------------------------------------------------------------------- + popda r0 @ Adresse + popda r1 @ Inhalt. + + @ Ist die gewünschte Stelle im Flash-Dictionary ? Außerhalb des Forth-Kerns ? + ldr r3, =Kernschutzadresse + cmp r0, r3 + blo 3f + + ldr r3, =FlashDictionaryEnde + cmp r0, r3 + bhs 3f + + + @ Prüfe Inhalt. Schreibe nur, wenn es NICHT -1 ist. + ldr r3, =0xFFFF + ands r1, r3 @ High-Halfword der Daten wegmaskieren + cmp r1, r3 + beq 2f @ Fertig ohne zu Schreiben + + @ Prüfe die Adresse: Sie muss auf 2 gerade sein: + movs r2, #1 + ands r2, r0 + cmp r2, #0 + bne 3f + + @ Ist an der gewünschten Stelle -1 im Speicher ? + ldrh r2, [r0] + cmp r2, r3 + bne 3f + + @ Okay, alle Proben bestanden. + + @ Im STM32F051 ist der Flash-Speicher gespiegelt, die wirkliche Adresse liegt weiter hinten ! + @ Flash memory is mirrored, use true address later for write + ldr r2, =0x08000000 + adds r0, r2 + + @ Bereit zum Schreiben ! + + @ Unlock Flash Control + ldr r2, =FLASH_KEYR + ldr r3, =0x45670123 + str r3, [r2] + ldr r3, =0xCDEF89AB + str r3, [r2] + + @ Enable write + ldr r2, =FLASH_CR + movs r3, #1 @ Select Flash programming + str r3, [r2] + + @ Write to Flash ! + strh r1, [r0] + + @ Wait for Flash BUSY Flag to be cleared + ldr r2, =FLASH_SR + +1: ldr r3, [r2] + @ ands r3, #1 + movs r0, #1 + ands r0, r3 + bne 1b + + @ Lock Flash after finishing this + ldr r2, =FLASH_CR + movs r3, #0x80 + str r3, [r2] + +2:bx lr +3:Fehler_Quit "Wrong address or data for writing flash !" + + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "flashpageerase" @ ( Addr -- ) + @ Löscht einen 2kb großen Flashblock Deletes one 2kb Flash page +flashpageerase: +@ ----------------------------------------------------------------------------- + push {r0, r1, r2, r3, lr} + popda r0 @ Adresse zum Löschen holen Fetch address to erase. + + @ Ist die gewünschte Stelle im Flash-Dictionary ? Außerhalb des Forth-Kerns ? Don't erase Forth core. + ldr r3, =Kernschutzadresse + cmp r0, r3 + blo 2f + + ldr r2, =FLASH_KEYR + ldr r3, =0x45670123 + str r3, [r2] + ldr r3, =0xCDEF89AB + str r3, [r2] + + @ Enable erase + ldr r2, =FLASH_CR + movs r3, #2 @ Set Erase bit + str r3, [r2] + + @ Set page to erase + ldr r2, =FLASH_AR + str r0, [r2] + + @ Start erasing + ldr r2, =FLASH_CR + movs r3, #0x42 @ Start + Erase + str r3, [r2] + + @ Wait for Flash BUSY Flag to be cleared + ldr r2, =FLASH_SR +1: ldr r3, [r2] + movs r0, #1 + ands r0, r3 + bne 1b + + @ Lock Flash after finishing this + ldr r2, =FLASH_CR + movs r3, #0x80 + str r3, [r2] + +2:pop {r0, r1, r2, r3, pc} + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "eraseflash" @ ( -- ) + @ Löscht den gesamten Inhalt des Flashdictionaries. +@ ----------------------------------------------------------------------------- + ldr r0, =FlashDictionaryAnfang +eraseflash_intern: + cpsid i + ldr r1, =FlashDictionaryEnde + ldr r2, =0xFFFF + +1: ldrh r3, [r0] + cmp r3, r2 + beq 2f + pushda r0 + dup + write "Erase block at " + bl hexdot + writeln " from Flash" + bl flashpageerase +2: adds r0, #2 + cmp r0, r1 + bne 1b + writeln "Finished. Reset !" + bl Restart + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "eraseflashfrom" @ ( Addr -- ) + @ Beginnt an der angegebenen Adresse mit dem Löschen des Dictionaries. +@ ----------------------------------------------------------------------------- + popda r0 + b.n eraseflash_intern diff --git a/mecrisp-stellaris-source/stm32f303-ra/interrupts.s b/mecrisp-stellaris-source/stm32f303-ra/interrupts.s new file mode 100644 index 0000000..00608d9 --- /dev/null +++ b/mecrisp-stellaris-source/stm32f303-ra/interrupts.s @@ -0,0 +1,38 @@ +@ +@ Mecrisp-Stellaris - A native code Forth implementation for ARM-Cortex M microcontrollers +@ Copyright (C) 2013 Matthias Koch +@ +@ This program is free software: you can redistribute it and/or modify +@ it under the terms of the GNU General Public License as published by +@ the Free Software Foundation, either version 3 of the License, or +@ (at your option) any later version. +@ +@ This program is distributed in the hope that it will be useful, +@ but WITHOUT ANY WARRANTY; without even the implied warranty of +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +@ GNU General Public License for more details. +@ +@ You should have received a copy of the GNU General Public License +@ along with this program. If not, see . +@ + +@ Routinen für die Interrupthandler, die zur Laufzeit neu gesetzt werden können. +@ Code for interrupt handlers that are exchangeable on the fly + +@------------------------------------------------------------------------------ +@ Alle Interrupthandler funktionieren gleich und werden komfortabel mit einem Makro erzeugt: +@ All interrupt handlers work the same way and are generated with a macro: +@------------------------------------------------------------------------------ + +interrupt exti0 +interrupt exti1 +interrupt exti2 +interrupt exti3 +interrupt exti4 +interrupt adc +interrupt tim2 +interrupt tim3 +interrupt tim4 + +@------------------------------------------------------------------------------ + diff --git a/mecrisp-stellaris-source/stm32f303-ra/mecrisp-stellaris-stm32f303.s b/mecrisp-stellaris-source/stm32f303-ra/mecrisp-stellaris-stm32f303.s new file mode 100644 index 0000000..b45092a --- /dev/null +++ b/mecrisp-stellaris-source/stm32f303-ra/mecrisp-stellaris-stm32f303.s @@ -0,0 +1,80 @@ +@ +@ Mecrisp-Stellaris - A native code Forth implementation for ARM-Cortex M microcontrollers +@ Copyright (C) 2013 Matthias Koch +@ +@ This program is free software: you can redistribute it and/or modify +@ it under the terms of the GNU General Public License as published by +@ the Free Software Foundation, either version 3 of the License, or +@ (at your option) any later version. +@ +@ This program is distributed in the hope that it will be useful, +@ but WITHOUT ANY WARRANTY; without even the implied warranty of +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +@ GNU General Public License for more details. +@ +@ You should have received a copy of the GNU General Public License +@ along with this program. If not, see . +@ + +.syntax unified +.cpu cortex-m4 +.thumb + +@ ----------------------------------------------------------------------------- +@ Swiches for capabilities of this chip +@ ----------------------------------------------------------------------------- + +.equ registerallocator, 1 +@ .equ charkommaavailable, 1 Not available. + +@ ----------------------------------------------------------------------------- +@ Start with some essential macro definitions +@ ----------------------------------------------------------------------------- + +.include "../common/datastackandmacros.s" + +@ ----------------------------------------------------------------------------- +@ Speicherkarte für Flash und RAM +@ Memory map for Flash and RAM +@ ----------------------------------------------------------------------------- + +@ Konstanten für die Größe des Ram-Speichers + +.equ RamAnfang, 0x20000000 @ Start of RAM Porting: Change this ! +.equ RamEnde, 0x2000A000 @ End of RAM. 40 kb. Porting: Change this ! + +@ Konstanten für die Größe und Aufteilung des Flash-Speichers + +.equ Kernschutzadresse, 0x00005000 @ Darunter wird niemals etwas geschrieben ! Mecrisp core never writes flash below this address. +.equ FlashDictionaryAnfang, 0x00005000 @ 20 kb für den Kern reserviert... 20 kb Flash reserved for core. +.equ FlashDictionaryEnde, 0x00040000 @ 236 kb Platz für das Flash-Dictionary 236 kb Flash available. Porting: Change this ! +.equ Backlinkgrenze, RamAnfang @ Ab dem Ram-Start. + + +@ ----------------------------------------------------------------------------- +@ Anfang im Flash - Interruptvektortabelle ganz zu Beginn +@ Flash start - Vector table has to be placed here +@ ----------------------------------------------------------------------------- +.text @ Hier beginnt das Vergnügen mit der Stackadresse und der Einsprungadresse +.include "vectors.s" @ You have to change vectors for Porting ! + +@ ----------------------------------------------------------------------------- +@ Include the Forth core of Mecrisp-Stellaris +@ ----------------------------------------------------------------------------- + +.include "../common/forth-core.s" + +@ ----------------------------------------------------------------------------- +Reset: @ Einsprung zu Beginn +@ ----------------------------------------------------------------------------- + @ Initialisierungen der Hardware, habe und brauche noch keinen Datenstack dafür + @ Initialisations for Terminal hardware, without Datastack. + bl uart_init + + @ Catch the pointers for Flash dictionary + .include "../common/catchflashpointers.s" + + welcome " for STM32F303 by Matthias Koch" + + @ Ready to fly ! + .include "../common/boot.s" diff --git a/mecrisp-stellaris-source/stm32f303-ra/memmap b/mecrisp-stellaris-source/stm32f303-ra/memmap new file mode 100644 index 0000000..0b333c5 --- /dev/null +++ b/mecrisp-stellaris-source/stm32f303-ra/memmap @@ -0,0 +1,13 @@ + +MEMORY +{ + rom(RX) : ORIGIN = 0x00000000, LENGTH = 0x5000 + ram(WAIL) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + +SECTIONS +{ + .text : { *(.text*) } > rom + .bss : { *(.bss*) } > ram +} + diff --git a/mecrisp-stellaris-source/stm32f303-ra/terminal.s b/mecrisp-stellaris-source/stm32f303-ra/terminal.s new file mode 100644 index 0000000..d1270da --- /dev/null +++ b/mecrisp-stellaris-source/stm32f303-ra/terminal.s @@ -0,0 +1,172 @@ +@ +@ Mecrisp-Stellaris - A native code Forth implementation for ARM-Cortex M microcontrollers +@ Copyright (C) 2013 Matthias Koch +@ +@ This program is free software: you can redistribute it and/or modify +@ it under the terms of the GNU General Public License as published by +@ the Free Software Foundation, either version 3 of the License, or +@ (at your option) any later version. +@ +@ This program is distributed in the hope that it will be useful, +@ but WITHOUT ANY WARRANTY; without even the implied warranty of +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +@ GNU General Public License for more details. +@ +@ You should have received a copy of the GNU General Public License +@ along with this program. If not, see . +@ + +@ Terminalroutinen +@ Terminal code and initialisations. +@ Porting: Rewrite this ! + + .equ GPIOA_BASE , 0x48000000 + .equ GPIOA_MODER , GPIOA_BASE + 0x00 + .equ GPIOA_OTYPER , GPIOA_BASE + 0x04 + .equ GPIOA_OSPEEDR , GPIOA_BASE + 0x08 + .equ GPIOA_PUPDR , GPIOA_BASE + 0x0C + .equ GPIOA_IDR , GPIOA_BASE + 0x10 + .equ GPIOA_ODR , GPIOA_BASE + 0x14 + .equ GPIOA_BSRR , GPIOA_BASE + 0x18 + .equ GPIOA_LCKR , GPIOA_BASE + 0x1C + .equ GPIOA_AFRL , GPIOA_BASE + 0x20 + .equ GPIOA_AFRH , GPIOA_BASE + 0x24 + .equ GPIOA_BRR , GPIOA_BASE + 0x28 + + .equ RCC_BASE , 0x40021000 + .equ RCC_AHBENR , RCC_BASE + 0x14 + .equ RCC_APB2ENR , RCC_BASE + 0x18 + .equ RCC_APB1ENR , RCC_BASE + 0x1C + + @ Note that the STM32F051 and STM32F303 USART is different to the bigger STM32F1/STM32F4 chips. + + .equ USART1_BASE , 0x40013800 + + .equ USART1_CR1 , USART1_BASE + 0x00 + .equ USART1_CR2 , USART1_BASE + 0x04 + .equ USART1_CR3 , USART1_BASE + 0x08 + .equ USART1_BRR , USART1_BASE + 0x0C + .equ USART1_GTPR , USART1_BASE + 0x10 + .equ USART1_RTOR , USART1_BASE + 0x14 + .equ USART1_RQR , USART1_BASE + 0x18 + .equ USART1_ISR , USART1_BASE + 0x1C + .equ USART1_ICR , USART1_BASE + 0x20 + .equ USART1_RDR , USART1_BASE + 0x24 + .equ USART1_TDR , USART1_BASE + 0x28 + + @ Flags for USART1_ISR register: + .equ RXNE , BIT5 + .equ TC , BIT6 + .equ TXE , BIT7 + +@ ----------------------------------------------------------------------------- +uart_init: @ ( -- ) A few bits are different to STM32F051 +@ ----------------------------------------------------------------------------- + + @ Enable all GPIO peripheral clock + ldr r1, = RCC_AHBENR + ldr r0, = BIT22+BIT21+BIT20+BIT19+BIT18+BIT17 + 0x14 @ $14 is Reset value + str r0, [r1] + + @ Enable the USART1 peripheral clock + ldr r1, = RCC_APB2ENR + ldr r0, = BIT14 + str r0, [r1] + + @ Set PORTA pins 9 and 10 in alternate function mode + ldr r1, = GPIOA_MODER + ldr r0, = 0xA8280000 @ A800 0000 is Reset value for Port A, and switch PA9 and PA10 to alternate function + str r0, [r1] + + @ Set alternate function 7 to enable USART 1 pins on Port A + ldr r1, = GPIOA_AFRH + ldr r0, = 0x770 @ Alternate function 7 for TX and RX pins of USART1 on PORTA + str r0, [r1] + + @ Configure BRR by deviding the bus clock with the baud rate + ldr r1, = USART1_BRR + movs r0, #0x46 @ 115200 bps, ein ganz kleines bisschen langsamer... + str r0, [r1] + + @ disable overrun detection before UE to avoid USART blocking on overflow + ldr r1, =USART1_CR3 + ldr r0, =BIT12 @ USART_CR3_OVRDIS + str r0, [r1] + + @ Enable the USART, TX, and RX circuit + ldr r1, =USART1_CR1 + ldr r0, =BIT3+BIT2+BIT0 @ USART_CR1_UE | USART_CR1_TE | USART_CR1_RE + str r0, [r1] + + bx lr + +@ Following code is the same as for STM32F051 +.include "../common/terminalhooks.s" + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "serial-emit" +serial_emit: @ ( c -- ) Emit one character +@ ----------------------------------------------------------------------------- + push {lr} + +1: bl serial_qemit + cmp tos, #0 + drop + beq 1b + + ldr r2, =USART1_TDR + strb tos, [r2] @ Output the character + drop + + pop {pc} + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "serial-key" +serial_key: @ ( -- c ) Receive one character +@ ----------------------------------------------------------------------------- + push {lr} + +1: bl serial_qkey + cmp tos, #0 + drop + beq 1b + + pushdatos + ldr r2, =USART1_RDR + ldrb tos, [r2] @ Fetch the character + + pop {pc} + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "serial-emit?" +serial_qemit: @ ( -- ? ) Ready to send a character ? +@ ----------------------------------------------------------------------------- + push {lr} + bl pause + + pushdaconst 0 @ False Flag + ldr r0, =USART1_ISR + ldr r1, [r0] @ Fetch status + movs r0, #TXE + ands r1, r0 + beq 1f + mvns tos, tos @ True Flag +1: pop {pc} + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "serial-key?" +serial_qkey: @ ( -- ? ) Is there a key press ? +@ ----------------------------------------------------------------------------- + push {lr} + bl pause + + pushdaconst 0 @ False Flag + ldr r0, =USART1_ISR + ldr r1, [r0] @ Fetch status + movs r0, #RXNE + ands r1, r0 + beq 1f + mvns tos, tos @ True Flag +1: pop {pc} + + .ltorg @ Hier werden viele spezielle Hardwarestellenkonstanten gebraucht, schreibe sie gleich ! diff --git a/mecrisp-stellaris-source/stm32f303-ra/vectors.s b/mecrisp-stellaris-source/stm32f303-ra/vectors.s new file mode 100644 index 0000000..f29fc7c --- /dev/null +++ b/mecrisp-stellaris-source/stm32f303-ra/vectors.s @@ -0,0 +1,110 @@ +@ +@ Mecrisp-Stellaris - A native code Forth implementation for ARM-Cortex M microcontrollers +@ Copyright (C) 2013 Matthias Koch +@ +@ This program is free software: you can redistribute it and/or modify +@ it under the terms of the GNU General Public License as published by +@ the Free Software Foundation, either version 3 of the License, or +@ (at your option) any later version. +@ +@ This program is distributed in the hope that it will be useful, +@ but WITHOUT ANY WARRANTY; without even the implied warranty of +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +@ GNU General Public License for more details. +@ +@ You should have received a copy of the GNU General Public License +@ along with this program. If not, see . +@ + +@ ----------------------------------------------------------------------------- +@ Interruptvektortabelle +@ ----------------------------------------------------------------------------- + +.include "../common/vectors-common.s" + +@ Special interrupt handlers for this particular chip: + +.word nullhandler+1 @ Position 0: Window Watchdog +.word nullhandler+1 @ Position 1: PVD through EXTI line detection +.word nullhandler+1 @ Position 2: Tamper and TimeStamp through EXTI line +.word nullhandler+1 @ Position 3: RTC Wakeup +.word nullhandler+1 @ Position 4: Flash +.word nullhandler+1 @ Position 5: RCC +.word irq_vektor_exti0+1 @ Position 6: EXTI Line 0 +.word irq_vektor_exti1+1 @ Position 7: EXTI Line 1 +.word irq_vektor_exti2+1 @ Position 8: EXTI Line 2 +.word irq_vektor_exti3+1 @ Position 9: EXTI Line 3 +.word irq_vektor_exti4+1 @ Position 10: EXTI Line 4 +.word nullhandler+1 @ Position 11: DMA1 Stream 0 +.word nullhandler+1 @ Position 12: DMA1 Stream 1 +.word nullhandler+1 @ Position 13: DMA1 Stream 2 +.word nullhandler+1 @ Position 14: DMA1 Stream 3 +.word nullhandler+1 @ Position 15: DMA1 Stream 4 +.word nullhandler+1 @ Position 16: DMA1 Stream 5 +.word nullhandler+1 @ Position 17: DMA1 Stream 6 +.word irq_vektor_adc+1 @ Position 18: ADC global interrupts +.word nullhandler+1 @ Position 19: +.word nullhandler+1 @ Position 20: +.word nullhandler+1 @ Position 21: +.word nullhandler+1 @ Position 22: +.word nullhandler+1 @ Position 23: +.word nullhandler+1 @ Position 24: +.word nullhandler+1 @ Position 25: +.word nullhandler+1 @ Position 26: +.word nullhandler+1 @ Position 27: +.word irq_vektor_tim2+1 @ Position 28: Timer 2 global interrupt +.word irq_vektor_tim3+1 @ Position 29: Timer 3 global interrupt +.word irq_vektor_tim4+1 @ Position 30: Timer 4 global interrupt +.word nullhandler+1 @ Position 31: +.word nullhandler+1 @ Position 32: +.word nullhandler+1 @ Position 33: +.word nullhandler+1 @ Position 34: +.word nullhandler+1 @ Position 35: +.word nullhandler+1 @ Position 36: +.word nullhandler+1 @ Position 37: +.word nullhandler+1 @ Position 38: +.word nullhandler+1 @ Position 39: +.word nullhandler+1 @ Position 40: +.word nullhandler+1 @ Position 41: +.word nullhandler+1 @ Position 42: +.word nullhandler+1 @ Position 43: +.word nullhandler+1 @ Position 44: +.word nullhandler+1 @ Position 45: +.word nullhandler+1 @ Position 46: +.word nullhandler+1 @ Position 47: +.word nullhandler+1 @ Position 48: +.word nullhandler+1 @ Position 49: +.word nullhandler+1 @ Position 50: +.word nullhandler+1 @ Position 51: +.word nullhandler+1 @ Position 52: +.word nullhandler+1 @ Position 53: +.word nullhandler+1 @ Position 54: +.word nullhandler+1 @ Position 55: +.word nullhandler+1 @ Position 56: +.word nullhandler+1 @ Position 57: +.word nullhandler+1 @ Position 58: +.word nullhandler+1 @ Position 59: +.word nullhandler+1 @ Position 60: +.word nullhandler+1 @ Position 61: +.word nullhandler+1 @ Position 62: +.word nullhandler+1 @ Position 63: +.word nullhandler+1 @ Position 64: +.word nullhandler+1 @ Position 65: +.word nullhandler+1 @ Position 66: +.word nullhandler+1 @ Position 67: +.word nullhandler+1 @ Position 68: +.word nullhandler+1 @ Position 69: +.word nullhandler+1 @ Position 70: +.word nullhandler+1 @ Position 71: +.word nullhandler+1 @ Position 72: +.word nullhandler+1 @ Position 73: +.word nullhandler+1 @ Position 74: +.word nullhandler+1 @ Position 75: +.word nullhandler+1 @ Position 76: +.word nullhandler+1 @ Position 77: +.word nullhandler+1 @ Position 78: +.word nullhandler+1 @ Position 79: +.word nullhandler+1 @ Position 80: +.word nullhandler+1 @ Position 81: + +@ ----------------------------------------------------------------------------- diff --git a/mecrisp-stellaris-source/stm32f303/flash.s b/mecrisp-stellaris-source/stm32f303/flash.s index 0bb988a..5e0c53b 100644 --- a/mecrisp-stellaris-source/stm32f303/flash.s +++ b/mecrisp-stellaris-source/stm32f303/flash.s @@ -16,13 +16,13 @@ @ along with this program. If not, see . @ -@ Schreiben und Löschen des Flash-Speichers im STM32F051. +@ Schreiben und Löschen des Flash-Speichers im STM32F303. @ In diesem Chip gibt es Flashschreibzugriffe mit wählbarer Breite - @ so ist es diesmal ganz komfortabel. Leider gibt es nur weniger große @ Sektoren, die getrennt gelöscht werden können. -@ Write and Erase Flash in STM32F051. +@ Write and Erase Flash in STM32F303. @ Porting: Rewrite this ! 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