From 09ea023373497a1af00d9a69897131673cd0c83e Mon Sep 17 00:00:00 2001 From: Jean Jonethal Date: Mon, 26 Oct 2015 11:14:47 +0100 Subject: [PATCH] mecrisp-stellaris-ra-1.0 --- CHANGELOG | 7 +- CREDITS | 2 + README | 1 + common/sine.txt | 22 +- kl25z128-ra/buildfresh | 1 + kl25z128-ra/mecrisp-stellaris-kl25z128.bin | Bin 19748 -> 19948 bytes kl25z128-ra/sine.txt | 109 + kl25z128/mecrisp-stellaris-kl25z128.srec | 2338 +++++++++-------- linux-ra/mecrisp-stellaris-linux | Bin 320328 -> 320612 bytes lm4f120-ra/mecrisp-stellaris-lm4f120.bin | Bin 19608 -> 19728 bytes .../mecrisp-stellaris-lpc1114fn28.bin | Bin 19312 -> 19512 bytes .../mecrisp-stellaris-lpc1114fn28.hex | 2317 ++++++++-------- mecrisp-stellaris-source/assemble | 8 + mecrisp-stellaris-source/calculatemd5 | 4 + .../common/datastackandmacros.s | 2 +- .../common/ra/calculations.s | 30 +- mecrisp-stellaris-source/common/ra/case.s | 8 +- .../common/ra/comparisions.s | 26 +- mecrisp-stellaris-source/common/ra/double.s | 141 +- mecrisp-stellaris-source/common/ra/logic.s | 2 + mecrisp-stellaris-source/common/ra/ra-logic.s | 90 +- mecrisp-stellaris-source/common/ra/ra-tools.s | 49 +- mecrisp-stellaris-source/stm32l152rb/Makefile | 21 + mecrisp-stellaris-source/stm32l152rb/flash.s | 204 ++ .../stm32l152rb/interrupts.s | 38 + .../mecrisp-stellaris-stm32l152rb.s | 81 + mecrisp-stellaris-source/stm32l152rb/memmap | 13 + .../stm32l152rb/terminal.s | 105 + .../stm32l152rb/vectors.s | 86 + mecrisp-stellaris-source/tidyup | 4 + stm32l152rb/blinky.txt | 18 + stm32l152rb/mecrisp-stellaris-stm32l152rb.bin | Bin 0 -> 15004 bytes stm32l152rb/mecrisp-stellaris-stm32l152rb.hex | 941 +++++++ stm32l152rb/st32l152.f | 481 ++++ tm4c1294-ra/mecrisp-stellaris-tm4c1294.bin | Bin 20224 -> 20344 bytes 35 files changed, 4643 insertions(+), 2506 deletions(-) create mode 100644 kl25z128-ra/sine.txt create mode 100644 mecrisp-stellaris-source/stm32l152rb/Makefile create mode 100644 mecrisp-stellaris-source/stm32l152rb/flash.s create mode 100644 mecrisp-stellaris-source/stm32l152rb/interrupts.s create mode 100644 mecrisp-stellaris-source/stm32l152rb/mecrisp-stellaris-stm32l152rb.s create mode 100644 mecrisp-stellaris-source/stm32l152rb/memmap create mode 100644 mecrisp-stellaris-source/stm32l152rb/terminal.s create mode 100644 mecrisp-stellaris-source/stm32l152rb/vectors.s create mode 100644 stm32l152rb/blinky.txt create mode 100644 stm32l152rb/mecrisp-stellaris-stm32l152rb.bin create mode 100644 stm32l152rb/mecrisp-stellaris-stm32l152rb.hex create mode 100644 stm32l152rb/st32l152.f diff --git a/CHANGELOG b/CHANGELOG index 65ae475..90d77af 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -392,7 +392,12 @@ - Contribution by Ulrich Hoffman: Examples for syscall usage in ARM Linux -11.10.2015, Matthias Koch, Mecrisp-Stellaris 2.2.0 & RA 0.6 experimental +15.10.2015, Matthias Koch, Mecrisp-Stellaris 2.1.5 + + - Contribution by Абдрахимов Илья: + New target: STM L152 Discovery + +22.10.2015, Matthias Koch, Mecrisp-Stellaris 2.2.0 & RA 1.0 experimental - Merged the experimental RA branch with the mainstream package diff --git a/CREDITS b/CREDITS index aedf280..ad6b701 100644 --- a/CREDITS +++ b/CREDITS @@ -13,6 +13,7 @@ Examples for LPC1114FN28 by Bert Lohmann Nucleo STM32F411 port by Jean Jonethal An example for a custom prompt by Glen Worstell Syscall usage examples by Ulrich Hoffmann +Discovery L152 port by Абдрахимов Илья Hardware donations: @@ -27,6 +28,7 @@ Carsten Strotmann Testing and hints in alphabetical order: John O. 'Sandy' Bumgarner +Ulrich Hoffmann Jean Jonethal Michael Kalus Izidor Makuc diff --git a/README b/README index e6445c5..ec39b7d 100644 --- a/README +++ b/README @@ -44,6 +44,7 @@ Contributions: - Teensy 3.1 with MK20DX256VLH7 - Chinese QF-LM4F232 with LM4F232H5QC - nRFgo Starter Kit with nRF51822 + - STM L152 Discovery with STM32L152RBT6 http://mecrisp.sourceforge.net/ diff --git a/common/sine.txt b/common/sine.txt index 6972d84..f462377 100644 --- a/common/sine.txt +++ b/common/sine.txt @@ -48,29 +48,21 @@ decimal : 2rshift 0 ?do d2/ loop ; -: cordic-erster-teil +: cordic ( f-angle -- f-error f-sine f-cosine ) + ( Angle between -Pi/2 and +Pi/2 ! ) + 0 0 $9B74EDA8 0 + 32 0 do + 2rot dup 0< + if i e^ka 0 d+ 2rot 2rot 2over i 2rshift 2rot 2rot 2swap 2over i 2rshift d- 2rot 2rot d+ -; - -: cordic-zweiter-teil + else i e^ka 0 d- 2rot 2rot 2over i 2rshift 2rot 2rot 2swap 2over i 2rshift d+ 2rot 2rot 2swap d- -; - -: cordic ( f-angle -- f-error f-sine f-cosine ) - ( Angle between -Pi/2 and +Pi/2 ! ) - 0 0 $9B74EDA8 0 - 32 0 do - 2rot dup 0< - if - cordic-erster-teil - else - cordic-zweiter-teil then loop 2-foldable ; diff --git a/kl25z128-ra/buildfresh b/kl25z128-ra/buildfresh index 326747d..ff7806a 100644 --- a/kl25z128-ra/buildfresh +++ b/kl25z128-ra/buildfresh @@ -4,4 +4,5 @@ cd ../mecrisp-stellaris-source ./assemble cd ../kl25z128-ra +ls -l *.bin ./thumbulator *.bin diff --git a/kl25z128-ra/mecrisp-stellaris-kl25z128.bin b/kl25z128-ra/mecrisp-stellaris-kl25z128.bin index a449d6baae8ae6c444691010f0d82f2730432001..e098af15b93bf96b8baa1744118835e4778909d4 100644 GIT binary patch delta 9388 zcmbVSdvsG(y5HyI(Fdh11=1I7lNLhXq$#uoN}4v97AO$`9TXgsHmM1gHl_uOat*Ih zL~Fumz0+q83!gtBq`JS63vO;D#I=f*M`q*(2_X-nG4;pl4JhpU|1Hl$ z_7DFD`M&{^_0LA8!@DY!mtMbKCCc@5hI+oRpDtGC347@G)Fr~JbeDSe^uu!EDKoJS zs|Hm4chYCni-b1%zItQlYKJPkc}(44ake`0ZK|+)EOCJJlW@`)38$c>p=6-U9wP&3 z{f#ZM^q!m+uU+CbD`*#Z&4Stxuhp~&UTvZ1%rDVgWV#o_O6?eZTBFN57)cCiOSB`5 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+07FF556E , +03FFEAAB , +01FFFD55 , + +00FFFFAA , +007FFFF5 , +003FFFFE , +001FFFFF , +000FFFFF , +0007FFFF , +0003FFFF , +0001FFFF , + +0000FFFF , +00007FFF , +00003FFF , +00001FFF , +00000FFF , +000007FF , +000003FF , +000001FF , + +000000FF , +0000007F , +0000003F , +0000001F , +0000000F , +00000007 , +00000003 , +00000001 , + +decimal + +: 2rshift 0 ?do d2/ loop ; + +: cordic ( f-angle -- f-error f-sine f-cosine ) + ( Angle between -Pi/2 and +Pi/2 ! ) + 0 0 $9B74EDA8 0 + 32 0 do + 2rot dup 0< + if + i e^ka 0 d+ 2rot 2rot + 2over i 2rshift 2rot 2rot + 2swap 2over i 2rshift + d- 2rot 2rot d+ + else + i e^ka 0 d- 2rot 2rot + 2over i 2rshift 2rot 2rot + 2swap 2over i 2rshift + d+ 2rot 2rot 2swap d- + then + loop +2-foldable ; + +: sine ( f-angle -- f-sine ) cordic 2drop 2nip 2-foldable ; +: cosine ( f-angle -- f-cosine ) cordic 2nip 2nip 2-foldable ; + +3,141592653589793 2constant pi +pi 2,0 f/ 2constant pi/2 +pi 4,0 f/ cosine f. \ Displays cos(Pi/4) + +: widecosine ( f-angle -- f-cosine ) + dabs + pi/2 ud/mod drop 3 and ( Quadrant f-angle ) + + case + 0 of cosine endof + 1 of dnegate pi/2 d+ cosine dnegate endof + 2 of cosine dnegate endof + 3 of dnegate pi/2 d+ cosine endof + endcase + + 2-foldable ; + +: widesine ( f-angle -- f-sine ) + dup >r \ Save sign + dabs + pi/2 ud/mod drop 3 and ( Quadrant f-angle ) + + case + 0 of sine endof + 1 of dnegate pi/2 d+ sine endof + 2 of sine dnegate endof + 3 of dnegate pi/2 d+ sine dnegate endof + endcase + + r> 0< if dnegate then + 2-foldable ; + + +here swap - +. \ Mecrisp-Stellaris 2.2.0: 1120 Bytes diff --git a/kl25z128/mecrisp-stellaris-kl25z128.srec b/kl25z128/mecrisp-stellaris-kl25z128.srec index 2ebae42..d549246 100644 --- a/kl25z128/mecrisp-stellaris-kl25z128.srec +++ b/kl25z128/mecrisp-stellaris-kl25z128.srec @@ -1,16 +1,16 @@ S02200006D6563726973702D7374656C6C617269732D6B6C32357A3132382E737265638F -S113000064F3FF1F914B0000994A0000994A0000D5 +S113000064F3FF1F594C0000614B0000614B00007A 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z_S(IX(-gf$8#JRxD1+)Lp?P*vy@GRw+2}>vW+xJmfW~bae(Z7wEJ;iB4C0paa zreD6wvW?ByAt6pzCpm|^`gY2xMOf0)2Q6uhNyrLPr@m_y@fnJVna&Duq6T|d641>9 zJZX$`_YXO}9^?nrqr0u&YfE@HES;ghx8w>>(K$F#N^#o0BG!0#JeHDpd&f{Sfj zSf)LXOWX&z%8bxk+bc5fjofGzkPtj}wYn(5R9&6~?ytbTiT=F3XyKQk{a0BIXSS+M zEKGku-)%4Oy&KwowGouWiCO8ZISuxVG1Qi`%=$ok1JT)M@%+5$>a6tf+^n=COqMLM zS99rE=@Ng+)Dlf$yh)r0OQWIotGZ}CF4TH8EM1y0UOj^nN5;afC1eet-h6mn!Dw%X}IWsr$fR89_c=fjW4$ytnEen0lDq=40^f4{rRhy zyO|pvvHt4iQXRNyE*@7^Zd-)E8GSSa6|#!9B`q7_OI58 zC#>}D)k_5zeRg$K%wbIMB)z&iKYu@JFYt!}74KZ$97%|`ap0_{OV*U<|8Qmw&*Yug wJA1tDK~KeoA!lD75|u&S`c_?aWg{I}b7R7Cc8jfK9`gnL%^J5dehnf22ad" @ ( n - dl dh ) Single --> Double conversion @------------------------------------------------------------------------------ @@ -305,9 +388,13 @@ dnegate: bx lr push {lr} bl dup_allocator - bl alloc_nullkleiner + bl make_tos_changeable + pushdaconstw 0x17C0 @ asrs r0, r0, #31 + bl chsmallplusminus pop {pc} + .ltorg + @------------------------------------------------------------------------------ @ --- Double star and slash --- @------------------------------------------------------------------------------ @@ -369,21 +456,7 @@ alloc_multiplikation_m3: push {lr} bl expect_two_elements bl expect_tos_in_register - - @ Sollte jetzt NOS eine Konstante sein, so wird sie gleich in den richtigen Register geladen. - - ldr r2, [r0, #offset_state_nos] - cmp r2, #constant - bne 5f - pushdatos - ldr tos, [r0, #offset_constant_nos] @ Hole die Konstante ab - bl get_free_register - str r3, [r0, #offset_state_nos] - pushda r3 - movs r2, r3 - bl registerliteralkomma - -5: @ Beide Argumente sind jetzt in Registern. + bl expect_nos_in_register @ Baue den Opcode zusammen: @@ -1116,7 +1189,7 @@ f_star: @ Signed multiply s31.32 pop {pc} @------------------------------------------------------------------------------ - Wortbirne Flag_foldable_4, "d<>" @ ( 1L 1H 2L 2H -- Flag ) + Wortbirne Flag_foldable_4|Flag_allocator, "d<>" @ ( 1L 1H 2L 2H -- Flag ) @------------------------------------------------------------------------------ ldm psp!, {r0, r1, r2} @@ -1130,8 +1203,13 @@ f_star: @ Signed multiply s31.32 bx lr + push {lr} + bl dgleichungleich_common + bl allocator_unequal_zero + pop {pc} + @------------------------------------------------------------------------------ - Wortbirne Flag_foldable_4, "d=" @ ( 1L 1H 2L 2H -- Flag ) + Wortbirne Flag_foldable_4|Flag_allocator, "d=" @ ( 1L 1H 2L 2H -- Flag ) @------------------------------------------------------------------------------ ldm psp!, {r0, r1, r2} @@ -1144,4 +1222,19 @@ f_star: @ Signed multiply s31.32 bx lr + push {lr} + bl dgleichungleich_common + bl allocator_equal_zero + pop {pc} + +dgleichungleich_common: + push {lr} + bl expect_four_elements @ ( 1L 1H 2L 2H ) + bl rot_allocator @ ( 1L 2L 2H 1H ) + bl xor_allocator @ ( 1L 2L H ) + bl minusrot_allocator @ ( H 1L 2L ) + bl xor_allocator @ ( L H ) + bl or_allocator @ ( ? ) + pop {pc} + .ltorg diff --git a/mecrisp-stellaris-source/common/ra/logic.s b/mecrisp-stellaris-source/common/ra/logic.s index d0fd0c0..446be7f 100644 --- a/mecrisp-stellaris-source/common/ra/logic.s +++ b/mecrisp-stellaris-source/common/ra/logic.s @@ -49,6 +49,7 @@ orrs tos, r0 bx lr +or_allocator: pushdaconstw 0x4300 @ orrs r0, r0 b.n alloc_kommutativ @@ -60,6 +61,7 @@ eors tos, r0 bx lr +xor_allocator: pushdaconstw 0x4040 @ eors r0, r0 b.n alloc_kommutativ diff --git a/mecrisp-stellaris-source/common/ra/ra-logic.s b/mecrisp-stellaris-source/common/ra/ra-logic.s index 019d786..ff2ad43 100644 --- a/mecrisp-stellaris-source/common/ra/ra-logic.s +++ b/mecrisp-stellaris-source/common/ra/ra-logic.s @@ -20,6 +20,14 @@ @ Sondereinsprünge, die für Memory Read-Modify-Write und die Schiebebefehle gebraucht werden. +@ ----------------------------------------------------------------------------- +alloc_unkommutativ: +@ ----------------------------------------------------------------------------- + push {r0, r1, r2, r3, lr} +alloc_unkommutativ_ohneregister: + bl expect_two_elements + b.n alloc_logic_gemeinsam + @ ----------------------------------------------------------------------------- alloc_kommutativ: @ ----------------------------------------------------------------------------- @@ -50,6 +58,11 @@ alloc_kommutativ_ohneregister: bl swap_allocator @ Ab jetzt ist es TOS ! 3: + +alloc_logic_gemeinsam: + + bl expect_nos_in_register @ Für den Fall, dass doch zwei Konstanten einlaufen. + .ifndef m0core ldr r1, [r0, #offset_state_tos] @ Prüfe, ob TOS eine Konstante ist. cmp r1, #constant @@ -87,7 +100,12 @@ alloc_kommutativ_ohneregister: b.n m3_opcodieren 5: - + ldr r2, =0x4380 @ bics r0, r0 Opcode + cmp tos, r2 + bne 6f + @ Ja, den Opcode kann ich verlängern und dann einfügen ! + ldr tos, =0xF0300000 @ bics r0, r0, #Imm12 + b.n m3_opcodieren 6: @ Sonderopcodierungen M3/M4 nicht möglich .endif @@ -140,74 +158,4 @@ m3_opcodieren: pop {r0, r1, r2, r3, pc} .endif -@ ----------------------------------------------------------------------------- -alloc_unkommutativ: -@ ----------------------------------------------------------------------------- - push {r0, r1, r2, r3, lr} -alloc_unkommutativ_ohneregister: - bl expect_two_elements - - @ Jetzt sind mindestens zwei Element in den Registern, also TOS und NOS gefüllt. - @ Der Fall, dass beide Konstanten sind tritt nicht auf, weil er von der Faltung bereits erledigt wird. - @ Entweder zwei Register, oder eine Konstante und einen Register. - - .ifndef m0core - ldr r1, [r0, #offset_state_tos] @ Prüfe, ob TOS eine Konstante ist. - cmp r1, #constant - bne 6f - @ TOS ist eine Konstante. - pushdatos - ldr tos, [r0, #offset_constant_tos] - bl twelvebitencoding @ Hole sie und prüfe, ob sie als Imm12 darstellbar ist. - ldmia psp!, {r1} @ Entweder die Bitmaske oder wieder die Konstante - - cmp tos, #0 - drop @ Preserves Flags ! - beq 6f - @ Die Konstante lässt sich als Imm12 darstellen - fein ! Bitmaske liegt in r1 bereit - @ Prüfe nun den Opcode, und ersetze ihn, falls möglich. - - ldr r2, =0x4380 @ bics r0, r0 Opcode - cmp tos, r2 - bne 6f - @ Ja, den Opcode kann ich verlängern und dann einfügen ! - ldr tos, =0xF0300000 @ bics r0, r0, #Imm12 - b.n m3_opcodieren - -6: @ Sonderopcodierungen M3/M4 nicht möglich - .endif - - @ Sorge dafür, dass NOS bereit zum Verändern wird. - bl nos_change_tos_away_later - - bl expect_tos_in_register - - @ Sollte jetzt NOS eine Konstante sein, so wird sie gleich in den richtigen Register geladen. - @ Schließlich trägt NOS nachher das Ergebnis. - - ldr r2, [r0, #offset_state_nos] - cmp r2, #constant - bne 5f - pushdatos - ldr tos, [r0, #offset_constant_nos] @ Hole die Konstante ab - bl get_free_register - str r3, [r0, #offset_state_nos] - pushda r3 - movs r2, r3 - bl registerliteralkomma - -5: @ Beide Argumente sind jetzt in Registern. - - lsls r1, #3 @ Quellregister ist um 3 Stellen geschoben - - @ Baue jetzt den Opcode zusammen: - - orrs tos, r1 - orrs tos, r2 - - bl hkomma - - bl eliminiere_tos - pop {r0, r1, r2, r3, pc} - .ltorg diff --git a/mecrisp-stellaris-source/common/ra/ra-tools.s b/mecrisp-stellaris-source/common/ra/ra-tools.s index 3273428..9b30605 100644 --- a/mecrisp-stellaris-source/common/ra/ra-tools.s +++ b/mecrisp-stellaris-source/common/ra/ra-tools.s @@ -87,34 +87,6 @@ r0_unfrei: bl registerliteralkomma pop {r0, r1, r2, pc} -@ ----------------------------------------------------------------------------- -put_element_in_register: @ Element, welches bearbeitet werden soll, in r3 ankündigen -@ ----------------------------------------------------------------------------- - push {r1, r2, lr} - adds r3, r0 - @ r3: Adresse des Elements - @ r2: Konstante - - ldr r1, [r3] @ Element holen - - cmp r1, #constant - bne 3f - @ Das Element ist eine Konstante. Prüfe, ob sie schon in r0 oder r1 bereitliegt: - ldr r2, [r3, #4] @ Hole die Konstante - - @ Dann generiere sie direkt in den gewünschten Register: - pushda r2 @ Konstante - - movs r1, r3 @ r3 freiräumen - kann vielleicht später noch die Register umsortieren - - bl get_free_register - str r3, [r1] - pushda r3 @ Zielregister - - bl registerliteralkomma - -3:pop {r1, r2, pc} - .ltorg @ ----------------------------------------------------------------------------- @@ -282,6 +254,7 @@ expect_tos_in_register: @ Sorgt dafür, dass TOS auf jeden Fall einem Register l bne 4f ldr r3, [r0, #offset_constant_tos] @ Hole die Konstante ab bl generiere_veraenderliche_konstante + str r3, [r0, #offset_state_tos] movs r1, r3 4: @ Beide Argumente sind jetzt in Registern. @@ -301,6 +274,26 @@ expect_nos_in_register: @ Sorgt dafür, dass NOS auf jeden Fall einem Register l bne 4f ldr r3, [r0, #offset_constant_nos] @ Hole die Konstante ab bl generiere_veraenderliche_konstante + str r3, [r0, #offset_state_nos] + movs r1, r3 + +4: @ Beide Argumente sind jetzt in Registern. + pop {pc} + +@ ----------------------------------------------------------------------------- +expect_3os_in_register: @ Sorgt dafür, dass 3OS auf jeden Fall einem Register liegt, + @ welcher in r1 zurückgegeben wird. +@ ----------------------------------------------------------------------------- + push {lr} + + @ Sollte jetzt 3OS eine Konstante sein, so wird sie geladen. + + ldr r1, [r0, #offset_state_3os] + cmp r1, #constant + bne 4f + ldr r3, [r0, #offset_constant_3os] @ Hole die Konstante ab + bl generiere_veraenderliche_konstante + str r3, [r0, #offset_state_3os] movs r1, r3 4: @ Beide Argumente sind jetzt in Registern. diff --git a/mecrisp-stellaris-source/stm32l152rb/Makefile b/mecrisp-stellaris-source/stm32l152rb/Makefile new file mode 100644 index 0000000..38abcd7 --- /dev/null +++ b/mecrisp-stellaris-source/stm32l152rb/Makefile @@ -0,0 +1,21 @@ + +ARMGNU?=arm-none-eabi + +COPS = -Wall -Os -nostdlib -nostartfiles -ffreestanding -save-temps +AOPS = --warn --fatal-warnings + +all : mecrisp-stellaris-stm32l152rb.bin + +mecrisp-stellaris-stm32l152rb.o : mecrisp-stellaris-stm32l152rb.s + $(ARMGNU)-as mecrisp-stellaris-stm32l152rb.s -o mecrisp-stellaris-stm32l152rb.o + +mecrisp-stellaris-stm32l152rb.bin : memmap mecrisp-stellaris-stm32l152rb.o + $(ARMGNU)-ld -o mecrisp-stellaris-stm32l152rb.elf -T memmap mecrisp-stellaris-stm32l152rb.o + $(ARMGNU)-objdump -D mecrisp-stellaris-stm32l152rb.elf > mecrisp-stellaris-stm32l152rb.list + $(ARMGNU)-objcopy mecrisp-stellaris-stm32l152rb.elf mecrisp-stellaris-stm32l152rb.bin -O binary + +clean: + rm -f *.bin + rm -f *.o + rm -f *.elf + rm -f *.list diff --git a/mecrisp-stellaris-source/stm32l152rb/flash.s b/mecrisp-stellaris-source/stm32l152rb/flash.s new file mode 100644 index 0000000..923a3fc --- /dev/null +++ b/mecrisp-stellaris-source/stm32l152rb/flash.s @@ -0,0 +1,204 @@ +@ +@ Mecrisp-Stellaris - A native code Forth implementation for ARM-Cortex M microcontrollers +@ Copyright (C) 2013 Matthias Koch +@ +@ This program is free software: you can redistribute it and/or modify +@ it under the terms of the GNU General Public License as published by +@ the Free Software Foundation, either version 3 of the License, or +@ (at your option) any later version. +@ +@ This program is distributed in the hope that it will be useful, +@ but WITHOUT ANY WARRANTY; without even the implied warranty of +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +@ GNU General Public License for more details. +@ +@ You should have received a copy of the GNU General Public License +@ along with this program. If not, see . +@ + +@ Schreiben und Löschen des Flash-Speichers im STM32L152. +@ Write and Erase Flash in STM32L152. +@ Porting: Rewrite this ! + +@ This chip has word writes only and very small erasable pages of 256 bytes. +@ One special feature is that erased Flash contains zeros ! + +.equ FLASH_Base, 0x40023C00 + +.equ FLASH_ACR, FLASH_Base + 0x00 @ Flash Access Control Register +.equ FLASH_PECR, FLASH_Base + 0x04 @ Flash +.equ FLASH_PDKEYR, FLASH_Base + 0x08 @ Flash +.equ FLASH_PEKEYR, FLASH_Base + 0x0C @ Flash +.equ FLASH_PRGKEYR, FLASH_Base + 0x10 @ Flash program memory key register +.equ FLASH_OPTKEYR, FLASH_Base + 0x14 @ Flash +.equ FLASH_SR, FLASH_Base + 0x18 @ Flash Status Register +.equ FLASH_OBR, FLASH_Base + 0x1C @ Flash + + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "flash!" @ ( x Addr -- ) + @ Schreibt an die auf 4 gerade Adresse in den Flash. +flashkomma: +@ ----------------------------------------------------------------------------- + popda r0 @ Adresse + popda r1 @ Inhalt. + + @ Ist die gewünschte Stelle im Flash-Dictionary ? Außerhalb des Forth-Kerns ? + ldr r3, =Kernschutzadresse + cmp r0, r3 + blo 5f @ Schreibzugriffe in den Kern ignorieren. + + @ Prüfe die Adresse: Sie muss auf 4 gerade sein: + movs r2, #3 + ands r2, r0 + bne 3f + + @ Prüfe Daten. Schreibe nur, wenn es NICHT 0 ist. + + cmp r1, #0 + beq 2f + + @ Prüfe Inhalt. Muss zum Schreiben 0 enthalten. + + ldr r2, [r0] + cmp r2, #0 + bne 4f + + @ Alles okay, alle Proben bestanden. Kann beginnen, zu schreiben. + + @ Im STM32 ist der Flash-Speicher gespiegelt, die wirkliche Adresse liegt weiter hinten ! + @ Flash memory is mirrored, use true address later for write + adds r0, #0x08000000 + + @ Bereit zum Schreiben ! + + @ Unlock Flash PECR register + + ldr r2, =FLASH_PEKEYR + ldr r3, =0x89ABCDEF + str r3, [r2] + ldr r3, =0x02030405 + str r3, [r2] + + @ Unlock program memory + + ldr r2, =FLASH_PRGKEYR + ldr r3, =0x8C9DAEBF + str r3, [r2] + ldr r3, =0x13141516 + str r3, [r2] + + @ Write to Flash ! No need to set a write bit before. + str r1, [r0] + + @ Wait for Flash BUSY Flag to be cleared + ldr r2, =FLASH_SR + +1: ldr r3, [r2] + ands r3, #1 + bne 1b + + @ Lock Flash after finishing this + ldr r2, =FLASH_PECR + movs r3, #7 + str r3, [r2] + +2:bx lr + +3:Fehler_Quit "Address has to be 4-aligned for writing flash !" +4:Fehler_Quit "Flash location cannot be written twice !" +5:Fehler_Quit "Cannot write into core !" + + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "flashpageerase" @ ( Addr -- ) + @ Löscht einen 256 Bytes großen Flashblock Deletes one 256 Bytes Flash page +flashpageerase: +@ ----------------------------------------------------------------------------- + push {r0, r1, r2, r3, lr} + popda r0 @ Adresse zum Löschen holen Fetch address to erase. + + @ Ist die gewünschte Stelle im Flash-Dictionary ? Außerhalb des Forth-Kerns ? Don't erase Forth core. + ldr r3, =Kernschutzadresse + cmp r0, r3 + blo 2f + + @ Im STM32L152 ist der Flash-Speicher gespiegelt, die wirkliche Adresse liegt weiter hinten ! + @ Flash memory is mirrored, use true address later for write and erase. + adds r0, #0x08000000 + + @ Unlock Flash PECR register + + ldr r2, =FLASH_PEKEYR + ldr r3, =0x89ABCDEF + str r3, [r2] + ldr r3, =0x02030405 + str r3, [r2] + + @ Unlock program memory + + ldr r2, =FLASH_PRGKEYR + ldr r3, =0x8C9DAEBF + str r3, [r2] + ldr r3, =0x13141516 + str r3, [r2] + + @ Set erase mode + + ldr r2, =FLASH_PECR + movs r3, #BIT9+BIT3 @ ERASE + PROG + str r3, [r2] + + @ Select page to erase: + + bics r0, #0xFF @ Write 0 to first word of Program page - mask away lower bits. One page is 64 words = 4*64 Bytes = 256 Bytes long. + movs r2, #0 + str r2, [r0] + + @ Wait for Flash BUSY Flag to be cleared + + ldr r2, =FLASH_SR + +1: ldr r3, [r2] + ands r3, #1 + bne 1b + + @ Lock Flash after finishing this + ldr r2, =FLASH_PECR + movs r3, #7 + str r3, [r2] + + pop {r0, r1, r2, r3, pc} + +2:Fehler_Quit "Cannot erase core !" + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "eraseflash" @ ( -- ) + @ Löscht den gesamten Inhalt des Flashdictionaries. +@ ----------------------------------------------------------------------------- + ldr r0, =FlashDictionaryAnfang +eraseflash_intern: + cpsid i + ldr r1, =FlashDictionaryEnde + +1: ldrh r3, [r0] + cmp r3, #0 + beq 2f + pushda r0 + dup + write "Erase block at " + bl hexdot + writeln " from Flash" + bl flashpageerase +2: adds r0, #2 + cmp r0, r1 + bne 1b + writeln "Finished. Reset !" + b Restart + +@ ----------------------------------------------------------------------------- + Wortbirne Flag_visible, "eraseflashfrom" @ ( Addr -- ) + @ Beginnt an der angegebenen Adresse mit dem Löschen des Dictionaries. +@ ----------------------------------------------------------------------------- + popda r0 + b.n eraseflash_intern diff --git a/mecrisp-stellaris-source/stm32l152rb/interrupts.s b/mecrisp-stellaris-source/stm32l152rb/interrupts.s new file mode 100644 index 0000000..791c7b1 --- /dev/null +++ b/mecrisp-stellaris-source/stm32l152rb/interrupts.s @@ -0,0 +1,38 @@ +@ +@ Mecrisp-Stellaris - A native code Forth implementation for ARM-Cortex M microcontrollers +@ Copyright (C) 2013 Matthias Koch +@ +@ This program is free software: you can redistribute it and/or modify +@ it under the terms of the GNU General Public License as published by +@ the Free Software Foundation, either version 3 of the License, or +@ (at your option) any later version. +@ +@ This program is distributed in the hope that it will be useful, +@ but WITHOUT ANY WARRANTY; without even the implied warranty of +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +@ GNU General Public License for more details. +@ +@ You should have received a copy of the GNU General Public License +@ along with this program. If not, see . +@ + +@ Routinen für die Interrupthandler, die zur Laufzeit neu gesetzt werden können. +@ Code for interrupt handlers that are exchangeable on the fly + +@------------------------------------------------------------------------------ +@ Alle Interrupthandler funktionieren gleich und werden komfortabel mit einem Makro erzeugt: +@ All interrupt handlers work the same way and are generated with a macro: +@------------------------------------------------------------------------------ + +interrupt exti0 +interrupt exti1 +interrupt exti2 +interrupt exti3 +interrupt exti4 +interrupt adc +interrupt dac +interrupt tim2 +interrupt tim3 +interrupt tim4 + +@------------------------------------------------------------------------------ diff --git a/mecrisp-stellaris-source/stm32l152rb/mecrisp-stellaris-stm32l152rb.s b/mecrisp-stellaris-source/stm32l152rb/mecrisp-stellaris-stm32l152rb.s new file mode 100644 index 0000000..3b728a3 --- /dev/null +++ b/mecrisp-stellaris-source/stm32l152rb/mecrisp-stellaris-stm32l152rb.s @@ -0,0 +1,81 @@ +@ +@ Mecrisp-Stellaris - A native code Forth implementation for ARM-Cortex M microcontrollers +@ Copyright (C) 2013 Matthias Koch +@ +@ This program is free software: you can redistribute it and/or modify +@ it under the terms of the GNU General Public License as published by +@ the Free Software Foundation, either version 3 of the License, or +@ (at your option) any later version. +@ +@ This program is distributed in the hope that it will be useful, +@ but WITHOUT ANY WARRANTY; without even the implied warranty of +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +@ GNU General Public License for more details. +@ +@ You should have received a copy of the GNU General Public License +@ along with this program. If not, see . +@ + +.syntax unified +.cpu cortex-m3 +.thumb + +@ ----------------------------------------------------------------------------- +@ Swiches for capabilities of this chip +@ ----------------------------------------------------------------------------- + +.equ erasedflashcontainszero, 1 +.equ emulated16bitflashwrites, 1 +@ Not available: .equ charkommaavailable, 1 + +@ ----------------------------------------------------------------------------- +@ Start with some essential macro definitions +@ ----------------------------------------------------------------------------- + +.include "../common/datastackandmacros.s" + +@ ----------------------------------------------------------------------------- +@ Speicherkarte für Flash und RAM +@ Memory map for Flash and RAM +@ ----------------------------------------------------------------------------- + +@ Konstanten für die Größe des Ram-Speichers + +.equ RamAnfang, 0x20000000 @ Start of RAM Porting: Change this ! +.equ RamEnde, 0x20004000 @ End of RAM. 16 kb. Porting: Change this ! + +@ Konstanten für die Größe und Aufteilung des Flash-Speichers + +.equ Kernschutzadresse, 0x00004000 @ Darunter wird niemals etwas geschrieben ! Mecrisp core never writes flash below this address. +.equ FlashDictionaryAnfang, 0x00004000 @ 16 kb für den Kern reserviert... 16 kb Flash reserved for core. +.equ FlashDictionaryEnde, 0x00020000 @ 128 kb Platz für das Flash-Dictionary 128 kb Flash available. Porting: Change this ! +.equ Backlinkgrenze, RamAnfang @ Ab dem Ram-Start. + + +@ ----------------------------------------------------------------------------- +@ Anfang im Flash - Interruptvektortabelle ganz zu Beginn +@ Flash start - Vector table has to be placed here +@ ----------------------------------------------------------------------------- +.text @ Hier beginnt das Vergnügen mit der Stackadresse und der Einsprungadresse +.include "vectors.s" @ You have to change vectors for Porting ! + +@ ----------------------------------------------------------------------------- +@ Include the Forth core of Mecrisp-Stellaris +@ ----------------------------------------------------------------------------- + +.include "../common/forth-core.s" + +@ ----------------------------------------------------------------------------- +Reset: @ Einsprung zu Beginn +@ ----------------------------------------------------------------------------- + @ Initialisierungen der Hardware, habe und brauche noch keinen Datenstack dafür + @ Initialisations for Terminal hardware, without Datastack. + bl uart_init + + @ Catch the pointers for Flash dictionary + .include "../common/catchflashpointers.s" + + welcome " for STM32L152RB by Matthias Koch" + + @ Ready to fly ! + .include "../common/boot.s" diff --git a/mecrisp-stellaris-source/stm32l152rb/memmap b/mecrisp-stellaris-source/stm32l152rb/memmap new file mode 100644 index 0000000..445dc8a --- /dev/null +++ b/mecrisp-stellaris-source/stm32l152rb/memmap @@ -0,0 +1,13 @@ + +MEMORY +{ + rom(RX) : ORIGIN = 0x00000000, LENGTH = 0x4000 + ram(WAIL) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + +SECTIONS +{ + .text : { *(.text*) } > rom + .bss : { *(.bss*) } > ram +} + diff --git a/mecrisp-stellaris-source/stm32l152rb/terminal.s b/mecrisp-stellaris-source/stm32l152rb/terminal.s new file mode 100644 index 0000000..70de9f1 --- /dev/null +++ b/mecrisp-stellaris-source/stm32l152rb/terminal.s @@ -0,0 +1,105 @@ +@ +@ Mecrisp-Stellaris - A native code Forth implementation for ARM-Cortex M microcontrollers +@ Copyright (C) 2013 Matthias Koch +@ +@ This program is free software: you can redistribute it and/or modify +@ it under the terms of the GNU General Public License as published by +@ the Free Software Foundation, either version 3 of the License, or +@ (at your option) any later version. +@ +@ This program is distributed in the hope that it will be useful, +@ but WITHOUT ANY WARRANTY; without even the implied warranty of +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +@ GNU General Public License for more details. +@ +@ You should have received a copy of the GNU General Public License +@ along with this program. If not, see . +@ + +@ Terminalroutinen +@ Terminal code and initialisations. +@ Porting: Rewrite this ! + + .equ GPIOA_BASE , 0x40020000 + .equ GPIOA_MODER , GPIOA_BASE + 0x00 + .equ GPIOA_OTYPER , GPIOA_BASE + 0x04 + .equ GPIOA_OSPEEDR , GPIOA_BASE + 0x08 + .equ GPIOA_PUPDR , GPIOA_BASE + 0x0C + .equ GPIOA_IDR , GPIOA_BASE + 0x10 + .equ GPIOA_ODR , GPIOA_BASE + 0x14 + .equ GPIOA_BSRR , GPIOA_BASE + 0x18 + .equ GPIOA_LCKR , GPIOA_BASE + 0x1C + .equ GPIOA_AFRL , GPIOA_BASE + 0x20 + .equ GPIOA_AFRH , GPIOA_BASE + 0x24 + + .equ RCC_BASE , 0x40023800 + .equ RCC_CR , RCC_BASE + 0x00 + .equ RCC_CFGR , RCC_BASE + 0x08 + .equ RCC_AHBENR , RCC_BASE + 0x1C + .equ RCC_APB1ENR , RCC_BASE + 0x20 + .equ RCC_APB1ENR , RCC_BASE + 0x24 + + .equ PWR_BASE , 0x40007000 + .equ PWR_CR , PWR_BASE + 0x00 + .equ PWR_CSR , PWR_BASE + 0x04 + + .equ Terminal_USART_Base, 0x40004400 @ USART 2 + .include "../common/stm-terminal.s" @ Common STM terminal code for emit, key and key? + +@ ----------------------------------------------------------------------------- +uart_init: @ ( -- ) +@ ----------------------------------------------------------------------------- + + @ Switch internal voltage regulator to high-performance "Range 1" + ldr r1, =PWR_CR + movs r0, #BIT11 + str r0, [r1] + + @ Select 16 MHz HSI clock instead of MSI which is boot default + ldr r1, =RCC_CR + movs r0, #1 @ HSI on + str r0, [r1] + +1:ldr r0, [r1] @ Check HSIRDY flag + ands r0, #2 + beq 1b + + ldr r1, =RCC_CFGR + movs r0, #1 @ HSI as system clock source + str r0, [r1] + + @ Enable all GPIO peripheral clock + ldr r1, = RCC_AHBENR + ldr r0, = 0x80FF @ FLITFEN and all GPIO clocks + str r0, [r1] + + @ Enable the USART2 peripheral clock by setting bit 17 + ldr r1, = RCC_APB1ENR + ldr r0, = BIT17 + str r0, [r1] + + @ Set PORTA pins in alternate function mode + ldr r1, = GPIOA_MODER + ldr r0, [r1] + orrs r0, #0xA0 + str r0, [r1] + + @ Set alternate function 7 to enable USART2 pins on Port A + ldr r1, = GPIOA_AFRL + ldr r0, = 0x7700 @ Alternate function 7 for TX and RX pins of USART2 on PORTA + str r0, [r1] + + @ Configure BRR by deviding the bus clock with the baud rate + + ldr r1, =Terminal_USART_BRR + movs r0, #0x8B @ 115200 bps at 16 MHz + str r0, [r1] + + @ Enable the USART, TX, and RX circuit + ldr r1, =Terminal_USART_CR1 + ldr r0, =BIT13+BIT3+BIT2 @ USART_CR1_UE | USART_CR1_TE | USART_CR1_RE + str r0, [r1] + + bx lr + + .ltorg @ Hier werden viele spezielle Hardwarestellenkonstanten gebraucht, schreibe sie gleich ! diff --git a/mecrisp-stellaris-source/stm32l152rb/vectors.s b/mecrisp-stellaris-source/stm32l152rb/vectors.s new file mode 100644 index 0000000..c7e7646 --- /dev/null +++ b/mecrisp-stellaris-source/stm32l152rb/vectors.s @@ -0,0 +1,86 @@ +@ +@ Mecrisp-Stellaris - A native code Forth implementation for ARM-Cortex M microcontrollers +@ Copyright (C) 2013 Matthias Koch +@ +@ This program is free software: you can redistribute it and/or modify +@ it under the terms of the GNU General Public License as published by +@ the Free Software Foundation, either version 3 of the License, or +@ (at your option) any later version. +@ +@ This program is distributed in the hope that it will be useful, +@ but WITHOUT ANY WARRANTY; without even the implied warranty of +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +@ GNU General Public License for more details. +@ +@ You should have received a copy of the GNU General Public License +@ along with this program. If not, see . +@ + +@ ----------------------------------------------------------------------------- +@ Interruptvektortabelle +@ ----------------------------------------------------------------------------- + +.include "../common/vectors-common.s" + +@ Special interrupt handlers for this particular chip: + +.word nullhandler+1 @ Position 0: Window Watchdog +.word nullhandler+1 @ Position 1: PVD through EXTI line detection +.word nullhandler+1 @ Position 2: Tamper and TimeStamp through EXTI line +.word nullhandler+1 @ Position 3: RTC Wakeup +.word nullhandler+1 @ Position 4: Flash +.word nullhandler+1 @ Position 5: RCC +.word irq_vektor_exti0+1 @ Position 6: EXTI Line 0 +.word irq_vektor_exti1+1 @ Position 7: EXTI Line 1 +.word irq_vektor_exti2+1 @ Position 8: EXTI Line 2 +.word irq_vektor_exti3+1 @ Position 9: EXTI Line 3 +.word irq_vektor_exti4+1 @ Position 10: EXTI Line 4 +.word nullhandler+1 @ Position 11: DMA1 Stream 0 +.word nullhandler+1 @ Position 12: DMA1 Stream 1 +.word nullhandler+1 @ Position 13: DMA1 Stream 2 +.word nullhandler+1 @ Position 14: DMA1 Stream 3 +.word nullhandler+1 @ Position 15: DMA1 Stream 4 +.word nullhandler+1 @ Position 16: DMA1 Stream 5 +.word nullhandler+1 @ Position 17: DMA1 Stream 6 +.word irq_vektor_adc+1 @ Position 18: ADC global interrupts +.word nullhandler+1 @ Position 19: +.word nullhandler+1 @ Position 20: +.word irq_vektor_dac+1 @ Position 21: DAC interrupt +.word nullhandler+1 @ Position 21: +.word nullhandler+1 @ Position 22: +.word nullhandler+1 @ Position 23: +.word nullhandler+1 @ Position 24: +.word nullhandler+1 @ Position 25: +.word nullhandler+1 @ Position 26: +.word nullhandler+1 @ Position 27: +.word irq_vektor_tim2+1 @ Position 28: TIM2 +.word irq_vektor_tim3+1 @ Position 29: TIM3 +.word irq_vektor_tim4+1 @ Position 30: TIM4 +.word nullhandler+1 @ Position 31: +.word nullhandler+1 @ Position 32: +.word nullhandler+1 @ Position 33: +.word nullhandler+1 @ Position 34: +.word nullhandler+1 @ Position 35: +.word nullhandler+1 @ Position 36: +.word nullhandler+1 @ Position 37: +.word nullhandler+1 @ Position 38: +.word nullhandler+1 @ Position 39: +.word nullhandler+1 @ Position 40: +.word nullhandler+1 @ Position 41: +.word nullhandler+1 @ Position 42: +.word nullhandler+1 @ Position 43: +.word nullhandler+1 @ Position 44: +.word nullhandler+1 @ Position 45: +.word nullhandler+1 @ Position 46: +.word nullhandler+1 @ Position 47: +.word nullhandler+1 @ Position 48: +.word nullhandler+1 @ Position 49: +.word nullhandler+1 @ Position 50: +.word nullhandler+1 @ Position 51: +.word nullhandler+1 @ Position 52: +.word nullhandler+1 @ Position 53: +.word nullhandler+1 @ Position 54: +.word nullhandler+1 @ Position 55: +.word nullhandler+1 @ Position 56: + +@ ----------------------------------------------------------------------------- diff --git a/mecrisp-stellaris-source/tidyup b/mecrisp-stellaris-source/tidyup index 1483cbb..31832ff 100644 --- a/mecrisp-stellaris-source/tidyup +++ b/mecrisp-stellaris-source/tidyup @@ -68,6 +68,10 @@ cd stm32l152 make clean cd .. +cd stm32l152rb +make clean +cd .. + cd stm32f100 make clean cd .. diff --git a/stm32l152rb/blinky.txt b/stm32l152rb/blinky.txt new file mode 100644 index 0000000..3293d9d --- /dev/null +++ b/stm32l152rb/blinky.txt @@ -0,0 +1,18 @@ +\ adapted to STM32L-DISCOVERY +\ buton - pa0 +\ led3 - pb6 +\ led4 - pb7 + +: button? ( -- ? ) 1 0 lshift gpioa_idr bit@ not ; +: led ( ? -- ) if 1 6 lshift gpiob_bsrr ! else 1 6 lshift 16 lshift gpiob_bsrr ! then ; + +: blinky ( -- ) + + %01 6 2* lshift gpiob_moder bis! \ Set LED Pin mode to output + + begin + button? if true led 500000 0 do loop false led 500000 0 do loop + else true led 1000000 0 do loop false led 1000000 0 do loop + then + key? until +; \ No newline at end of file diff --git a/stm32l152rb/mecrisp-stellaris-stm32l152rb.bin b/stm32l152rb/mecrisp-stellaris-stm32l152rb.bin new file mode 100644 index 0000000000000000000000000000000000000000..edf60fb7c5f5f7b51a1ffc064d8d77709f5fb146 GIT binary patch literal 15004 zcmb_@dw5&LweRe$hh@dFm6zi@2s=&?e#DOK1jkN{y)C7d?1UsFkkdAyNVeoi#Fm6C zCl2ie0cq;A914_^(-O+%@a6P!TWCXS=Z0WGN;y5ig<4KpnnD24(x`_*QPN=f5o@2{ znk^~G?Y-aq=lJ`^duFXQYu1|ATC-+k(J*OV17j=K{C#5o$KM^Gp+tZ5&C8Ut@TJQ7f>3slyKw$|MjWc6PAxVA^zT<;9p`vLEW=xW`eKv26z z9tqkH0kR&D-o371-Uv~t)N7rEENK5Rr`Oi{eL<#TgZ9@lH3EA)p%XdYX>ZW}=L{y? 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DAC $14 + constant DAC_DHR12R2 + DAC $18 + constant DAC_DHR12L2 + DAC $1C + constant DAC_DHR8R2 + DAC $20 + constant DAC_DHR12RD + DAC $24 + constant DAC_DHR12LD + DAC $28 + constant DAC_DHR8RD + DAC $2C + constant DAC_DOR1 + DAC $30 + constant DAC_DOR2 + DAC $34 + constant DAC_SR + + + $40026000 constant DMA1 + DMA1 $0 + constant DMA1_ISR + DMA1 $4 + constant DMA1_IFCR + DMA1 $8 + constant DMA1_CCR1 + DMA1 $C + constant DMA1_CNDTR1 + DMA1 $10 + constant DMA1_CPAR1 + DMA1 $14 + constant DMA1_CMAR1 + DMA1 $1C + constant DMA1_CCR2 + DMA1 $20 + constant DMA1_CNDTR2 + DMA1 $24 + constant DMA1_CPAR2 + DMA1 $28 + constant DMA1_CMAR2 + DMA1 $30 + constant DMA1_CCR3 + DMA1 $34 + constant DMA1_CNDTR3 + DMA1 $38 + constant DMA1_CPAR3 + DMA1 $3C + constant DMA1_CMAR3 + DMA1 $44 + constant DMA1_CCR4 + DMA1 $48 + constant DMA1_CNDTR4 + DMA1 $4C + constant DMA1_CPAR4 + DMA1 $50 + constant DMA1_CMAR4 + DMA1 $58 + constant DMA1_CCR5 + DMA1 $5C + constant DMA1_CNDTR5 + DMA1 $60 + constant DMA1_CPAR5 + DMA1 $64 + constant DMA1_CMAR5 + DMA1 $6C + constant DMA1_CCR6 + DMA1 $70 + constant DMA1_CNDTR6 + DMA1 $74 + constant DMA1_CPAR6 + DMA1 $78 + constant DMA1_CMAR6 + DMA1 $80 + constant DMA1_CCR7 + DMA1 $84 + constant DMA1_CNDTR7 + DMA1 $88 + constant DMA1_CPAR7 + DMA1 $8C + constant DMA1_CMAR7 + + + $40010400 constant EXTI + EXTI $0 + constant EXTI_IMR + EXTI $4 + constant EXTI_EMR + EXTI $8 + constant EXTI_RTSR + EXTI $C + constant EXTI_FTSR + EXTI $10 + constant EXTI_SWIER + EXTI $14 + constant EXTI_PR + + + $40023C00 constant Flash + Flash $0 + constant Flash_ACR + Flash $4 + constant Flash_PECR + Flash $8 + constant Flash_PDKEYR + Flash $C + constant Flash_PEKEYR + Flash $10 + constant Flash_PRGKEYR + Flash $14 + constant Flash_OPTKEYR + Flash $18 + constant Flash_SR + Flash $1C + constant Flash_OBR + Flash $20 + constant Flash_WRPR1 + Flash $80 + constant Flash_WRPR2 + Flash $84 + constant Flash_WRPR3 + + + $40020000 constant GPIOA + GPIOA $0 + constant GPIOA_MODER + GPIOA $4 + constant GPIOA_OTYPER + GPIOA $8 + constant GPIOA_OSPEEDER + GPIOA $C + constant GPIOA_PUPDR + GPIOA $10 + constant GPIOA_IDR + GPIOA $14 + constant GPIOA_ODR + GPIOA $18 + constant GPIOA_BSRR + GPIOA $1C + constant GPIOA_LCKR + GPIOA $20 + constant GPIOA_AFRL + GPIOA $24 + constant GPIOA_AFRH + + + $40020400 constant GPIOB + GPIOB $0 + constant GPIOB_MODER + GPIOB $4 + constant GPIOB_OTYPER + GPIOB $8 + constant GPIOB_OSPEEDER + GPIOB $C + constant GPIOB_PUPDR + GPIOB $10 + constant GPIOB_IDR + GPIOB $14 + constant GPIOB_ODR + GPIOB $18 + constant GPIOB_BSRR + GPIOB $1C + constant GPIOB_LCKR + GPIOB $20 + constant GPIOB_AFRL + GPIOB $24 + constant GPIOB_AFRH + + + $40020800 constant GPIOC + GPIOC $0 + constant GPIOC_MODER + GPIOC $4 + constant GPIOC_OTYPER + GPIOC $8 + constant GPIOC_OSPEEDER + GPIOC $C + constant GPIOC_PUPDR + GPIOC $10 + constant GPIOC_IDR + GPIOC $14 + constant GPIOC_ODR + GPIOC $18 + constant GPIOC_BSRR + GPIOC $1C + constant GPIOC_LCKR + GPIOC $20 + constant GPIOC_AFRL + GPIOC $24 + constant GPIOC_AFRH + + + $40020C00 constant GPIOD + + + $40021000 constant GPIOE + + + $40021400 constant GPIOH + + + $40005400 constant I2C1 + I2C1 $0 + constant I2C1_CR1 + I2C1 $4 + constant I2C1_CR2 + I2C1 $8 + constant I2C1_OAR1 + I2C1 $C + constant I2C1_OAR2 + I2C1 $10 + constant I2C1_DR + I2C1 $14 + constant I2C1_SR1 + I2C1 $18 + constant I2C1_SR2 + I2C1 $1C + constant I2C1_CCR + I2C1 $20 + constant I2C1_TRISE + + + $40005800 constant I2C2 + + + $40003000 constant IWDG + IWDG $0 + constant IWDG_KR + IWDG $4 + constant IWDG_PR + IWDG $8 + constant IWDG_RLR + IWDG $C + constant IWDG_SR + + + $40002400 constant LCD + LCD $0 + constant LCD_CR + LCD $4 + constant LCD_FCR + LCD $8 + constant LCD_SR + LCD $C + constant LCD_CLR + LCD $14 + constant LCD_RAM_COM0 + LCD $1C + constant LCD_RAM_COM1 + LCD $24 + constant LCD_RAM_COM2 + LCD $2C + constant LCD_RAM_COM3 + LCD $34 + constant LCD_RAM_COM4 + LCD $3C + constant LCD_RAM_COM5 + LCD $44 + constant LCD_RAM_COM6 + LCD $4C + constant LCD_RAM_COM7 + + + $40007000 constant PWR + PWR $0 + constant PWR_CR + PWR $4 + constant PWR_CSR + + + $40023800 constant RCC + RCC $0 + constant RCC_CR + RCC $4 + constant RCC_ICSCR + RCC $8 + constant RCC_CFGR + RCC $C + constant RCC_CIR + RCC $10 + constant RCC_AHBRSTR + RCC $14 + constant RCC_APB2RSTR + RCC $18 + constant RCC_APB1RSTR + RCC $1C + constant RCC_AHBENR + RCC $20 + constant RCC_APB2ENR + RCC $24 + constant RCC_APB1ENR + RCC $28 + constant RCC_AHBLPENR + RCC $2C + constant RCC_APB2LPENR + RCC $30 + constant RCC_APB1LPENR + RCC $34 + constant RCC_CSR + + + $40007C04 constant RI + RI $0 + constant RI_ICR + RI $4 + constant RI_ASCR1 + RI $8 + constant RI_ASCR2 + RI $C + constant RI_HYSCR1 + RI $10 + constant RI_HYSCR2 + RI $14 + constant RI_HYSCR3 + RI $18 + constant RI_HYSCR4 + RI $1C + constant RI_ASMR1 + RI $20 + constant RI_CMR1 + RI $24 + constant RI_CICR1 + RI $28 + constant RI_ASMR2 + RI $2C + constant RI_CMR2 + RI $30 + constant RI_CICR2 + RI $34 + constant RI_ASMR3 + RI $38 + constant RI_CMR3 + RI $3C + constant RI_CICR3 + RI $40 + constant RI_ASMR4 + RI $44 + constant RI_CMR4 + RI $48 + constant RI_CICR4 + RI $4C + constant RI_ASMR5 + RI $50 + constant RI_CMR5 + RI $54 + constant RI_CICR5 + + + $40002800 constant RTC + RTC $0 + constant RTC_TR + RTC $4 + constant RTC_DR + RTC $8 + constant RTC_CR + RTC $C + constant RTC_ISR + RTC $10 + constant RTC_PRER + RTC $14 + constant RTC_WUTR + RTC $18 + constant RTC_CALIBR + RTC $1C + constant RTC_ALRMAR + RTC $20 + constant RTC_ALRMBR + RTC $24 + constant RTC_WPR + RTC $28 + constant RTC_SSR + RTC $2C + constant RTC_SHIFTR + RTC $30 + constant RTC_TSTR + RTC $34 + constant RTC_TSDR + RTC $38 + constant RTC_TSSSR + RTC $3C + constant RTC_CALR + RTC $40 + constant RTC_TAFCR + RTC $44 + constant RTC_ALRMASSR + RTC $48 + constant RTC_ALRMBSSR + RTC $50 + constant RTC_BKP0R + RTC $54 + constant RTC_BKP1R + RTC $58 + constant RTC_BKP2R + RTC $5C + constant RTC_BKP3R + RTC $60 + constant RTC_BKP4R + RTC $64 + constant RTC_BKP5R + RTC $68 + constant RTC_BKP6R + RTC $6C + constant RTC_BKP7R + RTC $70 + constant RTC_BKP8R + RTC $74 + constant RTC_BKP9R + RTC $78 + constant RTC_BKP10R + RTC $7C + constant RTC_BKP11R + RTC $80 + constant RTC_BKP12R + RTC $84 + constant RTC_BKP13R + RTC $88 + constant RTC_BKP14R + RTC $8C + constant RTC_BKP15R + RTC $90 + constant RTC_BKP16R + RTC $94 + constant RTC_BKP17R + RTC $98 + constant RTC_BKP18R + RTC $9C + constant RTC_BKP19R + RTC $A0 + constant RTC_BKP20R + RTC $A4 + constant RTC_BKP21R + RTC $A8 + constant RTC_BKP22R + RTC $AC + constant RTC_BKP23R + RTC $B0 + constant RTC_BKP24R + RTC $B4 + constant RTC_BKP25R + RTC $B8 + constant RTC_BKP26R + RTC $BC + constant RTC_BKP27R + RTC $C0 + constant RTC_BKP28R + RTC $C4 + constant RTC_BKP29R + RTC $C8 + constant RTC_BKP30R + RTC $CC + constant RTC_BKP31R + + + $40013000 constant SPI1 + SPI1 $0 + constant SPI1_CR1 + SPI1 $4 + constant SPI1_CR2 + SPI1 $8 + constant SPI1_SR + SPI1 $C + constant SPI1_DR + SPI1 $10 + constant SPI1_CRCPR + SPI1 $14 + constant SPI1_RXCRCR + SPI1 $18 + constant SPI1_TXCRCR + SPI1 $1C + constant SPI1_I2SCFGR + SPI1 $20 + constant SPI1_I2SPR + + + $40003800 constant SPI2 + + + $40010000 constant SYSCFG + SYSCFG $0 + constant SYSCFG_MEMRMP + SYSCFG $4 + constant SYSCFG_PMC + SYSCFG $8 + constant SYSCFG_EXTICR1 + SYSCFG $C + constant SYSCFG_EXTICR2 + SYSCFG $10 + constant SYSCFG_EXTICR3 + SYSCFG $14 + constant SYSCFG_EXTICR4 + + + $40010C00 constant TIM10 + TIM10 $0 + constant TIM10_CR1 + TIM10 $C + constant TIM10_DIER + TIM10 $10 + constant TIM10_SR + TIM10 $14 + constant TIM10_EGR + TIM10 $18 + constant TIM10_CCMR1_Output + TIM10 $18 + constant TIM10_CCMR1_Input + TIM10 $20 + constant TIM10_CCER + TIM10 $24 + constant TIM10_CNT + TIM10 $28 + constant TIM10_PSC + TIM10 $2C + constant TIM10_ARR + TIM10 $34 + constant TIM10_CCR1 + TIM10 $50 + constant TIM10_OR + + + $40011000 constant TIM11 + + + $40000000 constant TIM2 + TIM2 $0 + constant TIM2_CR1 + TIM2 $4 + constant TIM2_CR2 + TIM2 $8 + constant TIM2_SMCR + TIM2 $C + constant TIM2_DIER + TIM2 $10 + constant TIM2_SR + TIM2 $14 + constant TIM2_EGR + TIM2 $18 + constant TIM2_CCMR1_Output + TIM2 $18 + constant TIM2_CCMR1_Input + TIM2 $1C + constant TIM2_CCMR2_Output + TIM2 $1C + constant TIM2_CCMR2_Input + TIM2 $20 + constant TIM2_CCER + TIM2 $24 + constant TIM2_CNT + TIM2 $28 + constant TIM2_PSC + TIM2 $2C + constant TIM2_ARR + TIM2 $34 + constant TIM2_CCR1 + TIM2 $38 + constant TIM2_CCR2 + TIM2 $3C + constant TIM2_CCR3 + TIM2 $40 + constant TIM2_CCR4 + TIM2 $48 + constant TIM2_DCR + TIM2 $4C + constant TIM2_DMAR + + + $40000400 constant TIM3 + + + $40000800 constant TIM4 + + + $40001000 constant TIM6 + TIM6 $0 + constant TIM6_CR1 + TIM6 $4 + constant TIM6_CR2 + TIM6 $C + constant TIM6_DIER + TIM6 $10 + constant TIM6_SR + TIM6 $14 + constant TIM6_EGR + TIM6 $24 + constant TIM6_CNT + TIM6 $28 + constant TIM6_PSC + TIM6 $2C + constant TIM6_ARR + + + $40001400 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