[QUESTION] endianness on arm (again)

[DenisYaroshevskiy]

Fron gcc's neon strlen

#ifdef __AARCH64EB__
--
/* Big-endian.  Early bytes are at MSB.  */
lsr        tmp1, tmp4, tmp1
lsr        tmp2, tmp4, tmp2
#else
/* Little-endian.  Early bytes are at LSB.  */
lsl        tmp1, tmp4, tmp1
lsl        tmp2, tmp4, tmp2
#endif

Full code: https://code.woboq.org/userspace/glibc/sysdeps/aarch64/multiarch/strlen_asimd.S.html

Can't say I understand what they are doing, but are we sure we don't care?

Also, from simd-everywhere comments:
https://github.com/simd-everywhere/simde/blob/12069d720f43830ae9791e8b0f4c4fa3c88012a0/simde/x86/sse2.h#L3626-L3630
Also the code is the same and they seem to indicate that the bits would be properly reversed.

[jfalcou]

Yes, there are two flavors of ARM concerning endianness, we should support both.
This also means more CI instances.

[DenisYaroshevskiy]

This also means more CI instances.

Nooooooo