From 46404b05348dec487e5275df4fee90e6819637e4 Mon Sep 17 00:00:00 2001 From: Umer Uddin Date: Thu, 31 Oct 2024 21:14:54 +0000 Subject: [PATCH] x1s: Bringup VQMMC via speedy Also adds some regs for S2MPS_19 for all 990 platforms as they all use S2MPS_19. Signed-off-by: Umer Uddin --- board/samsung/board-x1s.c | 55 ++++++++++++++++++++++++++++++++++++--- include/soc/exynos990.h | 14 ++++++++++ 2 files changed, 66 insertions(+), 3 deletions(-) diff --git a/board/samsung/board-x1s.c b/board/samsung/board-x1s.c index ecf09a83..7201e020 100644 --- a/board/samsung/board-x1s.c +++ b/board/samsung/board-x1s.c @@ -6,9 +6,9 @@ #include #include #include - -#define DECON_F_BASE 0x19050000 -#define HW_SW_TRIG_CONTROL 0x70 +#include +#include +#include void init_board_funcs(void *board) { @@ -24,6 +24,53 @@ void init_board_funcs(void *board) board_restruct->name = "X1S"; } +struct s2mps19_data { + uint32_t ldo_address; +}; + +static void s2mps19_setup(void) +{ + int ret; + struct speedy_transaction s2mps19; + + /* S2MPS19 configuration */ + s2mps19.base = SPEEDY_0_BASE; + s2mps19.slave = S2MPS19_PM_ADDR; + + /* + * Define LDO control register values + * Values have been borrowed from Linaro's LK + */ + const struct s2mps19_data data[] = { + { + S2MPS19_PM_LDO2M_CTRL + }, { + S2MPS19_PM_LDO15M_CTRL + } + }; + + /* Configure LDOs */ + for (int i = 0; i < 3; i++) { + s2mps19.offset = data[i].ldo_address; + + ret = speedy_read(&s2mps19); + if (ret) + goto handle_err; + + s2mps19.val |= S2MPS_OUTPUT_ON_NORMAL; + + ret = speedy_write(&s2mps19); + if (ret) + goto handle_err; + } + + return; + +handle_err: + printk(KERN_ERR, "s2mps19: err\n"); + return; +} + // Early initialization int board_init(void) { @@ -35,6 +82,8 @@ int board_init(void) // Late initialization int board_late_init(void) { + s2mps19_setup(); + return 0; } diff --git a/include/soc/exynos990.h b/include/soc/exynos990.h index a91ea55a..7a0167a5 100644 --- a/include/soc/exynos990.h +++ b/include/soc/exynos990.h @@ -9,4 +9,18 @@ #define DECON_F_BASE 0x19050000 #define HW_SW_TRIG_CONTROL 0x70 +#define SPEEDY_0_BASE 0x15940000 + +/* All exynos990 devices use S2MPS_19_22 */ + +/* S2MPS19 slave address */ +#define S2MPS19_PM_ADDR 0x1 + +/* S2MPS19 Register Address */ +#define S2MPS19_PM_LDO2M_CTRL 0x047 +#define S2MPS19_PM_LDO15M_CTRL 0x054 + +/* LDOx_CTRL */ +#define S2MPS_OUTPUT_ON_NORMAL (0x3 << 6) + #endif // EXYNOS990_H_