CPU.stx

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to F:/Desktop/FPGA/ninth_experiment/xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
 
--> Parameter xsthdpdir set to F:/Desktop/FPGA/ninth_experiment/xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
 
--> Reading design: CPU.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "F:\Desktop\FPGA\ninth_experiment\ipcore_dir\Inst_Rom.v" into library work
Parsing module <Inst_Rom>.
Analyzing Verilog file "F:\Desktop\FPGA\Third_experiment\Third_experiment_first.v" into library work
Parsing module <Third_experiment_first>.
Analyzing Verilog file "F:\Desktop\FPGA\ninth_experiment\PC.v" into library work
Parsing module <PC>.
Analyzing Verilog file "F:\Desktop\FPGA\ninth_experiment\OP_Func.v" into library work
Parsing module <OP_Func>.
Analyzing Verilog file "F:\Desktop\FPGA\ninth_experiment\ipcore_dir\RAM.v" into library work
Parsing module <RAM>.
Analyzing Verilog file "F:\Desktop\FPGA\ninth_experiment\Fourth_experiment_first.v" into library work
Parsing module <Fourth_experiment_first>.
Analyzing Verilog file "F:\Desktop\FPGA\ninth_experiment\CPU.v" into library work
Parsing module <CPU>.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.19 secs
 
--> 

Total memory usage is 4455604 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)