Yosys going belly up for OPL3 System Verilog

[chili-chips-ba]

Hi Guys, as we are porting your design to CologneChip GateMate FPGA, we ran into issues with Yosys and SV.

• Any tips and insights you can offer on that subject?

@DadoCCAG, @TarikHamedovic for awareness.

[gtaylormb]

See my comment here: chili-chips-ba/openCologne#3 (comment)

But more in general, if you run into other syntax issues (it appears Yosys doesn't like package imports), I'd push to get these fixes into Yosys as this is your only option for synthesis.

Very cool project by the way!