From 324d4a0e8c183366dbdcda3ef2e8de1e5145be56 Mon Sep 17 00:00:00 2001
From: Greg Taylor <gtaylor@sonic.net>
Date: Sat, 27 Apr 2024 11:20:49 -0400
Subject: [PATCH] Update README.md

---
 README.md | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/README.md b/README.md
index f6d775d..7364aef 100755
--- a/README.md
+++ b/README.md
@@ -1,6 +1,9 @@
 opl3_fpga
 =========
 ## News
+2024-4-27
+* OPL3_FPGA has been merged into https://github.com/MiSTer-devel/ao486_MiSTer and replaced the old Z80-based OPL3 core!
+
 2024-4-10
 * Massive refactoring. I changed up the top level interface/bus protocol to better match the real chip and make it easier to integrate into other projects. The register map is now internal instead of an external AXI version. Clock domain
 crossing logic is included to go between CPU and OPL3. This along with significant internal logic reduction work has massively cut down the area. LUT utilization was reduced by 78%, registers by 89%.