Envelope fixes, confident of bit widths now and overflow conditions (#38

) * register phase_inc rom * confident of bit width in envelope now
gtaylormb · Apr 25, 2024 · 0496d8e · 0496d8e
1 parent 38346bb
commit 0496d8e
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Showing 6 changed files with 34 additions and 34 deletions.
diff --git a/fpga/modules/operator/src/calc_phase_inc.sv b/fpga/modules/operator/src/calc_phase_inc.sv
@@ -59,37 +59,37 @@ module calc_phase_inc
     localparam PIPELINE_DELAY = 2;
 
     logic signed [PHASE_ACC_WIDTH-1:0] pre_mult_p0;
-    logic signed [PHASE_ACC_WIDTH-1:0] post_mult_p1 = 0;
+    logic signed [PHASE_ACC_WIDTH-1:0] pre_mult_p1 = 0;
     logic signed [PHASE_ACC_WIDTH-1:0] post_mult_p2 = 0;
-    logic signed [VIB_VAL_WIDTH-1:0] vib_val_p2;
+    logic [VIB_VAL_WIDTH-1:0] vib_val_p2;
     logic [PIPELINE_DELAY:1] vib_p;
-    logic [$clog2(30)-1:0] multiplier_p0;
+    logic [$clog2(30)-1:0] multiplier_p1 = 0;
 
     always_comb pre_mult_p0 = fnum << block;
 
-    always_comb
+    always_ff @(posedge clk)
         unique case (mult)
-        'h0: multiplier_p0 = 1;
-        'h1: multiplier_p0 = 2;
-        'h2: multiplier_p0 = 4;
-        'h3: multiplier_p0 = 6;
-        'h4: multiplier_p0 = 8;
-        'h5: multiplier_p0 = 10;
-        'h6: multiplier_p0 = 12;
-        'h7: multiplier_p0 = 14;
-        'h8: multiplier_p0 = 16;
-        'h9: multiplier_p0 = 18;
-        'hA: multiplier_p0 = 20;
-        'hB: multiplier_p0 = 20;
-        'hC: multiplier_p0 = 24;
-        'hD: multiplier_p0 = 24;
-        'hE: multiplier_p0 = 30;
-        'hF: multiplier_p0 = 30;
+        'h0: multiplier_p1 <= 1;
+        'h1: multiplier_p1 <= 2;
+        'h2: multiplier_p1 <= 4;
+        'h3: multiplier_p1 <= 6;
+        'h4: multiplier_p1 <= 8;
+        'h5: multiplier_p1 <= 10;
+        'h6: multiplier_p1 <= 12;
+        'h7: multiplier_p1 <= 14;
+        'h8: multiplier_p1 <= 16;
+        'h9: multiplier_p1 <= 18;
+        'hA: multiplier_p1 <= 20;
+        'hB: multiplier_p1 <= 20;
+        'hC: multiplier_p1 <= 24;
+        'hD: multiplier_p1 <= 24;
+        'hE: multiplier_p1 <= 30;
+        'hF: multiplier_p1 <= 30;
         endcase
 
     always_ff @(posedge clk) begin
-        post_mult_p1 <= (pre_mult_p0*multiplier_p0) >> 1;
-        post_mult_p2 <= post_mult_p1;
+        pre_mult_p1 <= pre_mult_p0;
+        post_mult_p2 <= (pre_mult_p1*multiplier_p1) >> 1;
     end
 
     pipeline_sr #(

diff --git a/fpga/modules/operator/src/envelope_generator.sv b/fpga/modules/operator/src/envelope_generator.sv
@@ -84,10 +84,11 @@ module envelope_generator
     logic [ENV_WIDTH-1:0] env_int_p0;
     logic [ENV_WIDTH-1:0] env_int_p1 = 0;
     logic [ENV_WIDTH-1:0] env_int_p2 = 0;
+    logic [ENV_WIDTH:0] env_add_p1; // one more bit for overflow check
     logic [AM_VAL_WIDTH-1:0] am_val_p2;
     logic [REG_ENV_WIDTH-1:0] requested_rate_p0;
     logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_counter_overflow_p1;
-    logic signed [ENV_WIDTH+3-1:0] env_tmp_p2; // three more bits wide than env for >, < comparison
+    logic [ENV_WIDTH+1:0] env_tmp_p2; // two more bits wide than env for overflow check
     logic [PIPELINE_DELAY:1] sample_clk_en_p;
     logic [PIPELINE_DELAY:1] [BANK_NUM_WIDTH-1:0] bank_num_p;
     logic [PIPELINE_DELAY:1] [OP_NUM_WIDTH-1:0] op_num_p;
@@ -201,6 +202,8 @@ module envelope_generator
         .dob(env_int_p0)
     );
 
+    always_comb env_add_p1 = env_int_p1 + rate_counter_overflow_p1;
+
     always_ff @(posedge clk) begin
         env_int_p1 <= env_int_p0;
         env_int_p2 <= env_int_p1;
@@ -217,11 +220,11 @@ module envelope_generator
                 // +1 for one's complement.
                 env_int_p2 <= env_int_p1 - (((env_int_p1*rate_counter_overflow_p1) >> 3) + 1);
             else if (state_p1 == DECAY || state_p1 == RELEASE) begin
-                if ((ENV_WIDTH+1)'(env_int_p1) + rate_counter_overflow_p1 > SILENCE)
+                if (env_add_p1[ENV_WIDTH])
                     // env_int would overflow
                     env_int_p2 <= SILENCE;
                 else
-                    env_int_p2 <= env_int_p1 + rate_counter_overflow_p1;
+                    env_int_p2 <= env_add_p1;
             end
         end
     end
@@ -235,17 +238,15 @@ module envelope_generator
 
     always_comb
         if (am)
-            env_tmp_p2 = env_int_p2 + (tl_p[2] << 2) + ksl_add_p2 + am_val_p2;
+            env_tmp_p2 = env_int_p2 + (tl_p[2] << 2) + ksl_add_p2 + am_val_p2; // max val 1044
         else
             env_tmp_p2 = env_int_p2 + (tl_p[2] << 2) + ksl_add_p2;
 
     // clamp envelope
     always_ff @(posedge clk)
-        if (env_tmp_p2 < 0)
-            env_p3 <= 0;
-        else if (env_tmp_p2 > SILENCE)
+        if (env_tmp_p2[ENV_WIDTH+1:ENV_WIDTH] != 0) // overflow
             env_p3 <= SILENCE;
         else
             env_p3 <= env_tmp_p2;
 endmodule
-`default_nettype wire
+`default_nettype wire
diff --git a/fpga/modules/operator/src/phase_generator.sv b/fpga/modules/operator/src/phase_generator.sv
@@ -68,7 +68,6 @@ module phase_generator
     logic [PHASE_ACC_WIDTH-1:0] phase_acc_p2;
     logic [PHASE_ACC_WIDTH-1:0] phase_acc_p3 = 0;
     logic [PHASE_ACC_WIDTH-1:0] final_phase_p4 = 0;
-    logic [PHASE_ACC_WIDTH-1:0] final_phase_p4 = 0;
     logic [PHASE_ACC_WIDTH-1:0] final_phase_p5 = 0;
     logic prev_final_phase_msb_p2;
     logic prev_final_phase_msb_p3 = 0;
@@ -283,7 +282,6 @@ module phase_generator
     always_comb log_sin_plus_gain_p5 = (ws_post_opl_p[5] == 7 ? tmp_ws7_p5 : log_sin_out_p5) + (env_p5 << 3);
 
     always_ff @(posedge clk) begin
-        final_phase_p4 <= final_phase_p4;
         final_phase_p5 <= final_phase_p4;
         log_sin_plus_gain_p6 <= log_sin_plus_gain_p5;
     end

diff --git a/fpga/modules/top_level/pkg/opl3_pkg.sv b/fpga/modules/top_level/pkg/opl3_pkg.sv
@@ -81,7 +81,7 @@ package opl3_pkg;
     localparam ENV_RATE_COUNTER_OVERFLOW_WIDTH = $clog2(7);
     localparam TREMOLO_MAX_COUNT = 13*1024;
     localparam TREMOLO_INDEX_WIDTH = $clog2(TREMOLO_MAX_COUNT);
-    localparam AM_VAL_WIDTH = TREMOLO_INDEX_WIDTH - 8 + 1;
+    localparam AM_VAL_WIDTH = TREMOLO_INDEX_WIDTH - 8;
     localparam KSL_ADD_WIDTH = 8;
 
     localparam NUM_BANKS = 2;

diff --git a/fpga/modules/top_level/sim/opl3_tb.sv b/fpga/modules/top_level/sim/opl3_tb.sv
@@ -77,6 +77,7 @@ module opl3_tb
     end
 
     opl3 opl3 (
+        .clk_dac('0),
         .*
     );
 

diff --git a/fpga/modules/top_level/src/opl3.sv b/fpga/modules/top_level/src/opl3.sv
@@ -46,7 +46,7 @@ module opl3
 (
     input wire clk, // opl3 clk
     input wire clk_host,
-    input wire clk_dac,
+    input wire clk_dac, // only used if INSTANTIATE_SAMPLE_SYNC_TO_DAC_CLK is set
     input wire ic_n, // clk_host reset
     input wire cs_n,
     input wire rd_n,
-Original file line number
+Diff line change
@@ Expand Up / @@ -77,6 +77,7 @@ module opl3_tb @@
         end
         opl3 opl3 (
+            .clk_dac('0),
             .*
         );
@@ Expand Down @@