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0026-kernel-backport-spi-nor-driver-from-4.4.9.patch
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0026-kernel-backport-spi-nor-driver-from-4.4.9.patch
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From: Matthias Schiffer <[email protected]>
Date: Sat, 7 May 2016 00:07:51 +0200
Subject: kernel: backport spi-nor driver from 4.4.9
diff --git a/target/linux/ar71xx/patches-3.18/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch b/target/linux/ar71xx/patches-3.18/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
index 568f516..6a91320 100644
--- a/target/linux/ar71xx/patches-3.18/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
+++ b/target/linux/ar71xx/patches-3.18/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
@@ -1,11 +1,11 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
-@@ -246,7 +246,9 @@ static int m25p_probe(struct spi_device
+@@ -229,7 +229,9 @@ static int m25p_probe(struct spi_device
ppdata.of_node = spi->dev.of_node;
-- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
-+ return mtd_device_parse_register(&flash->mtd,
+- return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
++ return mtd_device_parse_register(&nor->mtd,
+ data ? data->part_probes : NULL,
+ &ppdata,
data ? data->parts : NULL,
diff --git a/target/linux/ar71xx/patches-3.18/412-mtd-m25p80-zero-partition-parser-data.patch b/target/linux/ar71xx/patches-3.18/412-mtd-m25p80-zero-partition-parser-data.patch
index d51694d..175acf6 100644
--- a/target/linux/ar71xx/patches-3.18/412-mtd-m25p80-zero-partition-parser-data.patch
+++ b/target/linux/ar71xx/patches-3.18/412-mtd-m25p80-zero-partition-parser-data.patch
@@ -1,10 +1,10 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
-@@ -244,6 +244,7 @@ static int m25p_probe(struct spi_device
+@@ -227,6 +227,7 @@ static int m25p_probe(struct spi_device
if (ret)
return ret;
+ memset(&ppdata, '\0', sizeof(ppdata));
ppdata.of_node = spi->dev.of_node;
- return mtd_device_parse_register(&flash->mtd,
+ return mtd_device_parse_register(&nor->mtd,
diff --git a/target/linux/ar71xx/patches-3.18/462-mtd-m25p80-set-spi-transfer-type.patch b/target/linux/ar71xx/patches-3.18/462-mtd-m25p80-set-spi-transfer-type.patch
index 3320e5b..11bf9ff 100644
--- a/target/linux/ar71xx/patches-3.18/462-mtd-m25p80-set-spi-transfer-type.patch
+++ b/target/linux/ar71xx/patches-3.18/462-mtd-m25p80-set-spi-transfer-type.patch
@@ -1,6 +1,6 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
-@@ -142,10 +142,12 @@ static int m25p80_read(struct spi_nor *n
+@@ -137,10 +137,12 @@ static int m25p80_read(struct spi_nor *n
flash->command[0] = nor->read_opcode;
m25p_addr2cmd(nor, from, flash->command);
diff --git a/target/linux/ar71xx/patches-3.18/464-spi-ath79-fix-fast-flash-read.patch b/target/linux/ar71xx/patches-3.18/464-spi-ath79-fix-fast-flash-read.patch
index e48665d..758d231 100644
--- a/target/linux/ar71xx/patches-3.18/464-spi-ath79-fix-fast-flash-read.patch
+++ b/target/linux/ar71xx/patches-3.18/464-spi-ath79-fix-fast-flash-read.patch
@@ -1,6 +1,6 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
-@@ -142,6 +142,9 @@ static int m25p80_read(struct spi_nor *n
+@@ -137,6 +137,9 @@ static int m25p80_read(struct spi_nor *n
flash->command[0] = nor->read_opcode;
m25p_addr2cmd(nor, from, flash->command);
@@ -25,7 +25,7 @@
while (len--) {
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
-@@ -637,6 +637,7 @@ struct spi_transfer {
+@@ -633,6 +633,7 @@ struct spi_transfer {
u16 delay_usecs;
u32 speed_hz;
enum spi_transfer_type type;
diff --git a/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch b/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch
index b949694..be62e67 100644
--- a/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch
+++ b/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch
@@ -11,12 +11,12 @@ Signed-off-by: Jonas Gorski <[email protected]>
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
-@@ -246,7 +246,8 @@ static int m25p_probe(struct spi_device
+@@ -229,7 +229,8 @@ static int m25p_probe(struct spi_device
ppdata.of_node = spi->dev.of_node;
-- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
-+ return mtd_device_parse_register(&flash->mtd,
+- return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
++ return mtd_device_parse_register(&nor->mtd,
+ data ? data->part_probe_types : NULL, &ppdata,
data ? data->parts : NULL,
data ? data->nr_parts : 0);
diff --git a/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch b/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch
index 740fb2d..3877442 100644
--- a/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch
+++ b/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch
@@ -11,15 +11,15 @@ Signed-off-by: Jonas Gorski <[email protected]>
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
-@@ -32,6 +32,7 @@ struct m25p {
+@@ -31,6 +31,7 @@
+ struct m25p {
struct spi_device *spi;
struct spi_nor spi_nor;
- struct mtd_info mtd;
+ int max_transfer_len;
u8 command[MAX_CMD_SIZE];
};
-@@ -121,7 +122,7 @@ static inline unsigned int m25p80_rx_nbi
+@@ -119,7 +120,7 @@ static inline unsigned int m25p80_rx_nbi
* Read an address range from the nor chip. The address range
* may be any size provided it is within the physical boundaries.
*/
@@ -28,7 +28,7 @@ Signed-off-by: Jonas Gorski <[email protected]>
size_t *retlen, u_char *buf)
{
struct m25p *flash = nor->priv;
-@@ -157,6 +158,29 @@ static int m25p80_read(struct spi_nor *n
+@@ -152,6 +153,29 @@ static int m25p80_read(struct spi_nor *n
return 0;
}
@@ -58,7 +58,7 @@ Signed-off-by: Jonas Gorski <[email protected]>
static int m25p80_erase(struct spi_nor *nor, loff_t offset)
{
struct m25p *flash = nor->priv;
-@@ -240,6 +264,9 @@ static int m25p_probe(struct spi_device
+@@ -223,6 +247,9 @@ static int m25p_probe(struct spi_device
else
flash_name = spi->modalias;
diff --git a/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch b/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch
index b7bf57f..e421e9a 100644
--- a/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch
+++ b/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch
@@ -10,7 +10,7 @@ Subject: [PATCH 64/79] MTD: m25p80: allow passing pp_data
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
-@@ -267,6 +267,9 @@ static int m25p_probe(struct spi_device
+@@ -250,6 +250,9 @@ static int m25p_probe(struct spi_device
if (data)
flash->max_transfer_len = data->max_transfer_len;
diff --git a/target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch b/target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch
deleted file mode 100644
index 4d0403b..0000000
--- a/target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/drivers/mtd/spi-nor/spi-nor.c
-+++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -510,6 +510,7 @@ static const struct spi_device_id spi_no
- /* GigaDevice */
- { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
- { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
-+ { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
-
- /* Intel/Numonyx -- xxxs33b */
- { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
diff --git a/target/linux/generic/patches-3.18/093-m25p80_spi-nor_update_to_4.4.9.patch b/target/linux/generic/patches-3.18/093-m25p80_spi-nor_update_to_4.4.9.patch
new file mode 100644
index 0000000..5f74d3a
--- /dev/null
+++ b/target/linux/generic/patches-3.18/093-m25p80_spi-nor_update_to_4.4.9.patch
@@ -0,0 +1,1579 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -31,7 +31,6 @@
+ struct m25p {
+ struct spi_device *spi;
+ struct spi_nor spi_nor;
+- struct mtd_info mtd;
+ u8 command[MAX_CMD_SIZE];
+ };
+
+@@ -62,8 +61,7 @@ static int m25p_cmdsz(struct spi_nor *no
+ return 1 + nor->addr_width;
+ }
+
+-static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
+- int wr_en)
++static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+ {
+ struct m25p *flash = nor->priv;
+ struct spi_device *spi = flash->spi;
+@@ -128,13 +126,10 @@ static int m25p80_read(struct spi_nor *n
+ struct spi_device *spi = flash->spi;
+ struct spi_transfer t[2];
+ struct spi_message m;
+- int dummy = nor->read_dummy;
+- int ret;
++ unsigned int dummy = nor->read_dummy;
+
+- /* Wait till previous write/erase is done. */
+- ret = nor->wait_till_ready(nor);
+- if (ret)
+- return ret;
++ /* convert the dummy cycles to the number of bytes */
++ dummy /= 8;
+
+ spi_message_init(&m);
+ memset(t, 0, (sizeof t));
+@@ -160,20 +155,9 @@ static int m25p80_read(struct spi_nor *n
+ static int m25p80_erase(struct spi_nor *nor, loff_t offset)
+ {
+ struct m25p *flash = nor->priv;
+- int ret;
+
+ dev_dbg(nor->dev, "%dKiB at 0x%08x\n",
+- flash->mtd.erasesize / 1024, (u32)offset);
+-
+- /* Wait until finished previous write command. */
+- ret = nor->wait_till_ready(nor);
+- if (ret)
+- return ret;
+-
+- /* Send write enable, then erase commands. */
+- ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
+- if (ret)
+- return ret;
++ flash->spi_nor.mtd.erasesize / 1024, (u32)offset);
+
+ /* Set up command buffer. */
+ flash->command[0] = nor->erase_opcode;
+@@ -215,11 +199,10 @@ static int m25p_probe(struct spi_device
+ nor->read_reg = m25p80_read_reg;
+
+ nor->dev = &spi->dev;
+- nor->mtd = &flash->mtd;
++ nor->flash_node = spi->dev.of_node;
+ nor->priv = flash;
+
+ spi_set_drvdata(spi, flash);
+- flash->mtd.priv = nor;
+ flash->spi = spi;
+
+ if (spi->mode & SPI_RX_QUAD)
+@@ -228,7 +211,7 @@ static int m25p_probe(struct spi_device
+ mode = SPI_NOR_DUAL;
+
+ if (data && data->name)
+- flash->mtd.name = data->name;
++ nor->mtd.name = data->name;
+
+ /* For some (historical?) reason many platforms provide two different
+ * names in flash_platform_data: "name" and "type". Quite often name is
+@@ -246,7 +229,7 @@ static int m25p_probe(struct spi_device
+
+ ppdata.of_node = spi->dev.of_node;
+
+- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
++ return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
+ data ? data->parts : NULL,
+ data ? data->nr_parts : 0);
+ }
+@@ -257,64 +240,68 @@ static int m25p_remove(struct spi_device
+ struct m25p *flash = spi_get_drvdata(spi);
+
+ /* Clean up MTD stuff. */
+- return mtd_device_unregister(&flash->mtd);
++ return mtd_device_unregister(&flash->spi_nor.mtd);
+ }
+
+-
+ /*
+- * XXX This needs to be kept in sync with spi_nor_ids. We can't share
+- * it with spi-nor, because if this is built as a module then modpost
+- * won't be able to read it and add appropriate aliases.
++ * Do NOT add to this array without reading the following:
++ *
++ * Historically, many flash devices are bound to this driver by their name. But
++ * since most of these flash are compatible to some extent, and their
++ * differences can often be differentiated by the JEDEC read-ID command, we
++ * encourage new users to add support to the spi-nor library, and simply bind
++ * against a generic string here (e.g., "jedec,spi-nor").
++ *
++ * Many flash names are kept here in this list (as well as in spi-nor.c) to
++ * keep them available as module aliases for existing platforms.
+ */
+ static const struct spi_device_id m25p_ids[] = {
+- {"at25fs010"}, {"at25fs040"}, {"at25df041a"}, {"at25df321a"},
+- {"at25df641"}, {"at26f004"}, {"at26df081a"}, {"at26df161a"},
+- {"at26df321"}, {"at45db081d"},
+- {"en25f32"}, {"en25p32"}, {"en25q32b"}, {"en25p64"},
+- {"en25q64"}, {"en25qh128"}, {"en25qh256"},
+- {"f25l32pa"},
+- {"mr25h256"}, {"mr25h10"},
+- {"gd25q32"}, {"gd25q64"},
+- {"160s33b"}, {"320s33b"}, {"640s33b"},
+- {"mx25l2005a"}, {"mx25l4005a"}, {"mx25l8005"}, {"mx25l1606e"},
+- {"mx25l3205d"}, {"mx25l3255e"}, {"mx25l6405d"}, {"mx25l12805d"},
+- {"mx25l12855e"},{"mx25l25635e"},{"mx25l25655e"},{"mx66l51235l"},
+- {"mx66l1g55g"},
+- {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q256a"},
+- {"n25q512a"}, {"n25q512ax3"}, {"n25q00"},
+- {"pm25lv512"}, {"pm25lv010"}, {"pm25lq032"},
+- {"s25sl032p"}, {"s25sl064p"}, {"s25fl256s0"}, {"s25fl256s1"},
+- {"s25fl512s"}, {"s70fl01gs"}, {"s25sl12800"}, {"s25sl12801"},
+- {"s25fl129p0"}, {"s25fl129p1"}, {"s25sl004a"}, {"s25sl008a"},
+- {"s25sl016a"}, {"s25sl032a"}, {"s25sl064a"}, {"s25fl008k"},
+- {"s25fl016k"}, {"s25fl064k"},
+- {"sst25vf040b"},{"sst25vf080b"},{"sst25vf016b"},{"sst25vf032b"},
+- {"sst25vf064c"},{"sst25wf512"}, {"sst25wf010"}, {"sst25wf020"},
+- {"sst25wf040"},
+- {"m25p05"}, {"m25p10"}, {"m25p20"}, {"m25p40"},
+- {"m25p80"}, {"m25p16"}, {"m25p32"}, {"m25p64"},
+- {"m25p128"}, {"n25q032"},
++ /*
++ * Entries not used in DTs that should be safe to drop after replacing
++ * them with "nor-jedec" in platform data.
++ */
++ {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
++
++ /*
++ * Entries that were used in DTs without "nor-jedec" fallback and should
++ * be kept for backward compatibility.
++ */
++ {"at25df321a"}, {"at25df641"}, {"at26df081a"},
++ {"mr25h256"},
++ {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
++ {"mx25l25635e"},{"mx66l51235l"},
++ {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
++ {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
++ {"s25fl064k"},
++ {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
++ {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
++ {"m25p64"}, {"m25p128"},
++ {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
++ {"w25q80bl"}, {"w25q128"}, {"w25q256"},
++
++ /* Flashes that can't be detected using JEDEC */
+ {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
+ {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
+ {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
+- {"m45pe10"}, {"m45pe80"}, {"m45pe16"},
+- {"m25pe20"}, {"m25pe80"}, {"m25pe16"},
+- {"m25px16"}, {"m25px32"}, {"m25px32-s0"}, {"m25px32-s1"},
+- {"m25px64"}, {"m25px80"},
+- {"w25x10"}, {"w25x20"}, {"w25x40"}, {"w25x80"},
+- {"w25x16"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
+- {"w25x64"}, {"w25q64"}, {"w25q80"}, {"w25q80bl"},
+- {"w25q128"}, {"w25q256"}, {"cat25c11"},
+- {"cat25c03"}, {"cat25c09"}, {"cat25c17"}, {"cat25128"},
++
+ { },
+ };
+ MODULE_DEVICE_TABLE(spi, m25p_ids);
+
++static const struct of_device_id m25p_of_table[] = {
++ /*
++ * Generic compatibility for SPI NOR that can be identified by the
++ * JEDEC READ ID opcode (0x9F). Use this, if possible.
++ */
++ { .compatible = "jedec,spi-nor" },
++ {}
++};
++MODULE_DEVICE_TABLE(of, m25p_of_table);
+
+ static struct spi_driver m25p80_driver = {
+ .driver = {
+ .name = "m25p80",
+- .owner = THIS_MODULE,
++ .of_match_table = m25p_of_table,
+ },
+ .id_table = m25p_ids,
+ .probe = m25p_probe,
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -16,19 +16,63 @@
+ #include <linux/device.h>
+ #include <linux/mutex.h>
+ #include <linux/math64.h>
++#include <linux/sizes.h>
+
+-#include <linux/mtd/cfi.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/of_platform.h>
+ #include <linux/spi/flash.h>
+ #include <linux/mtd/spi-nor.h>
+
+ /* Define max times to check status register before we give up. */
+-#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
+
+-#define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
++/*
++ * For everything but full-chip erase; probably could be much smaller, but kept
++ * around for safety for now
++ */
++#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
++
++/*
++ * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
++ * for larger flash
++ */
++#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
++
++#define SPI_NOR_MAX_ID_LEN 6
++
++struct flash_info {
++ char *name;
++
++ /*
++ * This array stores the ID bytes.
++ * The first three bytes are the JEDIC ID.
++ * JEDEC ID zero means "no ID" (mostly older chips).
++ */
++ u8 id[SPI_NOR_MAX_ID_LEN];
++ u8 id_len;
++
++ /* The size listed here is what works with SPINOR_OP_SE, which isn't
++ * necessarily called a "sector" by the vendor.
++ */
++ unsigned sector_size;
++ u16 n_sectors;
++
++ u16 page_size;
++ u16 addr_width;
++
++ u16 flags;
++#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
++#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
++#define SST_WRITE 0x04 /* use SST byte programming */
++#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
++#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
++#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
++#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
++#define USE_FSR 0x80 /* use flag status register */
++};
+
+-static const struct spi_device_id *spi_nor_match_id(const char *name);
++#define JEDEC_MFR(info) ((info)->id[0])
++
++static const struct flash_info *spi_nor_match_id(const char *name);
+
+ /*
+ * Read the status register, returning its value in the location
+@@ -98,7 +142,7 @@ static inline int spi_nor_read_dummy_cyc
+ case SPI_NOR_FAST:
+ case SPI_NOR_DUAL:
+ case SPI_NOR_QUAD:
+- return 1;
++ return 8;
+ case SPI_NOR_NORMAL:
+ return 0;
+ }
+@@ -112,7 +156,7 @@ static inline int spi_nor_read_dummy_cyc
+ static inline int write_sr(struct spi_nor *nor, u8 val)
+ {
+ nor->cmd_buf[0] = val;
+- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
++ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
+ }
+
+ /*
+@@ -121,7 +165,7 @@ static inline int write_sr(struct spi_no
+ */
+ static inline int write_enable(struct spi_nor *nor)
+ {
+- return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
++ return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
+ }
+
+ /*
+@@ -129,7 +173,7 @@ static inline int write_enable(struct sp
+ */
+ static inline int write_disable(struct spi_nor *nor)
+ {
+- return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
++ return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
+ }
+
+ static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
+@@ -138,23 +182,24 @@ static inline struct spi_nor *mtd_to_spi
+ }
+
+ /* Enable/disable 4-byte addressing mode. */
+-static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable)
++static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
++ int enable)
+ {
+ int status;
+ bool need_wren = false;
+ u8 cmd;
+
+- switch (JEDEC_MFR(jedec_id)) {
+- case CFI_MFR_ST: /* Micron, actually */
++ switch (JEDEC_MFR(info)) {
++ case SNOR_MFR_MICRON:
+ /* Some Micron need WREN command; all will accept it */
+ need_wren = true;
+- case CFI_MFR_MACRONIX:
+- case 0xEF /* winbond */:
++ case SNOR_MFR_MACRONIX:
++ case SNOR_MFR_WINBOND:
+ if (need_wren)
+ write_enable(nor);
+
+ cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
+- status = nor->write_reg(nor, cmd, NULL, 0, 0);
++ status = nor->write_reg(nor, cmd, NULL, 0);
+ if (need_wren)
+ write_disable(nor);
+
+@@ -162,63 +207,73 @@ static inline int set_4byte(struct spi_n
+ default:
+ /* Spansion style */
+ nor->cmd_buf[0] = enable << 7;
+- return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
++ return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
+ }
+ }
+-
+-static int spi_nor_wait_till_ready(struct spi_nor *nor)
++static inline int spi_nor_sr_ready(struct spi_nor *nor)
+ {
+- unsigned long deadline;
+- int sr;
+-
+- deadline = jiffies + MAX_READY_WAIT_JIFFIES;
+-
+- do {
+- cond_resched();
++ int sr = read_sr(nor);
++ if (sr < 0)
++ return sr;
++ else
++ return !(sr & SR_WIP);
++}
+
+- sr = read_sr(nor);
+- if (sr < 0)
+- break;
+- else if (!(sr & SR_WIP))
+- return 0;
+- } while (!time_after_eq(jiffies, deadline));
++static inline int spi_nor_fsr_ready(struct spi_nor *nor)
++{
++ int fsr = read_fsr(nor);
++ if (fsr < 0)
++ return fsr;
++ else
++ return fsr & FSR_READY;
++}
+
+- return -ETIMEDOUT;
++static int spi_nor_ready(struct spi_nor *nor)
++{
++ int sr, fsr;
++ sr = spi_nor_sr_ready(nor);
++ if (sr < 0)
++ return sr;
++ fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
++ if (fsr < 0)
++ return fsr;
++ return sr && fsr;
+ }
+
+-static int spi_nor_wait_till_fsr_ready(struct spi_nor *nor)
++/*
++ * Service routine to read status register until ready, or timeout occurs.
++ * Returns non-zero if error.
++ */
++static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
++ unsigned long timeout_jiffies)
+ {
+ unsigned long deadline;
+- int sr;
+- int fsr;
++ int timeout = 0, ret;
+
+- deadline = jiffies + MAX_READY_WAIT_JIFFIES;
++ deadline = jiffies + timeout_jiffies;
++
++ while (!timeout) {
++ if (time_after_eq(jiffies, deadline))
++ timeout = 1;
++
++ ret = spi_nor_ready(nor);
++ if (ret < 0)
++ return ret;
++ if (ret)
++ return 0;
+
+- do {
+ cond_resched();
++ }
+
+- sr = read_sr(nor);
+- if (sr < 0) {
+- break;
+- } else if (!(sr & SR_WIP)) {
+- fsr = read_fsr(nor);
+- if (fsr < 0)
+- break;
+- if (fsr & FSR_READY)
+- return 0;
+- }
+- } while (!time_after_eq(jiffies, deadline));
++ dev_err(nor->dev, "flash operation timed out\n");
+
+ return -ETIMEDOUT;
+ }
+
+-/*
+- * Service routine to read status register until ready, or timeout occurs.
+- * Returns non-zero if error.
+- */
+-static int wait_till_ready(struct spi_nor *nor)
++static int spi_nor_wait_till_ready(struct spi_nor *nor)
+ {
+- return nor->wait_till_ready(nor);
++ return spi_nor_wait_till_ready_with_timeout(nor,
++ DEFAULT_READY_WAIT_JIFFIES);
+ }
+
+ /*
+@@ -228,19 +283,9 @@ static int wait_till_ready(struct spi_no
+ */
+ static int erase_chip(struct spi_nor *nor)
+ {
+- int ret;
+-
+- dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
++ dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
+
+- /* Wait until finished previous write command. */
+- ret = wait_till_ready(nor);
+- if (ret)
+- return ret;
+-
+- /* Send write enable, then erase commands. */
+- write_enable(nor);
+-
+- return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
++ return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
+ }
+
+ static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
+@@ -294,11 +339,28 @@ static int spi_nor_erase(struct mtd_info
+
+ /* whole-chip erase? */
+ if (len == mtd->size) {
++ unsigned long timeout;
++
++ write_enable(nor);
++
+ if (erase_chip(nor)) {
+ ret = -EIO;
+ goto erase_err;
+ }
+
++ /*
++ * Scale the timeout linearly with the size of the flash, with
++ * a minimum calibrated to an old 2MB flash. We could try to
++ * pull these from CFI/SFDP, but these values should be good
++ * enough for now.
++ */
++ timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
++ CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
++ (unsigned long)(mtd->size / SZ_2M));
++ ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
++ if (ret)
++ goto erase_err;
++
+ /* REVISIT in some cases we could speed up erasing large regions
+ * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
+ * to use "small sector erase", but that's not always optimal.
+@@ -307,6 +369,8 @@ static int spi_nor_erase(struct mtd_info
+ /* "sector"-at-a-time erase */
+ } else {
+ while (len) {
++ write_enable(nor);
++
+ if (nor->erase(nor, addr)) {
+ ret = -EIO;
+ goto erase_err;
+@@ -314,9 +378,15 @@ static int spi_nor_erase(struct mtd_info
+
+ addr += mtd->erasesize;
+ len -= mtd->erasesize;
++
++ ret = spi_nor_wait_till_ready(nor);
++ if (ret)
++ goto erase_err;
+ }
+ }
+
++ write_disable(nor);
++
+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
+
+ instr->state = MTD_ERASE_DONE;
+@@ -330,152 +400,267 @@ erase_err:
+ return ret;
+ }
+
+-static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
++static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
++ uint64_t *len)
+ {
+- struct spi_nor *nor = mtd_to_spi_nor(mtd);
+- uint32_t offset = ofs;
+- uint8_t status_old, status_new;
+- int ret = 0;
++ struct mtd_info *mtd = &nor->mtd;
++ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
++ int shift = ffs(mask) - 1;
++ int pow;
++
++ if (!(sr & mask)) {
++ /* No protection */
++ *ofs = 0;
++ *len = 0;
++ } else {
++ pow = ((sr & mask) ^ mask) >> shift;
++ *len = mtd->size >> pow;
++ *ofs = mtd->size - *len;
++ }
++}
+
+- ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
+- if (ret)
+- return ret;
++/*
++ * Return 1 if the entire region is locked, 0 otherwise
++ */
++static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
++ u8 sr)
++{
++ loff_t lock_offs;
++ uint64_t lock_len;
+
+- /* Wait until finished previous command */
+- ret = wait_till_ready(nor);
+- if (ret)
+- goto err;
++ stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
++
++ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
++}
++
++/*
++ * Lock a region of the flash. Compatible with ST Micro and similar flash.
++ * Supports only the block protection bits BP{0,1,2} in the status register
++ * (SR). Does not support these features found in newer SR bitfields:
++ * - TB: top/bottom protect - only handle TB=0 (top protect)
++ * - SEC: sector/block protect - only handle SEC=0 (block protect)
++ * - CMP: complement protect - only support CMP=0 (range is not complemented)
++ *
++ * Sample table portion for 8MB flash (Winbond w25q64fw):
++ *
++ * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
++ * --------------------------------------------------------------------------
++ * X | X | 0 | 0 | 0 | NONE | NONE
++ * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
++ * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
++ * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
++ * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
++ * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
++ * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
++ * X | X | 1 | 1 | 1 | 8 MB | ALL
++ *
++ * Returns negative on errors, 0 on success.
++ */
++static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
++{
++ struct mtd_info *mtd = &nor->mtd;
++ u8 status_old, status_new;
++ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
++ u8 shift = ffs(mask) - 1, pow, val;
+
+ status_old = read_sr(nor);
+
+- if (offset < mtd->size - (mtd->size / 2))
+- status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
+- else if (offset < mtd->size - (mtd->size / 4))
+- status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
+- else if (offset < mtd->size - (mtd->size / 8))
+- status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
+- else if (offset < mtd->size - (mtd->size / 16))
+- status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
+- else if (offset < mtd->size - (mtd->size / 32))
+- status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
+- else if (offset < mtd->size - (mtd->size / 64))
+- status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
+- else
+- status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
++ /* SPI NOR always locks to the end */
++ if (ofs + len != mtd->size) {
++ /* Does combined region extend to end? */
++ if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len,
++ status_old))
++ return -EINVAL;
++ len = mtd->size - ofs;
++ }
++
++ /*
++ * Need smallest pow such that:
++ *
++ * 1 / (2^pow) <= (len / size)
++ *
++ * so (assuming power-of-2 size) we do:
++ *
++ * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
++ */
++ pow = ilog2(mtd->size) - ilog2(len);
++ val = mask - (pow << shift);
++ if (val & ~mask)
++ return -EINVAL;
++ /* Don't "lock" with no region! */
++ if (!(val & mask))
++ return -EINVAL;
++
++ status_new = (status_old & ~mask) | val;
+
+ /* Only modify protection if it will not unlock other areas */
+- if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
+- (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
+- write_enable(nor);
+- ret = write_sr(nor, status_new);
+- if (ret)
+- goto err;
++ if ((status_new & mask) <= (status_old & mask))
++ return -EINVAL;
++
++ write_enable(nor);
++ return write_sr(nor, status_new);
++}
++
++/*
++ * Unlock a region of the flash. See stm_lock() for more info
++ *
++ * Returns negative on errors, 0 on success.
++ */
++static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
++{
++ struct mtd_info *mtd = &nor->mtd;
++ uint8_t status_old, status_new;
++ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
++ u8 shift = ffs(mask) - 1, pow, val;
++
++ status_old = read_sr(nor);
++
++ /* Cannot unlock; would unlock larger region than requested */
++ if (stm_is_locked_sr(nor, ofs - mtd->erasesize, mtd->erasesize,
++ status_old))
++ return -EINVAL;
++
++ /*
++ * Need largest pow such that:
++ *
++ * 1 / (2^pow) >= (len / size)
++ *
++ * so (assuming power-of-2 size) we do:
++ *
++ * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
++ */
++ pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len));
++ if (ofs + len == mtd->size) {
++ val = 0; /* fully unlocked */
++ } else {
++ val = mask - (pow << shift);
++ /* Some power-of-two sizes are not supported */
++ if (val & ~mask)
++ return -EINVAL;
+ }
+
+-err:
+- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
+- return ret;
++ status_new = (status_old & ~mask) | val;
++
++ /* Only modify protection if it will not lock other areas */
++ if ((status_new & mask) >= (status_old & mask))
++ return -EINVAL;
++
++ write_enable(nor);
++ return write_sr(nor, status_new);
+ }
+
+-static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
++/*
++ * Check if a region of the flash is (completely) locked. See stm_lock() for
++ * more info.
++ *
++ * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
++ * negative on errors.
++ */
++static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
++{
++ int status;
++
++ status = read_sr(nor);
++ if (status < 0)
++ return status;
++
++ return stm_is_locked_sr(nor, ofs, len, status);
++}
++
++static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+ {
+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
+- uint32_t offset = ofs;
+- uint8_t status_old, status_new;
+- int ret = 0;
++ int ret;
+
+- ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
+ if (ret)
+ return ret;
+
+- /* Wait until finished previous command */
+- ret = wait_till_ready(nor);
+- if (ret)
+- goto err;
++ ret = nor->flash_lock(nor, ofs, len);
+
+- status_old = read_sr(nor);
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
++ return ret;
++}
+
+- if (offset+len > mtd->size - (mtd->size / 64))
+- status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
+- else if (offset+len > mtd->size - (mtd->size / 32))
+- status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
+- else if (offset+len > mtd->size - (mtd->size / 16))
+- status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
+- else if (offset+len > mtd->size - (mtd->size / 8))
+- status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
+- else if (offset+len > mtd->size - (mtd->size / 4))
+- status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
+- else if (offset+len > mtd->size - (mtd->size / 2))
+- status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
+- else
+- status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
++static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
++{
++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
++ int ret;
+
+- /* Only modify protection if it will not lock other areas */
+- if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
+- (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
+- write_enable(nor);
+- ret = write_sr(nor, status_new);
+- if (ret)
+- goto err;
+- }
++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
++ if (ret)
++ return ret;
+
+-err:
+- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
++ ret = nor->flash_unlock(nor, ofs, len);
++
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
+ return ret;
+ }
+
+-struct flash_info {
+- /* JEDEC id zero means "no ID" (most older chips); otherwise it has
+- * a high byte of zero plus three data bytes: the manufacturer id,
+- * then a two byte device id.
+- */
+- u32 jedec_id;
+- u16 ext_id;
++static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
++{
++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
++ int ret;
+
+- /* The size listed here is what works with SPINOR_OP_SE, which isn't
+- * necessarily called a "sector" by the vendor.
+- */
+- unsigned sector_size;
+- u16 n_sectors;
++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
++ if (ret)
++ return ret;
+
+- u16 page_size;
+- u16 addr_width;
++ ret = nor->flash_is_locked(nor, ofs, len);
+
+- u16 flags;
+-#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
+-#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
+-#define SST_WRITE 0x04 /* use SST byte programming */
+-#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
+-#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
+-#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
+-#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
+-#define USE_FSR 0x80 /* use flag status register */